riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed another bug found using vloghammer

This commit is contained in:
Clifford Wolf 2013-07-07 16:49:30 +02:00
parent eff68560a2
commit e8da3ea7b6
2 changed files with 11 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
frontends/ast/genrtlil.cc
View File

@ -798,7 +798,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; is_signed = true; }
if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; is_signed = true; }
{
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint);
RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genRTLIL(width_hint);
int width = width_hint > 0 ? width_hint : left.width;
return binop2rtlil(this, type_name, width, left, right);

10
tests/simple/vloghammer.v Normal file
View File

@ -0,0 +1,10 @@
// test cases found using vloghammer
// https://github.com/cliffordwolf/VlogHammer
module test01(a, y);
input [7:0] a;
output [3:0] y;
assign y = ~a >> 4;
endmodule