mirror of https://github.com/YosysHQ/yosys.git
Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
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3
README
3
README
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@ -265,8 +265,7 @@ Verilog Attributes and non-standard features
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- In addition to the (* ... *) attribute syntax, yosys supports
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the non-standard {* ... *} attribute syntax to set default attributes
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for everything that comes after the {* ... *} statement. (Reset
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by adding an empty {* *} statement.) The preprocessor define
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__YOSYS_ENABLE_DEFATTR__ must be set in order for this feature to be active.
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by adding an empty {* *} statement.)
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Workarounds for known build problems
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@ -45,7 +45,6 @@ using namespace VERILOG_FRONTEND;
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namespace VERILOG_FRONTEND {
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std::vector<std::string> fn_stack;
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std::vector<int> ln_stack;
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bool lexer_feature_defattr;
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}
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%}
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@ -82,9 +81,6 @@ namespace VERILOG_FRONTEND {
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"`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
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"`yosys_enable_defattr" lexer_feature_defattr = true;
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"`yosys_disable_defattr" lexer_feature_defattr = false;
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"`"[a-zA-Z_$][a-zA-Z0-9_$]* {
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frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
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}
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@ -225,8 +221,8 @@ supply1 { return TOK_SUPPLY1; }
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"(*" { return ATTR_BEGIN; }
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"*)" { return ATTR_END; }
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"{*" { if (lexer_feature_defattr) return DEFATTR_BEGIN; else REJECT; }
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"*}" { if (lexer_feature_defattr) return DEFATTR_END; else REJECT; }
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"{*" { return DEFATTR_BEGIN; }
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"*}" { return DEFATTR_END; }
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"**" { return OP_POW; }
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"||" { return OP_LOR; }
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@ -198,13 +198,6 @@ static void input_file(FILE *f, std::string filename)
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input_buffer.insert(it, "`file_pop\n");
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}
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static std::string define_to_feature(std::string defname)
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{
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if (defname == "__YOSYS_ENABLE_DEFATTR__")
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return "defattr";
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return std::string();
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}
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std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::map<std::string, std::string> pre_defines_map, const std::list<std::string> include_dirs)
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{
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std::map<std::string, std::string> defines_map(pre_defines_map);
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@ -298,8 +291,6 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
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std::string name, value;
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skip_spaces();
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name = next_token(true);
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if (!define_to_feature(name).empty())
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output_code.push_back("`yosys_enable_" + define_to_feature(name));
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skip_spaces();
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int newline_count = 0;
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while (!tok.empty()) {
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@ -331,8 +322,6 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
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std::string name;
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skip_spaces();
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name = next_token(true);
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if (!define_to_feature(name).empty())
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output_code.push_back("`yosys_disable_" + define_to_feature(name));
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// printf("undef: >>%s<<\n", name.c_str());
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defines_map.erase(name);
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continue;
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@ -206,8 +206,6 @@ struct VerilogFrontend : public Frontend {
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fp = fmemopen((void*)code_after_preproc.c_str(), code_after_preproc.size(), "r");
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}
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lexer_feature_defattr = false;
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frontend_verilog_yyset_lineno(1);
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frontend_verilog_yyrestart(fp);
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frontend_verilog_yyparse();
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@ -42,9 +42,6 @@ namespace VERILOG_FRONTEND
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// this function converts a Verilog constant to an AST_CONSTANT node
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AST::AstNode *const2ast(std::string code, char case_type = 0);
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// lexer state variables
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extern bool lexer_feature_defattr;
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}
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// the pre-processor
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