mirror of https://github.com/YosysHQ/yosys.git
Correctly convert constants to RTLIL (fixed undef handling)
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@ -905,18 +905,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (width_hint < 0)
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detectSignWidth(width_hint, sign_hint);
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RTLIL::SigChunk chunk;
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chunk.wire = NULL;
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chunk.data.bits = bits;
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chunk.width = bits.size();
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chunk.offset = 0;
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RTLIL::SigSpec sig;
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sig.chunks.push_back(chunk);
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sig.width = chunk.width;
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is_signed = sign_hint;
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return sig;
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return RTLIL::SigSpec(bitsAsConst(width_hint, sign_hint));
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}
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// simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
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