mirror of https://github.com/YosysHQ/yosys.git
Added PRIM_DLATCHRS support to verific front-end
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@ -314,6 +314,16 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
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return true;
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}
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if (inst->Type() == PRIM_DLATCHRS)
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{
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if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
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module->addDlatch(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetControl()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
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else
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module->addDlatchsr(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetControl()), net_map.at(inst->GetSet()), net_map.at(inst->GetReset()),
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net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
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return true;
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}
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#define IN operatorInput(inst, net_map)
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#define IN1 operatorInput1(inst, net_map)
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#define IN2 operatorInput2(inst, net_map)
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