mirror of https://github.com/YosysHQ/yosys.git
Added read_verilog -nodpi
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parent
089c1e176f
commit
e2e092b144
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@ -39,6 +39,14 @@ using namespace VERILOG_FRONTEND;
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static std::vector<std::string> verilog_defaults;
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static std::list<std::vector<std::string>> verilog_defaults_stack;
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static void error_on_dpi_function(AST::AstNode *node)
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{
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if (node->type == AST::AST_DPI_FUNCTION)
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log_error("Found DPI function %s at %s:%d.\n", node->str.c_str(), node->filename.c_str(), node->linenum);
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for (auto child : node->children)
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error_on_dpi_function(child);
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}
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struct VerilogFrontend : public Frontend {
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VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
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virtual void help()
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@ -107,6 +115,9 @@ struct VerilogFrontend : public Frontend {
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log(" -nopp\n");
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log(" do not run the pre-processor\n");
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log("\n");
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log(" -nodpi\n");
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log(" disable DPI-C support\n");
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log("\n");
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log(" -lib\n");
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log(" only create empty blackbox modules. This implies -DBLACKBOX.\n");
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log("\n");
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@ -160,6 +171,7 @@ struct VerilogFrontend : public Frontend {
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bool flag_mem2reg = false;
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bool flag_ppdump = false;
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bool flag_nopp = false;
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bool flag_nodpi = false;
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bool flag_lib = false;
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bool flag_noopt = false;
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bool flag_icells = false;
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@ -229,6 +241,10 @@ struct VerilogFrontend : public Frontend {
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flag_nopp = true;
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continue;
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}
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if (arg == "-nodpi") {
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flag_nodpi = true;
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continue;
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}
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if (arg == "-lib") {
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flag_lib = true;
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defines_map["BLACKBOX"] = string();
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@ -320,6 +336,9 @@ struct VerilogFrontend : public Frontend {
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child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
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}
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if (flag_nodpi)
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error_on_dpi_function(current_ast);
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);
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if (!flag_nopp)
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