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Fixed a bug with autowire bit size 

(removed leftover from when we tried to auto-size the wires)
This commit is contained in:
Clifford Wolf 2015-02-08 00:48:23 +01:00
parent fbb16712f1
commit c8305e3a6d
1 changed files with 3 additions and 9 deletions
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12
frontends/ast/genrtlil.cc
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@ -1294,15 +1294,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// add entries to current_module->connections for assignments (outside of always blocks)
case AST_ASSIGN:
{
if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_AUTOWIRE) {
RTLIL::SigSpec right = children[1]->genRTLIL();
RTLIL::SigSpec left = children[0]->genWidthRTLIL(right.size());
current_module->connect(RTLIL::SigSig(left, right));
} else {
RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
current_module->connect(RTLIL::SigSig(left, right));
}
RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
current_module->connect(RTLIL::SigSig(left, right));
}
break;