Eddie Hung
5db96b8aec
Missing muxpack.o in Makefile
2019-06-25 10:38:42 -07:00
Eddie Hung
6f36ec8ecf
Merge remote-tracking branch 'origin/master' into xaig
2019-06-25 09:33:11 -07:00
Clifford Wolf
add2d415fc
Merge pull request #1130 from YosysHQ/eddie/fix710
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memory_dff: walk through more than one mux for computing read enable
2019-06-25 17:34:44 +02:00
Eddie Hung
42720ef6fe
Fix spacing
2019-06-25 08:33:17 -07:00
Eddie Hung
c4e4902098
Move only one consumer check outside of while loop
2019-06-25 08:29:55 -07:00
Eddie Hung
d2fed0a7f1
nullptr check
2019-06-25 06:06:32 -07:00
Eddie Hung
a19226c174
Fix for abc_scc_break is bus
2019-06-24 22:16:56 -07:00
Eddie Hung
5605002d8a
More meaningful error message
2019-06-24 22:12:55 -07:00
Eddie Hung
babadf5938
Do not use log_id as it strips \\, also fix scc for |wire| > 1
2019-06-24 22:04:22 -07:00
Eddie Hung
49a762ba46
Fix abc9's scc breaker, also break on abc_scc_break attr
2019-06-24 21:53:18 -07:00
Eddie Hung
b7deaceadd
Walk through as many muxes as exist for rd_en
2019-06-24 18:33:06 -07:00
Eddie Hung
4ddc0354c1
Merge remote-tracking branch 'origin/master' into eddie/muxpack
2019-06-22 14:40:55 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
ad296d77ab
Do not rename non LUT cells in abc9
2019-06-21 17:18:04 -07:00
Eddie Hung
e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091
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Add support for partial matches to muxcover
2019-06-21 17:13:41 -07:00
Eddie Hung
545cfbbe0d
Cope with $reduce_or common in case
2019-06-21 12:31:14 -07:00
Eddie Hung
15535112b7
Fix spacing
2019-06-21 11:52:51 -07:00
Eddie Hung
d89d663c92
Add doc
2019-06-21 11:52:28 -07:00
Eddie Hung
641b86d25f
Fix up ExclusiveDatabase with @cliffordwolf's help
2019-06-21 11:45:31 -07:00
Eddie Hung
63eb5cace9
Merge branch 'master' into eddie/muxpack
2019-06-21 11:17:19 -07:00
Clifford Wolf
ec979475e7
Replace "muxcover -freedecode" with "muxcover -dmux=cost"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 19:24:41 +02:00
Eddie Hung
6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
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Improve shregmap to handle case where first flop is common to two chains
2019-06-21 08:56:56 -07:00
Clifford Wolf
c9949dba99
Merge pull request #1117 from bwidawsk/more-home
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Add a few more filename rewrites
2019-06-21 10:13:51 +02:00
Clifford Wolf
9286b6f013
Add "muxcover -freedecode"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 10:02:10 +02:00
Eddie Hung
54f3237720
Fix gcc warning of potentially uninitialised
2019-06-20 22:10:43 -07:00
Clifford Wolf
891ea6512e
Improvements in muxcover
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- Slightly under-estimate cost of decoder muxes
- Prefer larger muxes at tree root at same cost
- Don't double-count input cost for partial muxes
- Add debug log output
2019-06-20 19:47:59 -07:00
Clifford Wolf
40188457d1
Add support for partial matches to muxcover, fixes #1091
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 19:47:59 -07:00
Eddie Hung
0e97e6a00d
Fix simple_abc9/generate test with 1'bx at MSB
2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
3f34779d64
Do not call "setundef -zero" in abc9
2019-06-20 17:38:04 -07:00
Eddie Hung
e63324f5ef
Actually, there might not be any harm in updating sigmap...
2019-06-20 17:03:05 -07:00
Eddie Hung
9c61fb0e0c
Add comment as per @cliffordwolf
2019-06-20 16:57:54 -07:00
Ben Widawsky
8767ec3fbd
Add a few more filename rewrites
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This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"
Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-20 10:27:59 -07:00
Clifford Wolf
477e566e8d
Fix typo, fixes #1095
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 15:34:52 +02:00
Clifford Wolf
06eb87bcb7
Improve shregmap help message, fixes #1113
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 15:23:55 +02:00
Clifford Wolf
2454ad99bf
Refactor "opt_rmdff -sat"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 13:44:21 +02:00
Clifford Wolf
73bd1d59a7
Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046
2019-06-20 13:04:04 +02:00
Clifford Wolf
11ec7b2aec
Fix typo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 12:23:07 +02:00
acw1251
0d888ee7ed
Fixed the help summary line for a few commands
2019-06-19 15:27:04 -04:00
Eddie Hung
96ade54993
Fix bug in #1078 , add entry to CHANGELOG
2019-06-19 09:51:11 -07:00
Clifford Wolf
3da5288ce0
Use input default values in hierarchy pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 11:49:20 +02:00
Eddie Hung
d80678e581
Cleanup
2019-06-17 15:10:33 -07:00
Eddie Hung
3ebba74461
Merge branch 'xaig' into xaig_dff
2019-06-17 13:51:53 -07:00
Eddie Hung
4d6d593fe3
&scorr before &sweep, remove &retime as recommended
2019-06-17 13:32:08 -07:00
Eddie Hung
a474fe937b
Merge branch 'xaig' into xaig_dff
2019-06-17 13:20:19 -07:00
Eddie Hung
63fc879a5f
Copy not move parameters/attributes
2019-06-17 13:19:45 -07:00
Eddie Hung
7dd3a7f161
Merge branch 'xaig' into xaig_dff
2019-06-17 12:58:41 -07:00
Eddie Hung
b45d06d7a3
Fix leak removing cells during ABC integration; also preserve attr
2019-06-17 12:54:24 -07:00
Eddie Hung
5ce672d1c5
Merge remote-tracking branch 'origin/xaig' into xaig_dff
2019-06-17 12:14:55 -07:00
Eddie Hung
7250c57c5a
Re-enable &dc2
2019-06-17 10:28:51 -07:00
Eddie Hung
fb90d8c18c
Cleanup
2019-06-16 09:34:26 -07:00
Eddie Hung
3ed95dae8d
Cleanup
2019-06-15 22:48:16 -07:00
Eddie Hung
416312b9ed
abc9 to recover_init by default
2019-06-15 22:44:45 -07:00
Eddie Hung
2309459605
Do not treat $__ABC_FF_ as a user cell
2019-06-15 19:36:55 -07:00
Eddie Hung
cdfb634977
Cleanup
2019-06-15 18:18:56 -07:00
Eddie Hung
c2f3f116d0
Use $__ABC_FF_ instead of $_FF_
2019-06-15 18:16:14 -07:00
Eddie Hung
a76c8a7ffd
Fix initialisation of flops
2019-06-15 09:46:35 -07:00
Eddie Hung
ac18a76beb
Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues
2019-06-15 09:34:48 -07:00
Eddie Hung
da487c4f31
For now, short $_DFF_[NP]_ from ff_map.v at re-integration
2019-06-15 09:08:18 -07:00
Eddie Hung
2d85725604
Get rid of compiler warnings
2019-06-14 13:07:56 -07:00
Eddie Hung
a632799d5b
Update abc9 -D doc
2019-06-14 12:29:46 -07:00
Eddie Hung
e391fc8e7b
Enable "abc9 -D <num>" for timing-driven synthesis
2019-06-14 12:28:01 -07:00
Eddie Hung
a48b5bfaa5
Further cleanup based on @daveshah1
2019-06-14 12:25:06 -07:00
Eddie Hung
751e640c1d
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-06-14 10:29:16 -07:00
Eddie Hung
a5425a2f7e
Remove extra semicolon
2019-06-14 10:11:34 -07:00
David Shah
9566573054
ecp5: Add abc9 option
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Signed-off-by: David Shah <dave@ds0.me>
2019-06-14 17:15:02 +01:00
Bogdan Vukobratovic
8451cbea89
Move netlist helper module to passes/opt for the time being
2019-06-14 12:14:02 +02:00
Bogdan Vukobratovic
fe651922cb
Merge remote-tracking branch 'upstream/master'
2019-06-14 12:06:57 +02:00
Bogdan Vukobratovic
53695e6729
Prepare for situation when port of the signal cannot be found
2019-06-14 11:39:24 +02:00
Bogdan Vukobratovic
291b36afeb
Some cleanup, revert sat.cc
2019-06-14 11:35:45 +02:00
Bogdan Vukobratovic
8665f48879
Implement disconnection of constant register bits
2019-06-13 19:35:37 +02:00
Eddie Hung
2c40b66785
Rip out all non FPGA stuff from abc9
2019-06-12 16:53:12 -07:00
Eddie Hung
f81a189fb8
Fix spelling
2019-06-12 16:52:09 -07:00
Eddie Hung
90dc4d82de
Revert "For 'stat' do not count modules with abc_box_id"
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This reverts commit b89bb74452
.
2019-06-12 16:51:37 -07:00
Eddie Hung
b3faf0246d
Be more precise when connecting during ABC9 re-integration
2019-06-12 16:04:33 -07:00
Eddie Hung
2e7e73f483
Remove hacky wideports_split from abc9
2019-06-12 15:52:49 -07:00
Eddie Hung
d9974b85e7
Fix compile errors when #if 1 for debug
2019-06-12 15:47:39 -07:00
Bogdan Vukobratovic
d69989b8d2
Rename satgen_algo.h -> algo.h, code cleanup and refactoring
2019-06-12 19:35:05 +02:00
Eddie Hung
8bb67fa67c
Do not call abc9 if no outputs
2019-06-12 10:18:44 -07:00
Eddie Hung
14e870d4c4
More write_xaiger cleanup
2019-06-12 10:00:57 -07:00
Eddie Hung
b21d29598a
Consistency
2019-06-12 09:40:51 -07:00
Eddie Hung
b2c72f74f0
Merge branch 'xc7mux' into xaig
2019-06-12 09:14:27 -07:00
Eddie Hung
afd620fd5f
Typo: wire delay is -W argument
2019-06-12 09:13:53 -07:00
Eddie Hung
2cbcd6224c
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
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This reverts commit a138381ac3
, reversing
changes made to b77c5da769
.
2019-06-12 09:05:02 -07:00
Eddie Hung
882a83c383
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
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This reverts commit eaee250a6e
, reversing
changes made to 935df3569b
.
2019-06-12 09:04:31 -07:00
Eddie Hung
86efe9a616
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
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This reverts commit 2223ca91b0
, reversing
changes made to eaee250a6e
.
2019-06-12 09:01:15 -07:00
Eddie Hung
1e838a8913
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
2019-06-12 08:49:15 -07:00
Eddie Hung
4c9fde87d1
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
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This reverts commit 2dffa4685b
.
2019-06-12 08:48:45 -07:00
Eddie Hung
2dffa4685b
Add "-W' wire delay arg to abc9, use from synth_xilinx
2019-06-11 17:10:47 -07:00
Eddie Hung
6cdea93724
Revert "Try way that doesn't involve creating a new wire"
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This reverts commit 2f427acc9e
.
2019-06-11 16:05:42 -07:00
Eddie Hung
d26646051c
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
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This reverts commit 5174082208
, reversing
changes made to 54379f9872
.
2019-06-11 16:05:27 -07:00
Eddie Hung
5174082208
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
2019-06-11 15:48:41 -07:00
Eddie Hung
2f427acc9e
Try way that doesn't involve creating a new wire
2019-06-11 15:48:20 -07:00
Bogdan Vukobratovic
9892df17ef
Generate satgen instance instead of calling sat pass
2019-06-11 11:47:13 +02:00
Eddie Hung
a138381ac3
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
2019-06-10 16:21:43 -07:00
Eddie Hung
f19aa8d989
If d_bit already in sigbit_chain_next, create extra wire
2019-06-10 16:16:40 -07:00
Eddie Hung
a1d4ae78a0
Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
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This reverts commit 94a5f4e609
.
2019-06-10 14:34:43 -07:00
Eddie Hung
7d27e1e431
Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"
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This reverts commit 45d1bdf83a
.
2019-06-10 14:34:16 -07:00
Eddie Hung
3579d68193
Revert "Refactor to ShregmapTechXilinx7Static"
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This reverts commit e1e37db860
.
2019-06-10 14:34:15 -07:00
Eddie Hung
b6a39351f4
Revert "Add -tech xilinx_static"
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This reverts commit dfe9d95579
.
2019-06-10 14:34:14 -07:00
Eddie Hung
e1dbeb3004
Revert "Continue support for ShregmapTechXilinx7Static"
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This reverts commit 72eda94a66
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2019-06-10 14:34:14 -07:00
Eddie Hung
9d8563178e
Revert "shregmap -tech xilinx_static to handle INIT"
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This reverts commit 935df3569b
.
2019-06-10 14:34:12 -07:00
Eddie Hung
5b999ae68d
Elaborate muxpack doc
2019-06-10 10:32:19 -07:00
Eddie Hung
1dd7e23a20
Merge remote-tracking branch 'origin/master' into eddie/muxpack
2019-06-10 10:28:40 -07:00
Eddie Hung
5a46a0b385
Fine tune aigerparse
2019-06-07 16:57:32 -07:00
Eddie Hung
f705f6a0b5
Comment O(N) -> O(N^2)
2019-06-07 15:39:12 -07:00
Eddie Hung
ba52d9b471
Extend ExclusiveDatabase to query SigSpec-s (for $pmux)
2019-06-07 15:34:16 -07:00
Eddie Hung
9b408838f1
Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results
2019-06-07 14:18:17 -07:00
Eddie Hung
887df8914c
Resolve @cliffordwolf comment on redundant check
2019-06-07 11:37:52 -07:00
Eddie Hung
5ab59cd59e
Resolve @cliffordwolf comment on sigmap
2019-06-07 11:36:19 -07:00
Eddie Hung
30abdaf3b2
Allow muxcover costs to be changed
2019-06-07 08:34:11 -07:00
Eddie Hung
fe4394fb9a
Allow muxcover costs to be changed
2019-06-07 08:30:39 -07:00
Eddie Hung
2223ca91b0
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
2019-06-06 14:22:10 -07:00
Eddie Hung
5c277c6325
Fix and test for balanced case
2019-06-06 14:21:34 -07:00
Eddie Hung
eaee250a6e
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
2019-06-06 14:06:59 -07:00
Eddie Hung
ccdf989025
Support cascading $pmux.A with $mux.A and $mux.B
2019-06-06 13:51:22 -07:00
Eddie Hung
dc7b8c4b94
More cleanup
2019-06-06 12:56:34 -07:00
Eddie Hung
978fda94f6
Fix spacing
2019-06-06 12:46:42 -07:00
Eddie Hung
d2172c6846
Non chain user check using next_sig
2019-06-06 12:44:50 -07:00
Eddie Hung
83450a9489
Move muxpack from passes/techmap to passes/opt
2019-06-06 12:15:13 -07:00
Eddie Hung
3dd0682f29
Update doc
2019-06-06 12:11:59 -07:00
Eddie Hung
3e76e3a6fa
Add tests, fix for !=
2019-06-06 11:54:38 -07:00
Eddie Hung
543dd11c7e
Missing file
2019-06-06 11:03:45 -07:00
Eddie Hung
7bd1c664a6
Initial adaptation of muxpack from shregmap
2019-06-06 10:51:02 -07:00
Clifford Wolf
e4e1cd6930
Merge pull request #1071 from YosysHQ/eddie/fix_1070
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Fix typo in opt_rmdff causing register to be incorrectly removed
2019-06-06 06:50:12 +02:00
Clifford Wolf
50e2dce5e7
Merge pull request #1072 from YosysHQ/eddie/fix_1069
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Error out if no top module given before 'sim'
2019-06-06 06:49:07 +02:00
Eddie Hung
fd8ef128bf
Missing doc for -tech xilinx in shregmap
2019-06-05 14:21:44 -07:00
Eddie Hung
dd134914cc
Error out if no top module given before 'sim'
2019-06-05 14:16:24 -07:00
Eddie Hung
feb2ddb52b
Fix typo in opt_rmdff
2019-06-05 14:08:14 -07:00
Eddie Hung
935df3569b
shregmap -tech xilinx_static to handle INIT
2019-06-05 12:55:59 -07:00
Eddie Hung
72eda94a66
Continue support for ShregmapTechXilinx7Static
2019-06-05 12:33:55 -07:00
Eddie Hung
dfe9d95579
Add -tech xilinx_static
2019-06-05 11:14:14 -07:00
Eddie Hung
e1e37db860
Refactor to ShregmapTechXilinx7Static
2019-06-05 11:08:08 -07:00
Eddie Hung
45d1bdf83a
shregmap -tech xilinx_dynamic to work -params and -enpol
2019-06-05 10:21:57 -07:00
Eddie Hung
a3a80b755c
Merge pull request #1067 from YosysHQ/clifford/fix1065
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Suppress driver-driver conflict warning for unknown cell types
2019-06-05 09:59:05 -07:00
Eddie Hung
bcc0a5d136
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-05 09:56:57 -07:00
Eddie Hung
b5aff1de04
Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux
2019-06-05 09:56:51 -07:00
Clifford Wolf
b33176dafb
Major rewrite of wire selection in setundef -init
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-05 10:26:48 +02:00
Clifford Wolf
6cc60ffd67
Indent fix
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-05 09:53:06 +02:00
Clifford Wolf
00d32eb73d
Merge pull request #999 from jakobwenzel/setundefInitFix
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initialize more registers in setundef -init
2019-06-05 09:50:15 +02:00
Clifford Wolf
4190d7c094
Fix typo in fmcombine log message, fixes #1063
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-05 09:26:44 +02:00
Clifford Wolf
8a6f9977f6
Suppress driver-driver conflict warning for unknown cell types, fixes #1065
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-05 09:14:12 +02:00
Eddie Hung
94a5f4e609
Rename shregmap -tech xilinx -> xilinx_dynamic
2019-06-04 14:34:36 -07:00
Eddie Hung
f81a0ed92e
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-03 23:07:08 -07:00
Eddie Hung
295bd8d0bf
Remove dupe
2019-06-03 12:32:20 -07:00
Eddie Hung
eb08e71bd1
Merge branch 'xaig' into xc7mux
2019-05-31 13:03:03 -07:00
Eddie Hung
a379234f56
Throw out unused code inherited from abc
2019-05-31 12:50:11 -07:00
Clifford Wolf
90ec2cda42
Fix "tee" handling of log_streams
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-31 09:28:51 +02:00
Eddie Hung
4a6b9af227
Fix spelling
2019-05-30 15:50:47 -07:00
Eddie Hung
a44fe3a632
Revert "Re-enable &dc2"
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This reverts commit 8c58c728a7
.
2019-05-30 11:41:50 -07:00
Eddie Hung
0800846e73
Do not double count LUT1s
2019-05-30 11:32:14 -07:00
Eddie Hung
8c58c728a7
Re-enable &dc2
2019-05-30 00:42:41 -07:00
Eddie Hung
2560f92f29
Reduce -W to 160
2019-05-29 23:01:46 -07:00
Eddie Hung
854557814e
Erase all boxes before stitching
2019-05-29 19:17:36 -07:00
Eddie Hung
b955344ecd
Call &if with -W 250
2019-05-29 16:34:52 -07:00
Eddie Hung
ecaa7856e9
Add some debug to abc9
2019-05-29 15:21:41 -07:00
Clifford Wolf
349c47250a
Merge pull request #1049 from YosysHQ/clifford/fix1047
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Do not use shiftmul peepopt pattern when mul result is truncated
2019-05-28 19:02:26 +02:00
Eddie Hung
cdedf51c32
From master
2019-05-28 09:37:50 -07:00
Eddie Hung
914074a07c
Update from master
2019-05-28 09:35:45 -07:00
Eddie Hung
ba9513b325
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-28 09:30:53 -07:00
Eddie Hung
4a76b425cc
Misspell
2019-05-28 08:44:59 -07:00
Clifford Wolf
cb285e4b87
Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 17:17:56 +02:00
Clifford Wolf
ba2185ead8
Refactor hierarchy wand/wor handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 16:43:25 +02:00
Bogdan Vukobratovic
29a78267d7
Fix the regression
2019-05-28 15:45:04 +02:00
Bogdan Vukobratovic
9a468f81c4
Optimizing DFFs whose initial value prevents their value from changing
...
This is a proof of concept implementation that invokes SAT solver via Pass::call
method.
2019-05-28 08:48:21 +02:00
Eddie Hung
89bd6b8504
If driver not found, use LUT2
2019-05-27 23:12:21 -07:00
Eddie Hung
4df37c77fd
Disconnect all ABC boxes too
2019-05-27 19:40:27 -07:00
Eddie Hung
75bd41eaeb
Parse without wideports
2019-05-27 12:22:05 -07:00
Eddie Hung
bf3b8d5e45
Remove mapped_mod when done
2019-05-27 12:19:21 -07:00
Eddie Hung
234156c01a
Instantiate cell type (from sym file) otherwise 'clean' warnings
2019-05-27 12:16:10 -07:00
Eddie Hung
03b289a851
Add 'cinput' and 'coutput' to symbols file for boxes
2019-05-27 11:38:52 -07:00
Stefan Biereigel
816082d5a1
Merge branch 'master' into wandwor
2019-05-27 19:07:46 +02:00
Stefan Biereigel
ed625a3102
move wand/wor resolution into hierarchy pass
2019-05-27 18:00:22 +02:00
Clifford Wolf
2a9c68e2d6
Merge pull request #1026 from YosysHQ/clifford/fix1023
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Keep zero-width wires in opt_clean if and only if they are ports
2019-05-27 13:24:19 +02:00
Eddie Hung
3981eba999
ABC9 to call &sweep
2019-05-26 11:31:35 -07:00
Eddie Hung
086b6560b4
Typo
2019-05-26 03:17:20 -07:00
Eddie Hung
823153e418
Combine ABC_COMMAND_LUT
2019-05-26 02:47:06 -07:00
Eddie Hung
32a4c10c0d
Fix "a" extension
2019-05-26 02:44:36 -07:00
Eddie Hung
d4fb6cac7c
Revert enable check
2019-05-25 12:55:57 -07:00
Eddie Hung
822d0b7789
opt_rmdff to optimise even in presence of enable signal, even removing
2019-05-24 18:30:51 -07:00
Eddie Hung
0d66103cbb
Add comments
2019-05-24 16:33:10 -07:00
Eddie Hung
357b1de6bc
Resolve @cliffordwolf review, set even if !has_init
2019-05-24 16:15:22 -07:00
Eddie Hung
6ad09bfcea
Add &fraig and &mfs back
2019-05-24 15:10:18 -07:00
Eddie Hung
68359bcd6f
Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
2019-05-23 13:37:53 -07:00
Eddie Hung
5ac7e38d0a
Fix spacing
2019-05-23 12:58:30 -07:00
Eddie Hung
50ed34a6d0
opt_rmdff to work on $dffe and $_DFFE_*
2019-05-23 11:26:18 -07:00
Clifford Wolf
e3f9ccf56d
Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-22 13:57:36 +02:00
Eddie Hung
fb09c6219b
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 14:21:00 -07:00
Clifford Wolf
c4b8575f43
Add "wreduce -keepdc", fixes #1016
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-20 15:36:13 +02:00
Clifford Wolf
a21a84b3b4
Improvements in opt_clean
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 16:01:28 +02:00
Clifford Wolf
f67ec1b235
Do not leak file descriptors in cover.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 13:51:02 +02:00
Henner Zeller
5e443a5d0d
Fix two instances of integer-assignment to string.
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o In cover.cc, the int-result of mkstemps() was assigned to a string
and silently interpreted as a single-character filename with a funny
value. Fix with the intent: assign the filename.
o in libparse.cc, an int was assigned to a string, but depending on
visible constructors, this is ambiguous. Explicitly cast this to
a char.
2019-05-14 22:01:15 -07:00
whitequark
c8c1df23a0
bugpoint: check for -script option.
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Fixes #925 .
2019-05-14 10:48:06 +00:00
Clifford Wolf
8166a142dd
Fix handling of glob_abort_cnt in opt_muxtree, fixes #1002
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-12 13:51:12 +02:00
Clifford Wolf
faf00586d8
Merge pull request #1003 from makaimann/zinit-all
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Zinit option '-singleton' -> '-all'
2019-05-11 13:56:51 +02:00
Clifford Wolf
b66b657b6b
Add "fmcombine -initeq -anyeq"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-11 09:28:55 +02:00
Clifford Wolf
04ef222cfb
Add "stat -tech xilinx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-11 09:24:52 +02:00
Makai Mann
2f5cfa014b
Zinit option '-singleton' -> '-all'
2019-05-10 10:23:14 -07:00
Jakob Wenzel
f06cb75b93
initialize more registers in setundef -init
2019-05-09 12:47:16 +02:00
Clifford Wolf
3870e7cf29
Merge pull request #991 from kristofferkoch/gcc9-warnings
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Fix all warnings that occurred when compiling with gcc9
2019-05-08 11:25:22 +02:00
Kristoffer Ellersgaard Koch
30c762d3a1
Fix all warnings that occurred when compiling with gcc9
2019-05-08 10:27:14 +02:00
Clifford Wolf
a76189e7ad
More opt_clean cleanups
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 14:41:58 +02:00
Clifford Wolf
752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify
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Add specify parser
2019-05-06 20:57:15 +02:00
Clifford Wolf
1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968
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Re-enable "final loop assignment" feature and fix opt_clean warnings
2019-05-06 20:53:38 +02:00
Clifford Wolf
7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import
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Improve verific -chparam and add hierarchy -chparam
2019-05-06 20:51:59 +02:00
Clifford Wolf
d187be39d6
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
2019-05-06 15:41:13 +02:00
Clifford Wolf
b37c31e2cb
Bugfix in peepopt_shiftmul.pmg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 15:34:19 +02:00
Clifford Wolf
c0782d8390
Merge pull request #989 from YosysHQ/dave/abc_name_improve
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ABC name recovery fixes
2019-05-06 13:57:35 +02:00
Clifford Wolf
f02e22a35a
Fix bug in "expose -input"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 13:30:55 +02:00
Clifford Wolf
ba6ce21a74
Cleanups in opt_clean
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 12:45:22 +02:00
Clifford Wolf
c7f2e93024
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
2019-05-06 11:46:10 +02:00
David Shah
a84256aa36
abc: Fix handling of postfixed names (e.g. for retiming)
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Signed-off-by: David Shah <dave@ds0.me>
2019-05-04 17:23:44 +01:00
David Shah
5ce9113eda
abc: Improve name recovery
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Signed-off-by: David Shah <dave@ds0.me>
2019-05-04 16:53:25 +01:00
Clifford Wolf
a01386c0e4
Improve opt_clean handling of unused wires
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 09:47:16 +02:00
Eddie Hung
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
Clifford Wolf
ec39cfd0ad
Add "hierarchy -chparam" support for non-verific top modules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 22:03:43 +02:00
Eddie Hung
eb21bf3651
log_warning_noprefix -> log_warning as per review
2019-05-03 20:53:25 +02:00
Eddie Hung
a27b42e975
WIP -chparam support for hierarchy when verific
2019-05-03 20:53:25 +02:00
Clifford Wolf
373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
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Improve pmgen, Add "peepopt" pass with shift-mul pattern
2019-05-03 20:39:50 +02:00
Clifford Wolf
f170fb6383
Merge pull request #984 from YosysHQ/eddie/fix_982
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dffinit to do nothing when (* init *) value is 1'bx
2019-05-03 20:34:32 +02:00
Eddie Hung
e08df0c739
If init is 1'bx, do not add to dict as per @cliffordwolf
2019-05-03 08:06:16 -07:00
Eddie Hung
fc349de033
Revert "dffinit -noreinit to silently continue when init value is 1'bx"
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This reverts commit aa081f83c7
.
2019-05-03 08:05:37 -07:00
Clifford Wolf
42190207b4
Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 14:25:01 +02:00
Clifford Wolf
5c2c0b4bb2
Further improve unused-detection for opt_clean driver-driver conflict warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 09:22:26 +02:00
Clifford Wolf
f12e1155f1
Improve unused-detection for opt_clean driver-driver conflict warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 09:12:10 +02:00
Clifford Wolf
2b29aa5c86
Update pmgen documentation
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 08:35:45 +02:00
Clifford Wolf
e8c5afcb84
Fix typo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 08:25:30 +02:00
Eddie Hung
aa081f83c7
dffinit -noreinit to silently continue when init value is 1'bx
2019-05-02 17:40:39 -07:00
Eddie Hung
8829cba901
Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux
2019-05-02 11:25:34 -07:00
Eddie Hung
5cd19b52da
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 10:44:59 -07:00
Eddie Hung
f86d153cef
Merge branch 'master' of github.com:YosysHQ/yosys
2019-05-01 16:26:43 -07:00
Clifford Wolf
521663f09e
Add missing enable_undef to "sat -tempinduct-def", fixes #883
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-02 00:03:31 +02:00
Clifford Wolf
93b7fd7744
Fix floating point exception in qwp, fixes #923
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 15:06:46 +02:00
Clifford Wolf
a30b99e66e
Silently resolve completely unused cell-vs-const driver-driver conflicts
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:29:34 +02:00
Clifford Wolf
32ff37bb5a
Fix segfault in wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 22:20:45 +02:00
Clifford Wolf
a27eeff573
Merge pull request #966 from YosysHQ/clifford/fix956
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Drive dangling wires with init attr with their init value
2019-04-30 18:08:41 +02:00
Clifford Wolf
9d117eba9d
Add handling of init attributes in "opt_expr -undriven"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 14:46:12 +02:00
Clifford Wolf
b515fd2d25
Add peepopt_muldiv, fixes #930
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 11:25:15 +02:00
Clifford Wolf
4306bebe58
pmgen progress
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 10:51:51 +02:00
Clifford Wolf
bb4f3642de
Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 08:04:22 +02:00
Clifford Wolf
58238da133
Progress in shiftmul peepopt pattern
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 07:59:39 +02:00
Clifford Wolf
ea547bcaa3
Add "peepopt" skeleton
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 13:38:56 +02:00
Clifford Wolf
9f792c599d
Add pmgen support for multiple patterns in one matcher
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 13:02:05 +02:00
Clifford Wolf
32881a989c
Support multiple pmg files (right now just concatenated together)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 12:09:02 +02:00
Clifford Wolf
754b1ee4b3
Drive dangling wires with init attr with their init value, fixes #956
2019-04-29 08:44:53 +02:00
Eddie Hung
acafcdc94d
Copy with 1'bx padding in $shiftx
2019-04-28 13:04:34 -07:00
Eddie Hung
dcc8a13e48
Revert "Merge branch 'eddie/split_shiftx' into xc7mux"
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This reverts commit 3042d58330
, reversing
changes made to feff976454
.
2019-04-26 15:32:02 -07:00
Eddie Hung
159e7cc298
Add -undef option to equiv_opt, passed to equiv_induct
2019-04-26 11:16:48 -07:00
Eddie Hung
4473fd1502
Add -undef option to equiv_opt, passed to equiv_induct
2019-04-26 11:14:33 -07:00
Eddie Hung
976d8030dc
Actually use pm.st.shiftxB
2019-04-25 19:59:33 -07:00
Eddie Hung
fb4348f840
Fix for when B_WIDTH has trailing zeroes
2019-04-25 19:38:19 -07:00
Eddie Hung
880652283c
Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7mux
2019-04-25 18:52:20 -07:00
Eddie Hung
ece2c49e92
In order to indicate a failed pattern, blacklist?
2019-04-25 18:39:13 -07:00
Eddie Hung
af3c374a35
Elaborate on help message
2019-04-25 17:35:39 -07:00
Eddie Hung
3042d58330
Merge branch 'eddie/split_shiftx' into xc7mux
2019-04-25 17:31:27 -07:00
Eddie Hung
ccd0729456
Add split_shiftx command
2019-04-25 17:23:59 -07:00
Eddie Hung
8d00b9ef7e
Make pmgen support files more generic
2019-04-25 17:23:46 -07:00
Eddie Hung
408161ea3a
Misspelling
2019-04-25 16:46:13 -07:00
Eddie Hung
d9c915042a
Move clean from aigerparse to abc9
2019-04-23 13:42:35 -07:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
634482380c
Preserve $specify[23] cells
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
c84cdc711c
Remove some left-over log_dump()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 17:55:41 +02:00
Eddie Hung
4df4a97ffa
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-04-22 18:20:39 -07:00
Eddie Hung
0bd2bfa737
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 18:15:28 -07:00
Eddie Hung
5f30a8795d
Tidy up
2019-04-22 17:47:05 -07:00
Eddie Hung
d9daf09cf3
Merge pull request #914 from YosysHQ/xc7srl
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synth_xilinx to now infer SRL16E/SRLC32E
2019-04-22 13:31:30 -07:00
Eddie Hung
4cfef7897f
Merge branch 'xaig' into xc7mux
2019-04-22 11:58:59 -07:00
Eddie Hung
4486a98fd5
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
2019-04-22 11:45:49 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Clifford Wolf
8ed4a53d99
Merge pull request #951 from YosysHQ/clifford/logdebug
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Add log_debug() framework
2019-04-22 20:09:51 +02:00
Clifford Wolf
1d538ff1ec
Merge pull request #949 from YosysHQ/clifford/pmux2shimprove
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Add full_pmux feature to pmux2shiftx
2019-04-22 20:01:43 +02:00
Eddie Hung
e300b1922c
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 10:36:27 -07:00
Clifford Wolf
e158ea2097
Add log_debug() framework
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 17:25:52 +02:00
whitequark
aeeefc32d8
attrmap: extend -remove to allow removing attributes with any value.
...
Currently, `-remove foo` would only remove an attribute `foo = ""`,
which doesn't work on an attribute like `src` that may have any
value. Extend `-remove` to handle both cases. `-remove foo=""` has
the old behavior, and `-remove foo` will remove the attribute with
whatever value it may have, which is still compatible with the old
behavior.
2019-04-22 14:18:15 +00:00
Clifford Wolf
0f0ada13f4
Add full_pmux feature to pmux2shiftx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 15:26:20 +02:00
Clifford Wolf
99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings
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Feature/python bindings
2019-04-22 14:47:52 +02:00
Clifford Wolf
a98b171814
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
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Add pmux2shiftx command
2019-04-22 08:39:37 +02:00
Eddie Hung
d06d4f35c3
Merge remote-tracking branch 'origin/clifford/libwb' into xaig
2019-04-21 18:10:46 -07:00
Clifford Wolf
7b35d57592
Disable blackbox detection in techmap files
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 02:07:36 +02:00
Eddie Hung
d99422411f
Use new pmux2shiftx from #944 , remove my old attempt
2019-04-21 14:16:34 -07:00
Eddie Hung
98781acf84
Merge remote-tracking branch 'origin/clifford/pmux2shiftx' into xc7srl
2019-04-20 17:24:33 -07:00
Eddie Hung
9dc11cd842
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 17:24:06 -07:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Clifford Wolf
f84a84e3f1
Merge pull request #943 from YosysHQ/clifford/whitebox
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[WIP] Add "whitebox" attribute, add "read_verilog -wb"
2019-04-20 20:51:54 +02:00
Eddie Hung
b25254020c
Merge remote-tracking branch 'origin/pmux2shiftx' into xc7srl
2019-04-20 10:44:01 -07:00
Eddie Hung
13ad19482f
Merge remote-tracking branch 'origin' into xc7srl
2019-04-20 10:41:43 -07:00
Clifford Wolf
fc23af1707
Auto-initialize OnehotDatabase on-demand in pmux2shiftx.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 18:13:37 +02:00
Clifford Wolf
97e9caa4fa
Add "onehot" pass, improve "pmux2shiftx" onehot handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 17:52:16 +02:00
Clifford Wolf
f3ad8d680a
Add "techmap -wb", use in formal flows
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:23:24 +02:00
Clifford Wolf
b7445ef387
Check blackbox attribute in techmap/simplemap
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:10:05 +02:00
Clifford Wolf
5b915f0153
Add "wbflip" command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:04:46 +02:00
Clifford Wolf
e3687f6f4e
Merge pull request #942 from YosysHQ/clifford/fix931
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Improve proc full_case detection and handling
2019-04-20 10:05:35 +02:00
Clifford Wolf
b3a3e08e38
Improve "pmux2shiftx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 02:03:44 +02:00
Clifford Wolf
e06d158e8a
Fix some typos
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 01:18:07 +02:00
Clifford Wolf
37728520a6
Improvements in "pmux2shiftx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 01:15:48 +02:00
Clifford Wolf
0070184ea9
Improvements in pmux2shiftx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf
177878cbb0
Improve pmux2shift ctrl permutation finder
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf
481f0015be
Complete rewrite of pmux2shiftx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf
1bf8c2b823
Import initial pmux2shiftx from eddieh
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf
eafc4bd49f
Improve "show" handling of 0/1/X/Z padding
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:37:43 +02:00
Eddie Hung
9dec3d9978
Spelling fixes
2019-04-19 14:00:22 +02:00
Eddie Hung
290a798cec
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:32:00 -07:00
Eddie Hung
c997a77014
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:19:45 -07:00
Eddie Hung
070a2d2fd6
Fix abc's remap_name to not ignore [^0-9] when extracting sid
2019-04-18 09:55:03 -07:00
Eddie Hung
8fe0a961b3
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
2019-04-18 09:00:06 -07:00
Eddie Hung
9aa94370a5
ABC to call retime all the time
2019-04-18 08:46:41 -07:00
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
Eddie Hung
0642baabbc
Merge branch 'master' into eddie/fix_retime
2019-04-18 07:57:17 -07:00
Clifford Wolf
88be1cbfa5
Improve proc full_case detection and handling, fixes #931
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 15:13:47 +02:00
Eddie Hung
a20ed260e1
Skip if abc_box_id earlier
2019-04-17 16:36:03 -07:00
Eddie Hung
709f76c107
Remove use of abc_box_id in stat
2019-04-17 16:35:27 -07:00
Eddie Hung
abcd3103ff
Do not print slack histogram
2019-04-17 15:11:14 -07:00
Eddie Hung
fd89c1056e
Working ABC9 script
2019-04-17 12:33:32 -07:00
Eddie Hung
ae2653c50f
abc9 to output some more info
2019-04-16 16:39:16 -07:00
Eddie Hung
b015ed48f7
Merge remote-tracking branch 'origin/master' into xaig
2019-04-16 15:04:20 -07:00
Eddie Hung
55a3638c71
Port from xc7mux branch
2019-04-16 15:01:45 -07:00
Eddie Hung
fc5fda595d
Merge branch 'xaig' into xc7mux
2019-04-16 13:15:53 -07:00
Eddie Hung
afcb86c3d1
abc9 to call "setundef -zero" behaving as for abc
2019-04-16 13:10:13 -07:00
Eddie Hung
98c297fabf
ABC to read_box before reading netlist
2019-04-16 12:44:10 -07:00
Eddie Hung
b89bb74452
For 'stat' do not count modules with abc_box_id
2019-04-16 11:19:54 -07:00
Eddie Hung
a2b106135b
Do not call abc on modules with abc_box_id attr
2019-04-16 11:19:42 -07:00
Eddie Hung
4da4a6da2f
Revert #895
2019-04-16 11:07:51 -07:00
Eddie Hung
538592067e
Merge branch 'xaig' into xc7mux
2019-04-15 22:04:20 -07:00
Eddie Hung
0391499e46
Merge remote-tracking branch 'origin/master' into xaig
2019-04-15 21:56:45 -07:00
Eddie Hung
b3378745fd
Revert "Recognise default entry in case even if all cases covered (fix for #931 )"
2019-04-15 17:52:45 -07:00
Eddie Hung
9bfcd80063
Handle __dummy_o__ and __const[01]__ in read_aiger not abc
2019-04-12 18:21:16 -07:00
Eddie Hung
482a60825b
abc to ignore __dummy_o__ and __const[01]__ when re-integrating
2019-04-12 18:16:50 -07:00
Eddie Hung
88d43a519b
Use -map instead of -symbols for aiger
2019-04-12 16:29:14 -07:00
Eddie Hung
941365b4bb
Comment out
2019-04-12 12:29:04 -07:00
Eddie Hung
04e466d5e4
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-12 12:28:37 -07:00
Eddie Hung
f77da46a87
Merge remote-tracking branch 'origin/master' into xaig
2019-04-12 12:21:48 -07:00
Eddie Hung
3c1f1a6605
Fix ordering of when to insert zero index
2019-04-11 16:25:59 -07:00
Eddie Hung
53513c52df
Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux
2019-04-11 16:21:01 -07:00
Eddie Hung
f587950bde
More unused
2019-04-11 16:20:43 -07:00
Eddie Hung
35181a7866
Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux
2019-04-11 16:18:45 -07:00
Eddie Hung
b15b410b41
Remove unused
2019-04-11 16:18:01 -07:00
Eddie Hung
b1f1db2fcf
Fixes
2019-04-11 16:17:09 -07:00
Eddie Hung
e8c26f2839
WIP
2019-04-11 15:52:04 -07:00
Eddie Hung
09e7eb7aed
Spelling fixes
2019-04-11 15:09:13 -07:00
Eddie Hung
adc6efb584
Recognise default entry in case even if all cases covered ( #931 )
2019-04-11 12:34:51 -07:00
Eddie Hung
5f4024ffd2
Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen"
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This reverts commit 19271bd996
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2019-04-10 08:31:40 -07:00
Eddie Hung
78d35a86c0
Revert ""&nf -D 0" fails => use "-D 1" instead"
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This reverts commit 3c253818ca
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2019-04-10 08:31:35 -07:00
Eddie Hung
c89cd48f58
Merge remote-tracking branch 'origin/master' into eddie/fix_retime
2019-04-10 08:23:00 -07:00
Eddie Hung
d536379c62
Add "-lut <file>" support to abc9
2019-04-09 14:31:31 -07:00
Eddie Hung
7e304c362b
Add "-box" option to abc9
2019-04-09 10:58:06 -07:00
Eddie Hung
bd523abef5
Add 'setundef -zero' call prior to aigmap in abc9
2019-04-09 10:32:58 -07:00
Eddie Hung
3b6f85b0a6
Comment out
2019-04-09 10:09:43 -07:00
Eddie Hung
3fc474aa73
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-09 10:06:44 -07:00
Eddie Hung
0deaccbaae
Fix a few typos
2019-04-08 16:46:33 -07:00
Eddie Hung
12c34136ba
More space fixing
2019-04-08 16:40:17 -07:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Eddie Hung
6797f6b6c4
$_XILINX_SHREG_ to preserve src attribute
2019-04-08 16:24:20 -07:00
Eddie Hung
7e773741ab
Merge branch 'undo_pr895' into xc7srl
2019-04-08 16:07:52 -07:00
Eddie Hung
13fc70d7a4
Undo #895 by instead setting an attribute
2019-04-08 16:05:24 -07:00
Eddie Hung
93b1621911
Cope with undoing #895
2019-04-08 15:57:07 -07:00
Eddie Hung
d3930ca79e
Revert "Remove handling for $pmux, since #895"
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This reverts commit aa693d5723
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2019-04-08 12:01:06 -07:00
David Shah
2bf3ca6443
memory_bram: Fix multiport make_transp
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Signed-off-by: David Shah <dave@ds0.me>
2019-04-07 16:56:31 +01:00
Eddie Hung
1d526b7f06
Call shregmap twice -- once for variable, another for fixed
2019-04-05 17:35:49 -07:00
Eddie Hung
4afcad70e2
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 16:30:17 -07:00
Eddie Hung
d559023007
Fix S0 -> S1
2019-04-05 16:28:14 -07:00
Eddie Hung
0364a5d811
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 15:46:18 -07:00
Eddie Hung
3c253818ca
"&nf -D 0" fails => use "-D 1" instead
2019-04-05 15:30:19 -07:00
Eddie Hung
19271bd996
abc -dff now implies "-D 0" otherwise retiming doesn't happen
2019-04-05 14:42:25 -07:00
Clifford Wolf
75ca06526a
Added missing argument checking to "mutate" command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-04 18:10:10 +02:00
Eddie Hung
572603409c
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 07:54:42 -07:00
Benedikt Tutzer
cae657cebd
Used PyImport_ImportModule instead of PyImport_Import to avoid the explicit conversion to a python string
2019-04-04 10:35:01 +02:00
Benedikt Tutzer
e64b3f1074
Changed filesystem dependency to boost instead of experimental std library
2019-04-04 09:24:50 +02:00
Eddie Hung
aa693d5723
Remove handling for $pmux, since #895
2019-04-03 08:35:32 -07:00
Sylvain Munaut
39380c45ba
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
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last_mux_cell can be NULL ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-04-03 14:50:12 +02:00
Benedikt Tutzer
fd7fb1377d
Added cross-platform support for plugin-paths
2019-04-03 13:21:40 +02:00
Eddie Hung
d8465590ac
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-03 03:36:11 -07:00
Benedikt Tutzer
bbfb43006d
Improved Error reporting when Python passes are loaded
2019-04-03 12:21:56 +02:00
David Shah
6acbc016f4
memory_bram: Consider read enable for address expansion register
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Signed-off-by: David Shah <dave@ds0.me>
2019-04-02 19:47:50 +01:00
Eddie Hung
aaa2690a56
Merge pull request #895 from YosysHQ/pmux2shiftx
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RFC: Add a pmux-to-shiftx optimisation to proc_mux
2019-04-02 00:16:14 -07:00
Benedikt Tutzer
03d1606b42
Merge remote-tracking branch 'origin/master' into feature/python_bindings
2019-03-28 12:16:39 +01:00
Clifford Wolf
32bd0f22ec
Merge pull request #901 from trcwm/libertyfixes
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Libertyfixes: accept superfluous ; at end of group.
2019-03-28 09:32:05 +01:00
Clifford Wolf
662429cc49
Merge pull request #903 from YosysHQ/bram_reset_transp
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memory_bram: Reset make_transp when growing read ports
2019-03-28 09:30:48 +01:00
David Shah
60594ad40c
memory_bram: Reset make_transp when growing read ports
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-27 17:19:14 +00:00
Niels Moseley
263ab60b43
Liberty file parser now accepts superfluous ;
2019-03-27 15:17:58 +01:00
Niels Moseley
487cb45b87
Liberty file parser now accepts superfluous ;
2019-03-27 15:15:53 +01:00
Clifford Wolf
2c7fe42ad1
Add "rename -output"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-27 13:47:42 +01:00
Clifford Wolf
d351b7cb99
Improve "rename" help message
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-27 13:33:26 +01:00
Clifford Wolf
38b3fbd3f0
Add "cutpoint -undef"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 16:01:14 +01:00
Clifford Wolf
d0b9b1bece
Add "hdlname" attribute
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 14:52:48 +01:00
Eddie Hung
6b90d3cf6c
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-25 13:17:22 -07:00
Clifford Wolf
ddc1a4488e
Add "cutpoint" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-25 19:49:00 +01:00
Eddie Hung
b7a3d35c6b
Create one $shiftx per bit in width
2019-03-25 11:16:56 -07:00
Clifford Wolf
9ec50ca7b9
Merge pull request #896 from YosysHQ/transp_fixes
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memory_bram: Fix multiclock make_transp
2019-03-25 14:55:16 +01:00
Niels Moseley
1f7f54e68e
spaces -> tabs
2019-03-25 14:12:04 +01:00
Niels Moseley
9d9cc8a314
EOL is now accepted as ';' replacement on lines that look like: feature_xyz(option)
2019-03-25 12:15:10 +01:00
Niels Moseley
3b3b77291a
Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.
2019-03-24 22:54:18 +01:00
David Shah
ac6cc88db3
memory_bram: Fix multiclock make_transp
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-24 16:21:36 +00:00
Eddie Hung
2507d01b03
Add a pmux-to-shiftx optimisation to proc_mux
2019-03-23 16:45:36 -07:00
Eddie Hung
bf83c074c8
Cope with SHREG not having E port; Revert $pmux fine tune
2019-03-23 16:09:38 -07:00
Clifford Wolf
ccfa2fe01c
Add "mutate -none -mode", "mutate -mode none"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 20:20:32 +01:00
Clifford Wolf
59c44bb61a
Add "mutate -s <filename>"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 17:53:09 +01:00
Eddie Hung
098bd5758f
Add support for SHREGMAP+$mux, also fine tune $pmux
2019-03-22 23:22:19 -07:00
Eddie Hung
0895093c7c
Leftover printf
2019-03-22 19:14:04 -07:00
Eddie Hung
456295eb66
Fixes for multibit
2019-03-22 18:32:42 -07:00
Eddie Hung
03d108cd1f
Working for 1 bit
2019-03-22 17:46:49 -07:00
Eddie Hung
46753cf89f
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 13:10:42 -07:00
Clifford Wolf
7cfd83c341
Trim init attributes when resizing FFs in "wreduce", fixes #887
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-22 11:42:19 +01:00
Eddie Hung
5597270b9e
Opt
2019-03-21 10:20:27 -07:00
Eddie Hung
2b911e270b
Fix spacing
2019-03-20 12:28:39 -07:00
Eddie Hung
505e4c2d59
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
2019-03-19 21:58:05 -07:00
Eddie Hung
5445cd4d00
Add support for variable length Xilinx SRL > 128
2019-03-19 17:44:33 -07:00
Eddie Hung
4cd8f02973
shregmap -tech xilinx to delete $shiftx for var length SRL
2019-03-19 15:05:08 -07:00
Eddie Hung
24553326dd
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 13:11:30 -07:00
Eddie Hung
0ea7eba5f1
Make output port a non chain user
2019-03-19 13:08:43 -07:00
Eddie Hung
ed32119d13
Fix shregmap to correctly recognise non chain users; cleanup
2019-03-18 16:12:19 -07:00
Eddie Hung
b94db54664
shiftx NULL pointer check
2019-03-18 13:35:54 -07:00
Eddie Hung
d6d9ef0fee
Cleanup
2019-03-16 12:49:46 -07:00
Eddie Hung
fadeadb8c8
Only accept <128 for variable length, only if $shiftx exclusive
2019-03-16 08:51:13 -07:00
Eddie Hung
06f8f2654a
Working
2019-03-15 19:13:40 -07:00
Clifford Wolf
aa65d3fe65
Improve mix of src/wire/wirebit coverage in "mutate -list"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-16 00:55:46 +01:00
Clifford Wolf
dacaebae35
Add "fmcombine -fwd -bwd -nop"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-15 21:45:37 +01:00
Clifford Wolf
370db33a4c
Add fmcombine pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-15 20:46:17 +01:00
Clifford Wolf
d1985f6a22
Improvements in "mutate" list-reduce algorithm
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-15 00:18:31 +01:00
Clifford Wolf
27a5d9c91e
Add "mutate -cfg", improve pick_cover behavior
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 23:20:41 +01:00
Clifford Wolf
4d304e3da7
Add a strictly coverage-driven mutation selection strategy
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 23:01:55 +01:00
Clifford Wolf
2a4263a75d
Improve "mutate" wire coverage metric
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 23:01:01 +01:00
Clifford Wolf
1b4fdbb0d8
Add more mutation types, improve mutation src cover
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
6ad5d036c5
Add "mutate" command DB reduce functionality
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
8e6b69d7bb
Add "mutate -mode inv", various other mutate improvements
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
ea8ee24140
Add basic "mutate -list N" framework
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
f806b95ed6
Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 20:52:00 +01:00
Eddie Hung
8af9979aab
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
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This reverts commit 26ecbc1aee
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2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee
Add shregmap -init_msb_first and use in synth_xilinx
2019-03-14 08:10:02 -07:00
Clifford Wolf
399ab16315
Add $dffsr support to async2sync
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-09 11:52:00 -08:00
Eddie Hung
d03780c3f4
Fix spelling in pmgen/README.md
2019-03-05 17:55:29 -08:00
Clifford Wolf
ae9286386d
Only run derive on blackbox modules when ports have dynamic size
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 12:36:46 -08:00
Larry Doolittle
57f8bb471f
Try again for passes/pmgen/ice40_dsp_pm.h rule
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Tested on both in-tree and out-of-tree builds
2019-03-01 20:20:53 -08:00
Clifford Wolf
e847690bda
Fix multiple issues in wreduce FF handling, fixes #835
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 17:24:46 -08:00
Larry Doolittle
e2fc18f27b
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
Clifford Wolf
68a6937173
Fix pmgen for in-tree builds
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 14:56:05 -08:00
Clifford Wolf
64d91219b4
Fix pmgen for out-of-tree build
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 14:00:58 -08:00
Clifford Wolf
63be3f3bab
Improvements in "supercover" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-27 11:45:13 -08:00
Clifford Wolf
a58dbcf2ba
Add "supercover" skeleton
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-27 11:37:08 -08:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Eddie Hung
7cac3b1c8b
abc9 -- multiple connections for inouts
2019-02-26 12:18:28 -08:00
Larry Doolittle
61fc411c5d
Clean up some whitepsace outliers
2019-02-26 09:39:46 -08:00
Eddie Hung
967297cd57
abc9 cleanup
2019-02-25 18:40:53 -08:00
Eddie Hung
721f6a14fb
read_aiger to accept empty string for clk_name, passable only if no latches
2019-02-25 15:34:02 -08:00
Eddie Hung
0ca3fd6a1c
abc9 not to clean after aigmap
2019-02-25 15:31:52 -08:00
Eddie Hung
51f28a6747
abc9 to call "clean" once at the end of all abc9_module() calls
2019-02-25 12:55:47 -08:00
Clifford Wolf
c258b99040
Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:41:36 +01:00
Clifford Wolf
c118f9a377
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
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Define basic_cell_type() function and use it to derive the cell type …
2019-02-24 11:39:13 -08:00
Clifford Wolf
cd722f26a5
Cleanups in ARST handling in wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:34:23 +01:00
Clifford Wolf
da14bc8524
Merge pull request #824 from litghost/fix_reduce_on_ff
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Fix WREDUCE on FF not fixing ARST_VALUE parameter.
2019-02-24 11:29:14 -08:00
Jim Lawson
71bcc4c644
Address requested changes - don't require non-$ name.
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Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
2019-02-22 16:06:10 -08:00
Keith Rothman
25680f6a07
Fix WREDUCE on FF not fixing ARST_VALUE parameter.
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Adds test case that fails without code change.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-22 10:30:42 -08:00
Eddie Hung
d56f02d1fc
abc9 to use AIGER symbol table, as opposed to map file
2019-02-21 17:03:40 -08:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress
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Improve ABC netname preservation
2019-02-22 01:16:34 +01:00
Eddie Hung
2811d66dea
Revert "abc9 to write_xaiger -symbols, not -map"
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This reverts commit 04429f8152
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2019-02-21 14:58:40 -08:00
Eddie Hung
7ad9628f07
Remove irrelevant citations
2019-02-21 14:41:11 -08:00
Eddie Hung
085ed9f487
Add attribution
2019-02-21 14:40:13 -08:00
Eddie Hung
875a02a6f2
abc9 to not select anything extra, and pop selection after final clean
2019-02-21 14:38:52 -08:00
Eddie Hung
04429f8152
abc9 to write_xaiger -symbols, not -map
2019-02-21 14:28:36 -08:00
Eddie Hung
3307295488
Merge branch 'read_aiger' into xaig
2019-02-21 14:27:32 -08:00
Eddie Hung
7f8f36273a
abc9 to use &mfs
2019-02-21 13:16:24 -08:00
Eddie Hung
a8803a1519
Merge remote-tracking branch 'origin/master' into xaig
2019-02-21 11:23:00 -08:00
Eddie Hung
6b96df41bc
abc9 to only disconnect output ports of AND and NOT gates
2019-02-21 11:15:47 -08:00
Clifford Wolf
d55790909c
Hotfix for 4c82ddf
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 19:27:23 +01:00
Keith Rothman
4c82ddf394
Add -params mode to force undef parameters in selected cells.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-21 10:16:38 -08:00
Clifford Wolf
0e371109b0
Merge pull request #818 from YosysHQ/clifford/dffsrfix
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Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
2019-02-21 18:58:44 +01:00
Clifford Wolf
893194689d
Fix typo in passes/pmgen/README.md
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:50:02 +01:00
Eddie Hung
be061810d7
Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig
2019-02-21 09:31:17 -08:00
Clifford Wolf
2da4c9c8f0
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:49:45 +01:00
Clifford Wolf
2fe1c830eb
Bugfix in ice40_dsp
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:28:46 +01:00
Eddie Hung
7f26043caf
ABC -> ABC9
2019-02-20 17:36:57 -08:00
Eddie Hung
e5b8bb9faa
abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_
2019-02-20 17:33:35 -08:00
Eddie Hung
32853b1f8d
lut/not/and suffix to be ${lut,not,and}
2019-02-20 16:30:30 -08:00
Eddie Hung
2ca83005fb
abc9 to cope with multiple modules
2019-02-20 12:56:15 -08:00
Eddie Hung
d6b317b349
abc9 to use & syntax for -fast, and name fixes
2019-02-20 12:40:17 -08:00
Clifford Wolf
218e9051bb
Add "synth_ice40 -dsp"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:42:27 +01:00
Clifford Wolf
246391200e
Add FF support to wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:36:42 +01:00
Clifford Wolf
dca65d83a0
Detect and reject cases that do not map well to iCE40 DSPs (yet)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 11:18:19 +01:00
Eddie Hung
62e5ff9ba8
abc9 to cope with indexed wires when creating $lut from $_NOT_
2019-02-19 16:06:03 -08:00
Jim Lawson
5c4a72c43e
Fix normal (non-array) hierarchy -auto-top.
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Add simple test.
2019-02-19 14:35:15 -08:00
Eddie Hung
8158bc3f99
abc9 to replace $_NOT_ with $lut
2019-02-19 12:30:20 -08:00
Clifford Wolf
5a853ed46c
Add actual DSP inference to ice40_dsp pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-17 15:35:48 +01:00
Clifford Wolf
c06c062469
Merge branch 'master' of github.com:YosysHQ/yosys into pmgen
2019-02-17 12:10:19 +01:00
Eddie Hung
45d49d5d14
Get rid of debugging stuff in abc9
2019-02-16 22:25:22 -08:00
Eddie Hung
f853b2f3c1
abc9 to write_aiger with -O option, and ignore dummy outputs
2019-02-16 20:09:40 -08:00
Eddie Hung
d8c4d4e6c7
abc9 to handle comb loops, cope with constant outputs, disconnect using new wire
2019-02-16 13:47:38 -08:00
Eddie Hung
e7c7ab8fc0
expose command to not skip 'internal' wires beginning with '$'
2019-02-16 13:45:17 -08:00
Eddie Hung
d4545d415b
abc9 to cope with non-wideports, count cells properly
2019-02-16 08:53:06 -08:00
Eddie Hung
f8d0134598
Move lookup inside if
2019-02-15 15:23:26 -08:00
Eddie Hung
a786ac4d53
Refactor
2019-02-15 13:00:13 -08:00
Eddie Hung
914546efd9
Cope with width != 1 when re-mapping cells
2019-02-15 12:55:52 -08:00
Eddie Hung
956ee545c5
abc9 to stitch results with CI/CO properly
2019-02-15 11:52:34 -08:00
Jim Lawson
5c504c5ae6
Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code).
2019-02-15 11:31:37 -08:00
Eddie Hung
206f11dca3
Fix stitching
2019-02-13 17:04:23 -08:00
Eddie Hung
f0f5d8a5cc
Merge remote-tracking branch 'origin/read_aiger' into xaig
2019-02-13 14:09:36 -08:00
Eddie Hung
06cf0555ee
Merge https://github.com/YosysHQ/yosys into xaig
2019-02-13 14:08:31 -08:00
Eddie Hung
87f059adf7
Rip out some more stuff
2019-02-13 10:44:52 -08:00
Eddie Hung
045f7763ae
Rip out unused functions in abc9
2019-02-12 16:25:22 -08:00
Eddie Hung
b3341b4abb
WIP for ABC with aiger
2019-02-12 09:31:22 -08:00
Eddie Hung
c23e3f0751
Missing headers for Xcode?
2019-02-12 09:24:13 -08:00
Eddie Hung
5a0a5aae4f
Compile abc9
2019-02-08 13:58:47 -08:00
Eddie Hung
e25a22015f
Copy abc.cc to abc9.cc
2019-02-08 13:23:54 -08:00
David Shah
a4515712cb
fsm_opt: Fix runtime error for FSMs without a reset state
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-07 10:35:36 +00:00
David Shah
58c22dae31
abc: Improved recovered netnames, also preserve src on nets with dress
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
David Shah
8524a479b1
abc: Preserve naming through ABC using 'dress' command
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-06 22:23:13 +01:00
whitequark
58d059ccb7
proc_clean: fix critical typo.
2019-01-23 22:08:38 +00:00
whitequark
95b6c35882
proc_clean: fix fully def check to consider compare/signal length.
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Fixes #790 .
2019-01-18 23:22:19 +00:00
Clifford Wolf
8ddec5d882
Progress in pmgen
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
5216735210
Progress in pmgen, add pmgen README
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
55ac030382
Fix pmgen "reject" statement
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
d45379936b
Progress in pmgen
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
1f8e76f993
Progress in pmgen
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
b9545aa0e1
Progress in pmgen
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
Clifford Wolf
ad69c668ce
Add mockup .pmg (pattern matcher generator) file
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:23:25 +01:00
whitequark
e792bd56b7
flowmap: clean up terminology.
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* "map": group gates into LUTs;
* "pack": replace gates with LUTs.
This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.
Also clean up some other log messages while we're at it.
2019-01-08 02:05:06 +00:00
whitequark
211c26a4c9
flowmap: implement depth relaxation.
2019-01-08 01:13:05 +00:00
Clifford Wolf
8a63fc51d3
Bugfix in $memrd sharing
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-07 10:04:47 +01:00
Clifford Wolf
dbd51d7bda
Merge pull request #782 from whitequark/flowmap_dfs
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flowmap: construct a max-volume max-flow min-cut, not just any one
2019-01-07 09:47:57 +01:00
Clifford Wolf
b5f6e786ea
Switch "bugpoint" from system() to run_command()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-07 09:45:21 +01:00
whitequark
a342d6db49
bugpoint: new pass.
...
A typical use of `bugpoint` would involve a script with a pass under
test, e.g.:
flowmap -relax -optarea 100
and would be invoked as:
bugpoint -yosys ./yosys -script flowmap.ys -clean -cells
This replaces the current design with the minimal design that still
crashes the `flowmap.ys` script.
`bugpoint` can also be used to perform generic design minimization
using `select`, e.g. the following script:
select i:* %x t:$_MUX_ %i -assert-max 0
would remove all parts of the design except for an unbroken path from
an input to an output port that goes through exactly one $_MUX_ cell.
(The condition is inverted.)
2019-01-07 03:13:19 +00:00
whitequark
8b44198e23
flowmap: construct a max-volume max-flow min-cut, not just any one.
2019-01-06 19:51:37 +00:00
Scott Mansell
62c90c4e17
Rename cells based on the wires they drive.
2019-01-06 19:00:16 +13:00
whitequark
2fcc1ee72e
flowmap: add -minlut option, to allow postprocessing with opt_lut.
2019-01-04 21:18:03 +00:00
whitequark
9bc5cf0844
flowmap: cleanup for clarity. NFCI.
2019-01-04 13:04:20 +00:00
whitequark
fd21564deb
flowmap: improve debug graph output. NFC.
2019-01-04 03:30:04 +00:00
whitequark
7850a0c28a
flowmap: add link to longer version of paper. NFC.
2019-01-04 02:33:10 +00:00
Clifford Wolf
d98fe8ce1f
Merge pull request #775 from whitequark/opt_flowmap
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flowmap: new techmap pass
2019-01-03 17:03:18 +01:00
whitequark
07af772a72
flowmap: new techmap pass.
2019-01-03 14:28:19 +00:00
Clifford Wolf
0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp
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opt_expr: refactor and improve simplification of comparisons
2019-01-02 17:34:04 +01:00
whitequark
bf8db55ef3
opt_expr: improve simplification of comparisons with large constants.
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The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.
However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.
This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
2019-01-02 15:45:28 +00:00
Clifford Wolf
979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init
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Initialization of Anlogic DFFs
2019-01-02 15:52:22 +01:00
Clifford Wolf
2e606b1802
Merge pull request #773 from whitequark/opt_lut_elim_fixes
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opt_lut: elimination fixes
2019-01-02 15:45:29 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
c55dfb8369
opt_lut: reflect changes in sigmap.
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Otherwise, some LUTs will be missed during elimination.
2019-01-02 10:21:58 +00:00
whitequark
06143ab33f
opt_lut: use a worklist, and revisit cells affected by elimination.
2019-01-02 09:36:32 +00:00
whitequark
f7363ac508
opt_lut: count eliminated cells, and set opt.did_something for them.
2019-01-02 09:14:43 +00:00
whitequark
4fd458290c
opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.
2019-01-02 05:11:29 +00:00
whitequark
9e9846a6ea
opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.
2019-01-02 03:01:25 +00:00
whitequark
8e53d2e0bf
opt_expr: simplify any unsigned comparisons with all-0 and all-1.
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Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
2019-01-02 02:45:49 +00:00
whitequark
42c356c49c
opt_lut: eliminate LUTs evaluating to constants or inputs.
2018-12-31 23:55:40 +00:00
Clifford Wolf
0a840dd883
Fix handling of (* keep *) wires in wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-31 16:37:40 +01:00
whitequark
18291c20d2
proc_clean: remove any empty cases if all cases use all-def compare.
2018-12-23 09:04:30 +00:00
whitequark
b784440857
proc_clean: remove any empty cases at the end of the switch.
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Previously, only completely empty switches were removed.
2018-12-22 09:04:46 +00:00
whitequark
0c318e7db5
memory_collect: do not truncate 'x from \INIT.
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The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
2018-12-21 02:01:27 +00:00
David Shah
2b16d4ed3d
memory_dff: Fix typo when checking init value
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-12-18 17:40:01 +00:00
Icenowy Zheng
256fb8c95c
Add "dffinit -noreinit" parameter
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Sometimes the FF cell might be initialized during the map process, e.g.
some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has
only a "SR" pin for a FF for async reset, that resets the FF to the
initial value, which means the async reset value should be set as the
initial value. In this case the DFFINIT pass shouldn't reinitialize it
to a different value, which will lead to error.
Add a "-noreinit" parameter for the safeguard. If a FF is not
technically initialized before DFFINIT pass, the default value should be
set to x.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 23:10:40 +08:00
Icenowy Zheng
fec8b3c81f
Add "dffinit -strinit high low"
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On some platforms the string to initialize DFF might not be "high" and
"low", e.g. with Anlogic TD it's "SET" and "RESET".
Add a "-strinit" parameter for dffinit to allow specify the strings used
for high and low.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 15:37:43 +08:00
Clifford Wolf
2641a3089b
Revert "Proof-of-concept: preserve naming through ABC using dress"
2018-12-16 21:27:31 +01:00
Clifford Wolf
ddff75b60a
Merge pull request #736 from whitequark/select_assert_list
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select: print selection if a -assert-* flag causes an error
2018-12-16 16:45:49 +01:00
whitequark
f6412d7109
select: print selection if a -assert-* flag causes an error.
2018-12-16 15:44:29 +00:00
Clifford Wolf
0d9c850a07
Merge pull request #735 from daveshah1/trifixes
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deminout fixes
2018-12-16 16:02:21 +01:00
Clifford Wolf
f53e19cc71
Fix equiv_opt indenting
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-16 15:57:28 +01:00
Clifford Wolf
2a681909df
Merge pull request #724 from whitequark/equiv_opt
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equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
Clifford Wolf
a2154c1be0
Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata
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memory_bram: Fix initdata bit order after shuffling
2018-12-16 15:53:44 +01:00
Clifford Wolf
a1fb5b1e4b
Merge pull request #714 from daveshah1/abc_preserve_naming
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Proof-of-concept: preserve naming through ABC using dress
2018-12-16 15:41:30 +01:00
Clifford Wolf
19ca4e2ac3
Merge pull request #722 from whitequark/rename_src
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rename: add -src, for inferring names from source locations
2018-12-16 15:28:29 +01:00
Clifford Wolf
556341a77f
Merge pull request #720 from whitequark/master
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lut2mux: handle 1-bit INIT constant in $lut cells
2018-12-16 15:27:23 +01:00
David Shah
4c59447168
deminout: Consider $tribuf cells
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 17:17:40 +00:00
David Shah
d3fe9465f3
deminout: Don't demote constant-driven inouts to inputs
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 16:50:46 +00:00
Graham Edgecombe
4fef9689ab
memory_bram: Fix initdata bit order after shuffling
...
In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.
This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).
This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
2018-12-11 21:02:49 +00:00
whitequark
7ff5a9db2d
equiv_opt: pass -D EQUIV when techmapping.
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This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
whitequark
c38ea9ae65
equiv_opt: new command, for verifying optimization passes.
2018-12-07 17:20:34 +00:00
whitequark
7ec740b7ad
opt_lut: leave intact LUTs with cascade feeding module outputs.
2018-12-07 17:13:52 +00:00
whitequark
9eb03d458d
opt_lut: show original truth table for both cells.
2018-12-07 17:04:41 +00:00
whitequark
a8ab722824
opt_lut: add -limit option, for debugging misoptimizations.
2018-12-07 16:36:26 +00:00
David Shah
1dfb2fecab
abc: Preserve naming through ABC using 'dress' command
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 15:05:07 +00:00
Clifford Wolf
643f858acf
Bugfix in opt_expr handling of a<0 and a>=0
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:29:21 +01:00
whitequark
a9baee4b24
rename: add -src, for inferring names from source locations.
2018-12-05 20:35:13 +00:00
whitequark
d1f2cb01dc
lut2mux: handle 1-bit INIT constant in $lut cells.
...
This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
2018-12-05 19:27:48 +00:00
whitequark
88217d0157
opt_lut: simplify type conversion. NFC.
2018-12-05 19:12:02 +00:00
Clifford Wolf
2d98db73e3
Rename opt_lut.cpp to opt_lut.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-05 18:03:58 +01:00
whitequark
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
whitequark
e603484070
opt_lut: always prefer to eliminate 1-LUTs.
...
These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
2018-12-05 16:30:37 +00:00
whitequark
59eea0183f
opt_lut: collect and display statistics.
2018-12-05 16:30:37 +00:00
whitequark
e54c7e951c
opt_lut: refactor to use a worker. NFC.
2018-12-05 16:30:37 +00:00
whitequark
9e072ec21f
opt_lut: new pass, to combine LUTs for tighter packing.
2018-12-05 16:30:37 +00:00
Clifford Wolf
c800e3bb16
Fix typo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-04 23:30:23 +01:00
Clifford Wolf
70c417174d
Merge pull request #702 from smunaut/min_ce_use
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Add option to only use DFFE is the resulting E signal would be use > N times
2018-12-04 14:29:21 -08:00
Clifford Wolf
47c89d600c
Merge pull request #676 from rafaeltp/master
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Splits SigSpec into bits before calling check_signal_in_fanout (solves #675 )
2018-12-01 04:11:19 +01:00
Sylvain Munaut
8d3ab626ea
dff2dffe: Add option for unmap to only remove DFFE with low CE signal use
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-27 21:50:42 +01:00
Clifford Wolf
ab97eddee9
Add iteration limit to "opt_muxtree"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-20 17:56:47 +01:00
Niels Moseley
cfc9b9147c
DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info.
2018-11-06 12:11:52 +01:00
Clifford Wolf
719e29404a
Allow square brackets in liberty identifiers
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-05 12:33:33 +01:00
Niels Moseley
04cd179696
Liberty file newline handling is more relaxed. More descriptive error message
2018-11-03 18:38:49 +01:00
Niels Moseley
d1e8249f9a
Report an error when a liberty file contains pin references that reference non-existing pins
2018-11-03 18:07:51 +01:00
rafaeltp
f8b97e21f3
using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal
2018-10-21 11:32:44 -07:00
rafaeltp
7b964bfb83
cleaning up for PR
2018-10-20 18:02:59 -07:00
rafaeltp
ce069830c5
fixing code style
2018-10-20 17:57:26 -07:00
rafaeltp
0ad4321781
solves #675
2018-10-20 17:50:21 -07:00
Ruben Undheim
436e3c0a7c
Refactor code to avoid code duplication + added comments
2018-10-20 16:06:48 +02:00
Ruben Undheim
397dfccb30
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
Clifford Wolf
6514443a5c
Merge pull request #672 from daveshah1/fix_bram
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memory_bram: Reset make_outreg when growing read ports
2018-10-19 16:09:11 +02:00
David Shah
3420ae5ca5
memory_bram: Reset make_outreg when growing read ports
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-19 14:46:31 +01:00
Clifford Wolf
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces
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Support for SystemVerilog interfaces and modports
2018-10-18 10:58:47 +02:00
Ruben Undheim
c50afc4246
Documentation improvements etc.
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- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
tklam
f4343b3dc7
stop check_signal_in_fanout from traversing FFs
2018-10-13 23:24:24 +08:00
tklam
302edf0429
stop check_signal_in_fanout from traversing FFs
2018-10-13 23:11:19 +08:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
tklam
b86eb3deef
fix bug: pass by reference
2018-09-26 17:57:39 +08:00
TK Lam
2b89074240
Fix issue #639
2018-09-26 16:11:45 +08:00
Clifford Wolf
592a82c0ad
Merge pull request #625 from aman-goel/master
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Minor revision to -expose in setundef pass
2018-09-14 12:36:13 +02:00
acw1251
5fe16c25b8
Fixed minor typo in "sim" help message
2018-09-12 18:34:27 -04:00
Aman Goel
75c1f8d241
Minor revision to -expose in setundef pass
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Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
2018-09-10 21:44:36 -04:00
Benedikt Tutzer
95d65971f3
added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile
2018-08-20 16:04:43 +02:00
Benedikt Tutzer
d87c7df27f
Two passes are not allowed to have the same filename
2018-08-20 15:28:09 +02:00
Benedikt Tutzer
6d18837d62
Python passes are now looked for in share/plugins and can be added by specifying a relative or absolute path
2018-08-20 15:11:06 +02:00
Clifford Wolf
05466790a6
Merge pull request #606 from cr1901/show-win
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`show` pass `-format` and `-viewer` improvements on Windows
2018-08-19 15:25:46 +02:00
Aman Goel
83b41260f6
Revision to expose option in setundef pass
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Corrects indentation
Simplifications and corrections
2018-08-18 09:08:07 +05:30
Aman Goel
61f002c908
Merge pull request #3 from YosysHQ/master
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Updates from official repo
2018-08-18 08:18:40 +05:30
Benedikt Tutzer
d79a2808cf
Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script
2018-08-16 16:00:11 +02:00
William D. Jones
7ce7ea2eb4
Update show pass documentation with Windows caveats.
2018-08-15 17:18:19 -04:00
William D. Jones
9f91c62348
Fix run_command() when using -format and -viewer in show pass.
2018-08-15 17:18:19 -04:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override
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Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
Clifford Wolf
0eaab6cd1d
Add missing <deque> include (MSVC build fix)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 15:21:59 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf
87aef8f0cc
Add async2sync pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-19 15:31:12 +02:00
Aman Goel
5dcb899e76
Merge pull request #2 from YosysHQ/master
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Merging with official repo
2018-07-18 11:34:18 -04:00
David Shah
459d367913
ecp5: Adding synchronous set/reset support
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-14 16:18:01 +02:00
Aman Goel
4d343fc1cd
Merging with official repo
2018-07-04 15:14:28 -04:00
Clifford Wolf
5f2bc1ce76
Add automatic verific import in hierarchy command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-20 23:45:01 +02:00
Clifford Wolf
675a44b41a
Be slightly less aggressive in "deminout" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-19 14:29:38 +02:00
Edmond Cote
d89560a0ba
Include module name for area summary stats
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The PR prints the name of the module when displaying the final area count.
Pros:
- Easier for the user to `grep` for area information about a specific module
Cons:
- Arguably more verbose, less "pretty" than author desires
Verification:
~~~~
30c30
< Chip area for this module: 20616.349000
---
> Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
< Chip area for this module: 88.697700
---
> Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
< Chip area for this module: 20705.046700
---
> Chip area for top module '\picorv32_axi': 20705.046700
~~~~
2018-06-18 17:29:01 -07:00
Clifford Wolf
f273291dfe
Add setundef -anyseq / -anyconst support to -undriven mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 11:57:28 +02:00
Clifford Wolf
4cd6d5556a
Add "setundef -anyconst"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 11:49:58 +02:00
Clifford Wolf
3ab79a231b
Bugfix in handling of array instances with empty ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-31 18:09:31 +02:00
Clifford Wolf
cee4b1e6bc
Disable memory_dff for initialized FFs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-28 17:16:15 +02:00
Clifford Wolf
74efafc1cf
Add some cleanup code to memory_nordff
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-28 16:42:06 +02:00
Robert Ou
9763e4d830
Fix infinite loop in abc command under emscripten
2018-05-18 22:42:39 -07:00
Robert Ou
bfce3a7479
Add an option to statically link abc into yosys
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This is currently incomplete because the output filter no longer works.
2018-05-18 22:35:28 -07:00
Aman Goel
6e63df6dd0
Correction to -expose with setundef
2018-05-15 13:06:23 -04:00
Clifford Wolf
fe80b39f56
Fix iopadmap for loops between tristate IO buffers
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 14:02:27 +02:00
Clifford Wolf
edd297fb1c
Fix iopadmap for cases where IO pins already have buffers on them
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 13:13:43 +02:00
Aman Goel
8b9a8c7f91
Minor correction
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Minor typo error correction in -expose with setundef
2018-05-14 18:58:49 -04:00
Aman Goel
b4a303a1b7
Corrections to option -expose in setundef pass
2018-05-13 20:13:54 -04:00
Aman Goel
9286acb687
Add option -expose to setundef pass
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Option -expose converts undriven wires to inputs.
Example usage: setundef -undriven -expose [selection]
2018-05-13 16:53:35 -04:00
Clifford Wolf
0fad1570b5
Some cleanups in setundef.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-13 16:36:12 +02:00
Christian Krämer
c1ecb1b2f1
Add "#ifdef __FreeBSD__"
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(Re-commit e3575a8
with corrected author field)
2018-05-13 13:08:26 +02:00
Clifford Wolf
1167538d26
Revert "Add "#ifdef __FreeBSD__""
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This reverts commit e3575a86c5
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2018-05-13 13:06:36 +02:00
Clifford Wolf
587056447e
Add optimization of tristate buffer with constant control input
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-12 15:18:27 +02:00
Clifford Wolf
11406a8082
Add "hierarchy -simcheck"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-12 13:59:13 +02:00
Johnny Sorocil
e3575a86c5
Add "#ifdef __FreeBSD__"
2018-05-05 13:02:44 +02:00
Clifford Wolf
145c685de0
Add ABC FAQ to "help abc"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-04 21:59:31 +02:00
Clifford Wolf
a572b49538
Replace -ignore_redef with -[no]overwrite
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-03 15:25:59 +02:00
Clifford Wolf
705c366a91
Added missing dont_use handling for SR FFs to dfflibmap
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-05 11:01:45 +02:00
Clifford Wolf
665eec3d53
Removed $timescale from "sat" command VCD writer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-29 12:38:41 +02:00
Clifford Wolf
ee3c12d6d9
Chenged "extensions_map" to "extensions_list" in hierarchy.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-27 14:12:57 +02:00
Sergi Granell
f93f8aaa11
passes/hierarchy: Reduce code duplication in expand_module
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This also makes it easier to add new file extensions support.
Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
2018-03-27 09:35:20 +02:00
Clifford Wolf
491c352da7
Add .sv support to "hierarchy -libdir"
2018-03-26 21:19:00 +02:00
Clifford Wolf
08225f49a4
Add "expose -input"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-12 13:52:52 +01:00
Clifford Wolf
83ffb23739
Add "setundef -undef"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-12 13:52:35 +01:00
Clifford Wolf
a74f805ba0
Fix handling of src attributes in flatten
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-10 13:55:30 +01:00
Clifford Wolf
73c01dca65
Add "memory_nordff" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-06 23:31:51 +01:00
Clifford Wolf
61a9e2eeb3
Fix connwrappers help message
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 22:54:34 +01:00
Clifford Wolf
d31584c649
Add $dlatchsr support to clk2fflogic
2018-02-26 12:20:28 +01:00
Clifford Wolf
fba499b866
Fix opt_rmdff handling of $dlatchsr
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-26 11:46:05 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
717abc93a8
Recognize stand-alone obj pattern even when it contains a slash
2018-02-13 14:55:24 +01:00
Clifford Wolf
9337e4999d
Improve log messages in equiv_make
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-19 16:20:40 +01:00
Clifford Wolf
9ac560f5d3
Add "dffinit -highlow" and fix synth_intel
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-09 18:42:19 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
446ccf1f05
Bugfix in hierarchy blackbox module port width handling
2018-01-07 16:35:22 +01:00
Clifford Wolf
c80315cea4
Bugfix in hierarchy handling of blackbox module ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-05 13:28:45 +01:00
Clifford Wolf
fefb652d56
Merge pull request #480 from Fatsie/liberty_value_expression
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Value of properties can be expression.
2018-01-04 13:30:00 +01:00
Clifford Wolf
2d140a44eb
Temporarily derive blackbox modules in hierarchy to evaluate port widths
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-04 13:23:29 +01:00
Staf Verhaegen
92eb841f0a
Value of properties can be expression.
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Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:
input_voltage(CMOS) {
vil : 0.3 * VDD ;
vih : 0.7 * VDD ;
vimin : -0.5 ;
vimax : VDD + 0.5 ;
}
Current implementation just parses the expression but no interpretation is done.
2018-01-03 21:37:17 +00:00
Clifford Wolf
6132e6e72a
Fix a bug in clk2fflogic memory handling
2017-12-14 03:05:55 +01:00
Clifford Wolf
590e6961cb
Add clk2fflogic memory support
2017-12-14 02:07:31 +01:00
Clifford Wolf
88182e46d7
Check for memories in clk2fflogic
2017-12-13 19:14:34 +01:00
Clifford Wolf
ca2adc30c9
Add warnings for driver-driver conflicts between FFs (and other cells) and constants
2017-12-12 17:13:27 +01:00
Clifford Wolf
9ae25039fb
Add support for editline as replacement for readline
2017-11-08 02:55:00 +01:00
Clifford Wolf
4f31cb6dad
Add "ltp" command
2017-10-31 12:40:25 +01:00
Clifford Wolf
c238f45ecf
Fix memory corruption bug in opt_rmdff
2017-10-26 18:02:15 +02:00
Clifford Wolf
1e502ef5a0
Fix typo in opt_clean log message
2017-10-26 18:01:48 +02:00
Clifford Wolf
716dbc9274
Revert 90be0d8
as it causes endless loops for some designs
2017-10-14 11:57:25 +02:00
Kaj Tuomi
90be0d800b
Fix input vector for reduce cells.
2017-10-12 13:05:10 +03:00
Clifford Wolf
7c57d8fbb4
Rewrite ABC output to include proper net names in timing report
2017-10-10 13:32:58 +02:00
Clifford Wolf
3f22f48eeb
Add blackbox command
2017-10-04 18:30:42 +02:00
Andrew Zonenberg
2b65b65d70
Added missing "break"
2017-09-15 17:54:52 -07:00
Andrew Zonenberg
7b3966714c
Implemented off-chain support for extract_reduce
2017-09-15 13:59:18 -07:00
Andrew Zonenberg
3404934c9c
extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored.
2017-09-15 13:59:05 -07:00
Clifford Wolf
ce78717e36
Merge pull request #412 from azonenberg/reduce-fixes
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extract_reduce: Fix segfault on "undriven" inputs
2017-09-14 22:36:25 +02:00
Robert Ou
ab1bf8d661
extract_reduce: Fix segfault on "undriven" inputs
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This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
2017-09-14 12:54:44 -07:00
Clifford Wolf
498526cc0b
Merge pull request #411 from azonenberg/counter-extraction-fixes
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Various improvements and bug fixes to extract_counter
2017-09-14 21:44:26 +02:00
Andrew Zonenberg
66e8986ae7
Minor changes to opt_demorgan requested during code review
2017-09-14 10:35:25 -07:00
Andrew Zonenberg
367d6b2194
Fixed bug where counter extraction on non-GreenPAK devices incorrectly handled parallel counter output
2017-09-14 10:27:10 -07:00
Andrew Zonenberg
c8f2f082c6
Added support for inferring counters with reset to full scale instead of zero
2017-09-14 10:26:43 -07:00
Andrew Zonenberg
122532b7e1
Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
2017-09-14 10:26:32 -07:00
Andrew Zonenberg
0484ad666d
Added support for inferring counters with active-low reset
2017-09-14 10:26:21 -07:00
Andrew Zonenberg
a84172b23b
Initial support for extraction of counters with clock enable
2017-09-14 10:26:10 -07:00
Andrew Zonenberg
c4a70a8cc3
Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters.
2017-09-14 10:25:51 -07:00
Andrew Zonenberg
6da5d36968
Initial version of opt_demorgan is functioning for AND/OR gates. Not the prettiest results for bus inputs, but this can be improved
2017-09-12 18:47:46 -07:00
Clifford Wolf
f9d023c53f
Add src attribute to extra cells generated by proc_dlatch
2017-09-09 10:18:08 +02:00
Clifford Wolf
7d41c5e177
Further improve extract_fa (but still buggy)
2017-09-02 16:39:17 +02:00
Clifford Wolf
18609f3df8
Merge branch 'master' of github.com:cliffordwolf/yosys
2017-09-01 12:35:09 +02:00
Clifford Wolf
8a66bd30c6
Update more stuff to use get_src_attribute() and set_src_attribute()
2017-09-01 12:26:55 +02:00
Jason Lowdermilk
8dc6083de7
updated to use get_src_attribute() and set_src_attribute().
2017-08-31 14:51:56 -06:00
Andrew Zonenberg
ed1e3ed39b
extract_counter: Added optimizations to remove unused high-order bits
2017-08-30 18:15:12 -07:00
Andrew Zonenberg
634f18be96
extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
2017-08-30 16:28:25 -07:00
Jason Lowdermilk
32c0f1193e
Add support for source line tracking through synthesis phase
2017-08-29 14:46:35 -06:00