e9154b1f74
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2019-07-16 14:42:45 -06:00
115411941b
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2019-07-16 13:15:45 -06:00
69014704ef
Explicit verilog final push
2019-07-16 13:13:30 -06:00
e602006a07
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
2019-07-16 12:45:13 -06:00
b810b5cab9
fpga_flow bug fix + upload k8 architecture
2019-07-16 07:04:45 -06:00
35e1962732
Merge branch 'dev' into documentation
2019-07-15 21:19:26 -06:00
1cf4e78502
Update documentation and help
2019-07-15 21:16:15 -06:00
bcc6346533
speeding up identifying unique modules in routing
2019-07-14 13:49:20 -06:00
4c6e245885
speed-up the unique routing process
2019-07-14 12:22:00 -06:00
b690e702f6
adding more info to show the progress bar in backannotating GSBs
2019-07-13 19:53:44 -06:00
aa4cd850ae
try to optimize the runtime of routing uniqueness detection
2019-07-13 18:10:34 -06:00
78578f66c5
bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
2019-07-13 14:48:32 -06:00
ef600bc63f
Save workspace
2019-07-12 15:57:41 -06:00
f140e08093
Pre-Merge modifications
2019-07-12 10:48:43 -06:00
a0f1f8d163
Fix when explicit verilog is NOT used
2019-07-12 10:39:31 -06:00
f0ecc51b51
bug fixing to resolve the conflicts between explicit port map and standard cell map
2019-07-12 10:38:20 -06:00
e65cf9f5fd
Update ERI-demo
2019-07-12 08:55:19 -06:00
40d3460bac
Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
2019-07-11 22:13:30 -06:00
e461cd0b99
Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
2019-07-11 22:09:49 -06:00
1431ee2f82
Fix Explicit verilog
2019-07-11 22:09:34 -06:00
cffdebd912
bug fixed for the tileable RR graph generator for heterogeneous blocks
2019-07-11 21:02:09 -06:00
c9b84f61c9
Hot fix
2019-07-11 17:39:02 -06:00
d0cd5a2bc1
Hot fix
2019-07-11 17:27:31 -06:00
9c203ca4d2
bug fixing in SDC generator
2019-07-11 17:10:08 -06:00
f4be375637
Latest version explicit
2019-07-11 14:33:56 -06:00
31749fe62b
fix bugs in fpga_flow.pl
2019-07-10 21:12:00 -06:00
a90316e9f4
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2019-07-10 15:13:46 -06:00
acee0161c7
Merge branch 'tileable_routing' into dev
2019-07-10 15:13:24 -06:00
6441f2ebe7
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2019-07-10 14:16:55 -06:00
0a978db866
Fix regression test
2019-07-10 14:16:34 -06:00
b7f9831bd2
add statistics for unique GSBs
2019-07-10 13:08:03 -06:00
c6a4d29ed8
Merge branch 'tileable_routing' into dev
2019-07-10 12:05:43 -06:00
57ae5dbbec
bug fixing for rectangle FPGA sizes
2019-07-09 20:47:52 -06:00
edfe3144c3
update profiling, found where runtime is lost
2019-07-09 20:28:01 -06:00
737cc2874f
Merge branch 'tileable_routing' into dev
2019-07-09 17:42:44 -06:00
65f696c1d7
fix critical bugs in rectangle floorplan
2019-07-09 17:41:20 -06:00
4ca0967453
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2019-07-09 14:35:51 -06:00
792ba23f4f
Correction pre-merge
2019-07-09 14:34:34 -06:00
589f58b55e
Regression test succeeded
2019-07-09 09:18:06 -06:00
25f5bc7792
Latest version, not stable yet but close
2019-07-09 08:34:01 -06:00
5d5e09fcdb
minor fix in trying to accelerate the unique routing functions
2019-07-08 17:12:36 -06:00
df0a3d23a3
Correction top module
2019-07-08 10:23:14 -06:00
ae05c553d5
Top module done
2019-07-08 09:48:33 -06:00
76fefdb876
bug fixing in Fc_in and be serious in the performance of rr_graph
2019-07-05 16:23:15 -06:00
c62762ce59
bug fixing in assign ipins to tracks using Fc_in
2019-07-05 13:42:22 -06:00
64d8e9663a
minor fix to satisfy Fc_in and Fc_out
2019-07-05 13:13:35 -06:00
3077efa74f
add option to compact tileable routing arch
2019-07-04 17:13:34 -06:00
d64aeef5c4
add profiling to routing compact process
2019-07-03 16:57:34 -06:00
1a1da30ae9
fixed a critical bug in using tileable route chan W
2019-07-03 16:46:43 -06:00
b79d276ea9
add profiling to fpga_x2p_setup
2019-07-03 14:44:54 -06:00
d5137eb424
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
2019-07-03 14:31:18 -06:00
5195faab8b
Merge branch 'dev' into tileable_routing
2019-07-03 14:30:39 -06:00
4f3cb0bdf3
added tileable routing chanW adaption to fixed W router
2019-07-03 14:29:50 -06:00
443a73954f
Removed all local files
...
+ Removed local configurations and scripts from previous commit
2019-07-03 14:26:06 -06:00
57ad71438b
Merging ganesh_dev to dev
...
- Added spice_tool option in fpga_flow
- Some local customization
2019-07-03 13:39:52 -06:00
0c3e8bb70a
add a new option to the router to enable conversion of route_chan_width to be tileable
2019-07-03 12:11:48 -06:00
02398818a9
update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area
2019-07-03 10:33:02 -06:00
4392c6bc3a
bug fixing in fpga_flow scripts and add more print-out message for VPR
2019-07-02 15:34:59 -06:00
b08513d902
Big chunk added on the routing part of the explicit mapping
2019-07-02 14:12:42 -06:00
8f5ad2eb67
Snapshot of progress
2019-07-02 10:10:48 -06:00
95674c4687
added Switch Block SubType and SubFs for tileable rr_graph generation
2019-07-02 10:00:02 -06:00
44301bfd77
updated SPICE generator to avoid issues on clb2clb_direct
2019-07-02 09:01:52 -06:00
5b25bbb120
bug fixed for direct connection in CBs and direct connection in top netlist
2019-07-01 17:25:00 -06:00
f189ef1d8f
Done with the submodules
2019-07-01 14:24:09 -06:00
370ce23646
Mux explicit verilog done
2019-07-01 13:58:24 -06:00
863e8677c0
Further add new functions to tree
2019-07-01 12:12:36 -06:00
0e04b88c8f
Include new files in the parameter spreading
2019-07-01 11:27:48 -06:00
1332ba62e8
update tileable rr_graph generator to improve routability and also enable assoicated testing
2019-06-27 17:52:25 -06:00
15c536e9b4
minor fixing in printing the rr_node stats
2019-06-27 16:34:21 -06:00
04eb6d3488
Correction pre-merge
2019-06-27 14:33:06 -06:00
11e6350214
Merge remote-tracking branch 'origin/multimode_clb' into ganesh_dev
2019-06-27 14:22:40 -06:00
7c742f1cbb
Stable, is_explicit propagated through the code. Not implemented though except for muxes
2019-06-27 10:29:57 -06:00
8edd85c9fc
keep fixing bugs in verilog SDC generator for tileable CBs
2019-06-26 22:58:52 -06:00
711e369fe7
fixing bugs in the SDC generator and report_timing
2019-06-26 18:09:09 -06:00
0fe54d87d5
fixed a bug in SDC generator for constraining SBs in tileable arch
2019-06-26 17:06:14 -06:00
0ce9846e47
Stable, unfinished
2019-06-26 16:54:41 -06:00
7d85eb544d
start fixing bugs for SDC generator when using tileable arch
2019-06-26 16:48:17 -06:00
f5920c7422
fix bugs in ptc_num using for SB
2019-06-26 16:21:02 -06:00
3d8200e217
critical bug fixed in bitstream generator for compact routing hierarchy
2019-06-26 15:51:11 -06:00
d2ed82d14d
Merge branch 'tileable_routing' into multimode_clb
2019-06-26 15:00:39 -06:00
57616361c2
fixed critical bugs in cb configuration port indices
2019-06-26 14:58:52 -06:00
d2bd2be76b
Warnings correction in the make sequence
2019-06-26 14:33:12 -06:00
87ddca9f57
commiting current work. Stable but function not implemented yet
2019-06-26 14:22:02 -06:00
42f85004b6
fix bugs in finding the ending SB of a rr_node
2019-06-26 14:13:41 -06:00
9b6a4b39bb
Merge branch 'tileable_routing' into multimode_clb
2019-06-26 11:36:08 -06:00
c879e7f6c5
fixed a critical bug when instanciating Connection blocks
2019-06-26 11:33:02 -06:00
b7c2954b91
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-06-26 10:51:55 -06:00
8f21a3b177
Memory leakage correction
2019-06-26 10:50:38 -06:00
d50fb7ee19
fixed the bug in determine passing wires for rr_gsb
2019-06-26 10:50:23 -06:00
ec504049ef
Update Testbenches to increase accuracy + commented compact routing option until debug
2019-06-26 10:01:12 -06:00
a3670bb752
Merge branch 'multimode_clb' into tileable_routing
2019-06-26 09:45:04 -06:00
56557b94e7
Bug Fix
2019-06-26 08:53:46 -06:00
3c0ef2067d
fixed critical bugs in pass_tracks identification and update regression test for tileable arch
2019-06-25 21:59:38 -06:00
bb250ddef9
Bug fix in cpp
2019-06-25 16:47:10 -06:00
6d3066174b
Merge remote-tracking branch 'origin/fpga_spice' into ganesh_dev
2019-06-25 15:12:13 -06:00
4d3b5f12b4
fixed bugs for UNIVERSAL and WILTON switch blocks
2019-06-25 14:15:29 -06:00
332ce17f03
Division between horizontal and vertical analysis
2019-06-25 13:44:41 -06:00
a88263a4c2
update rr_block writer to include IPINs in XML files
2019-06-25 11:17:22 -06:00
785b560bd5
sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now
2019-06-24 22:46:56 -06:00
fd301eeb66
many bug fixing and now start improving the routability of tileable rr_graph
2019-06-24 17:33:29 -06:00
0d62661c71
bug fixing and spot critical bugs in directlist parser
2019-06-23 20:52:38 -06:00
cdd4af9c58
vpr likes the tileable rr_graph while fpga_x2p does not
2019-06-23 18:11:13 -06:00
59df305668
bug fixing and reorganize rr_graph builder source files
2019-06-23 16:40:13 -06:00
2837f44df2
bug fixing for tileable rr_graph generator.
2019-06-22 20:41:06 -06:00
7c38b32eb1
keep bug fixing for tileable rr_graph generator
2019-06-21 22:51:11 -06:00
1b91c32121
Merge branch 'multimode_clb' into tileable_routing
2019-06-21 17:59:55 -06:00
41954056ce
many bug fixing for tileable rr_graph generator. Still debugging
2019-06-21 17:58:46 -06:00
0a42f6a796
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-06-21 15:47:14 -06:00
c0d7099cd6
Allow CB on top of blocks with height > 1
2019-06-21 15:46:05 -06:00
d48fd959a9
keep bug fixing for tileable rr_graph generator
2019-06-20 22:30:26 -06:00
548242b368
plug-in tileable rr generator which can be enable by a XML property
2019-06-20 21:06:26 -06:00
cf82d87e11
Merge branch 'multimode_clb' into tileable_routing
2019-06-20 18:18:20 -06:00
baab9c4a21
basically finished the coding of tileable rr_graph generator. testing to go
2019-06-20 18:17:07 -06:00
be25b6dd66
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-06-20 14:11:03 -06:00
3bd6c40a10
Report timing modified to have only one liners
2019-06-20 14:10:39 -06:00
a7502bb43b
Avoid configuration bits for module wihch don't require them
2019-06-20 09:40:41 -06:00
e7f2bd3b7c
Merge branch 'multimode_clb' into tileable_routing
2019-06-19 21:31:54 -06:00
2f15d2d13c
keep developing tileable rr_graph, track2ipin and opin2track to go
2019-06-19 21:30:16 -06:00
ff00e4c79c
Free only if it's possible to free
2019-06-19 16:15:30 -06:00
ba15358564
developing ipin2track mapping for tiles
2019-06-18 18:06:21 -06:00
9ca1b42f4c
developing switch block pattern for tileable routing architecture
2019-06-18 16:52:42 -06:00
352c97302b
start building object GSB graph
2019-06-17 22:10:30 -06:00
f4191315da
use rr_gsb to build edges of rr_graph
2019-06-17 18:01:45 -06:00
51ff150a77
bug fixing in tileable rr_graph generator
2019-06-17 10:16:08 -06:00
0d14fef53e
bug fixing in setting CHANX and CHANY nodes in tileable rr_graph generator
2019-06-16 23:02:18 -06:00
04ffb99ca6
Merge branch 'multimode_clb' into tileable_routing
2019-06-16 16:01:30 -06:00
57a4ad1f99
Break memories even in the clb sdc
2019-06-16 14:27:29 -06:00
1af3b5ef55
set chan_rr_nodes in tileable rr_graph builder
2019-06-16 14:23:19 -06:00
8c9cc003ea
developing routing track rr_node set up in tileable routing architecture
2019-06-15 18:11:08 -06:00
155c8d4924
fix CMakeList bug in disabling VPR graphics
2019-06-15 13:21:25 -06:00
d19b470b33
Merge branch 'tileable_routing' into multimode_clb
...
Conflicts:
vpr7_x2p/vpr/regression_verilog.sh
2019-06-15 12:25:30 -06:00
c8bf456097
bug fixing for memory leaking in allocating pb_rr_graph and power estimation
2019-06-15 12:23:36 -06:00
d3296d0975
developing tileable rr_graph builder
2019-06-14 22:35:42 -06:00
a33627606e
developing tileable routing track arrangement
2019-06-14 17:35:40 -06:00
29dadc51b4
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-06-14 11:46:02 -06:00
c76dbaac33
Update regression test avoiding overwritting files
2019-06-14 11:44:44 -06:00
4d2a3680be
support bus explicit port mapping to standard cells (for BRAMs)
2019-06-14 11:09:15 -06:00
0902d1e75a
c++ string is not working, use char which is stable
2019-06-13 18:38:46 -06:00
5f61cd8876
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
...
Conflicts:
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
2019-06-13 16:32:39 -06:00
af1628abfe
use bus port for primitives in Verilog generator
2019-06-13 16:26:58 -06:00
dddbbac85c
merge from multimode_clb bug fixing
2019-06-13 15:59:34 -06:00
15b4cc9ecb
Error correction in memory generation for pb_types without modes
2019-06-13 15:34:25 -06:00
43128ad3f0
fix a bug in formal verification port for memory bank configuration circuits
2019-06-13 15:33:13 -06:00
44d21ebb90
fixed a bug in Verilog generator supporting SRAM5T
2019-06-13 14:42:39 -06:00
5ae4dec0af
fix bugs in CMakeList on enable/disable VPR Graphics
2019-06-12 22:48:00 -06:00
1d00e3665b
start developing tileable_rr_graph_builder
2019-06-11 16:50:40 -06:00
65b5454f3a
start developing tileable_rr_graph_builder
2019-06-11 16:49:10 -06:00
bf13c1f731
Add a script to create a new file with correct path rather than overwrite the existing
2019-06-11 14:28:58 -06:00
1da363f7f1
Merge remote-tracking branch 'lnis_open_fpga/fpga_spice' into ganesh_dev
2019-06-11 11:59:54 -06:00
7245917b9c
fix a bug for iopad SPICE generation
2019-06-11 11:43:56 -06:00
1093e341a8
Added additional architecure files
2019-06-11 11:26:44 -06:00
1776ae3ec8
add explicit port mapping for inverters of memory decoders
2019-06-10 17:36:14 -06:00
8e3ad675e0
use sstream for rr_block verilog writer
2019-06-10 16:23:35 -06:00
009e5244d3
minor fix on the port direction of configuration peripherals for memory decoders
2019-06-10 15:39:35 -06:00
f43955037c
remove input port requirements for SRAM circuit module
2019-06-10 15:29:44 -06:00
e4f70771a2
updated SDC generator to embrace the RRGSB data structure
2019-06-10 14:47:27 -06:00
8a8f4153ce
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
2019-06-10 12:50:10 -06:00
e31407f693
start cleaning up SDC generator with new RRGSB data structure
2019-06-10 10:57:26 -06:00
17bc7fc296
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
2019-06-08 20:11:22 -06:00
61e359efc5
Enable an option to disable/enable graphics in VPR compilation
2019-06-08 15:08:17 -06:00
90696def6d
remove vpr Makefile
2019-06-07 23:44:39 -06:00
d737c4ff46
fix path in regression test! TODO: must keep a duplicated copy for template.xml
2019-06-07 23:31:42 -06:00
8c5ec4572d
revert string to sprintf
2019-06-07 20:20:41 -06:00
0f1ed19ad0
Revert to the use of sprintf instead std::string. Have no idea why string is not working
2019-06-07 18:54:57 -06:00
44ce0e8834
update gsb unique module detection and fix formal verification port direction
2019-06-07 17:18:38 -06:00
24d53390d8
clean up DeviceRRGSB internal data and member functions
2019-06-07 14:45:56 -06:00
c9f810ceb6
update rr_gsb to build connection blocks
2019-06-07 11:01:55 -06:00
472aff5acb
add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
2019-06-06 23:45:21 -06:00
ce9fc5696c
rename rr_switch_block to rr_gsb, a generic block
2019-06-06 17:41:01 -06:00
8c1e7b799f
fixed critical bugs in Connection Block Unique Module detection
2019-06-06 16:31:50 -06:00
4f543c510c
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-06-06 12:50:03 -06:00
873e4d989f
fine-tuning Verilog format and node addition to rr_blocks
2019-06-06 12:48:41 -06:00
182d49da45
Update regression test scripts
2019-06-06 11:47:51 -06:00
c2de0eefb1
fix redundant comma in SB Verilog module
2019-06-06 09:15:05 -06:00
b9e1b1afc4
fix a critical bug in num_reserved_sram_ports
2019-06-05 17:31:01 -06:00
aaf8d23971
fix critical bugs in routing submodules
2019-06-05 16:43:18 -06:00
01e075377d
fix typo in Verilog generation
2019-06-05 15:30:34 -06:00
21d0cb52bc
Merge remote-tracking branch 'origin' into tileable_sb
2019-06-05 13:31:49 -06:00
24ca3104b0
fix minor bugs in Switch Block submodules
2019-06-05 13:30:55 -06:00
0f87ae9886
support switch block submodule Verilog generation by segments
2019-06-05 12:56:05 -06:00
84fabbd43b
Fix sdc analysis bug related to virtual nodes + add the option in regression test
2019-06-05 12:10:28 -06:00
d24488092d
Fix bug
2019-06-05 11:40:04 -06:00
c2d8fa00ba
add rr_block unique_side_module verilog generation
2019-06-04 17:47:40 -06:00
a2f6ded2a2
Add path modification in file changing a keyword into OpenFPGA full path
2019-06-04 15:21:15 -06:00
98b82c17be
bug fixing for clear RRSwitchBlock
2019-06-04 14:02:49 -06:00
2c6780ab92
add side mirror detection for RRSwitchBlock
2019-06-04 13:01:22 -06:00
813470d459
Test Cmake fix
2019-06-03 10:31:44 -06:00
7368e6d7e4
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-31 11:01:07 -06:00
737300eb54
Fix regression test
2019-05-31 11:00:30 -06:00
1932d00309
Correction of the SDC to remove global clocks
2019-05-30 15:04:21 -06:00
ba05a08ef0
Path correction in tech debugging + correction of yosys rewrite file in fpga_flow
2019-05-30 09:52:19 -06:00
46fa1197b0
Test reading tech file
2019-05-29 16:43:56 -06:00
74ee6bad7f
Update spice path in architecture
2019-05-29 10:08:58 -06:00
5b15a746d3
add num_driver_nodes to Switch Block XML writter
2019-05-28 20:52:33 -06:00
5ed076dfb4
fixed a critical bug in rotating
2019-05-28 17:55:09 -06:00
9cc5518d5a
keep adding segment information for SB XML outputter
2019-05-28 15:59:55 -06:00
e7e18eb4c1
Add more information in SB XML outputter
2019-05-28 15:56:41 -06:00
ca363da30c
add options to specify output directory of SB XML
2019-05-28 15:19:10 -06:00
6b51b42ee7
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-28 14:53:44 -06:00
af91fca1e0
add rr_blocks XML writer to help debugging Switch Block Rotation
2019-05-28 14:52:44 -06:00
3da216f297
correction Null issue for the flat model
2019-05-28 14:15:24 -06:00
ffdcd4bb9c
Path correction 2
2019-05-28 11:59:09 -06:00
c75ffa858b
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-28 11:26:16 -06:00
6f30d3ad05
support rotation on segment groups inside RRChan and improve rotatable mirror searching
2019-05-28 11:25:16 -06:00
20f80a73e7
Correct path to tech files
2019-05-28 11:24:03 -06:00
0f5666ea11
fixed the bug in mirror node direction
2019-05-27 21:58:21 -06:00
eece161d58
keep debugging on Switch Block rotation
2019-05-27 21:10:30 -06:00
5720217cfd
Add copy constructor for RRChan, RRSwitchBlock etc.
2019-05-27 15:44:34 -06:00
1bea9870fc
developed new rotating methods for RRSwitchBlocks, debugging ongoing
2019-05-26 23:35:30 -06:00
4b852afeac
skip rotating mirror detection which is too time-consuming
2019-05-25 23:41:46 -06:00
22e71f5847
Add rotate one side of switch block functionality
2019-05-25 22:48:07 -06:00
858a323228
Add more support for rotating Switch Blocks
2019-05-25 21:26:35 -06:00
2eab0b1c1c
update unique_mirror search algorithm for Switch Blocks
2019-05-25 19:54:15 -06:00
d3eae80e64
implemented an native way in finding rotable Switch blocks
2019-05-25 19:37:18 -06:00
ae0248fbc6
debugging SwitchBlock rotating
2019-05-24 23:10:30 -06:00
9adc2945c8
add rotate functionality for RRSwitchBlock
2019-05-24 21:40:16 -06:00
02b48d036d
clean warnings
2019-05-24 16:48:08 -06:00
2c46da6888
clean-up warnings Verilog routing generator
2019-05-24 16:29:17 -06:00
27b996337a
fixed a critical bug in Compact Verilog generation for SB/CBs
2019-05-24 16:14:46 -06:00
1ade1f1d3f
update SDC generator disabled_unused_mux by using RRSwitchBlock
2019-05-24 15:42:00 -06:00
f27b88db8d
Use RRChan in SDC generator to replace old data structures
2019-05-24 15:34:56 -06:00
27c234711e
clean up warnings in SDC pb_type generator
2019-05-24 15:23:38 -06:00
924136e7a2
Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
2019-05-24 15:10:08 -06:00
994b90ae53
updated report_timing for using RRSwitchBlock
2019-05-24 14:25:51 -06:00
eef1312325
updated bitstream to use new RRSwitchBlock as well as the report timing engine
2019-05-24 12:54:10 -06:00
8f4f590ff9
update Verilog compact_netlist outputter with RRSwitchBlock classes
2019-05-23 21:52:12 -06:00
ea8c36ce6e
upgrade Verilog SB generator using the RRSwitchBlock
2019-05-23 17:37:39 -06:00
4aab93b729
update class rr_switch_block and be ready for updating the downstream verilog generator
2019-05-22 22:04:31 -06:00
efbc454cdd
Add Class for RRSwtichBlock and plug-in to replace the old t_sb
2019-05-22 12:34:06 -06:00
ec3b4c86c4
update file organization and be ready for SB/CB class
2019-05-21 12:15:38 -06:00
8186d6dd11
reorganize files and clean some warnings
2019-05-21 10:17:54 -06:00
b185a17359
add routing_channel unique module generation
2019-05-20 22:33:17 -06:00
ceee28226e
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-20 16:47:07 -06:00
8b520349e7
fixed a bug for rram based fpga when using explicit verilog port mapping
2019-05-20 16:44:47 -06:00
4f921b03da
Add travis full path to avoid missing sources
2019-05-16 15:51:10 -06:00
f31339bb5c
Correctly instantiate script variables
2019-05-16 14:30:16 -06:00
57d75520a6
Verilog verification with Travis
2019-05-15 15:57:05 -06:00
e44e228153
Force graphics to false
2019-05-15 15:01:54 -06:00
f940c4fd59
Third try to fix issues with graphics on mac
2019-05-15 13:22:14 -06:00
a55886a4d9
Second try to fix travis autotest adding x11 in macos packages
2019-05-15 09:28:29 -06:00
1961b18d14
Fix CMakeList to avoid MacOS build failure
2019-05-14 18:15:13 -06:00
99beeb48cc
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-13 16:42:27 -06:00
a3656dde45
Add missing Verilog source, Archictecture folder and Testbenches correction
2019-05-13 16:41:35 -06:00
b48a27acf0
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-13 14:45:57 -06:00
2019840d7c
cleaned unused variables
2019-05-13 14:45:02 -06:00
3313eac23b
add rr_chan obj
2019-05-10 22:50:08 -06:00
9c05a4fb0a
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-10 14:09:23 -06:00
ff9b84d800
Bug fix in Icarus requirement
2019-05-10 14:07:32 -06:00
be4643b8a6
updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated
2019-05-10 10:21:06 -06:00
5c646f5de7
fix bugs in routing identification
2019-05-09 21:40:06 -06:00
a9df922412
finish the identification on mirror switch and connection blocks
...
Verilog generator to be updated
2019-05-09 21:31:39 -06:00
a3c3f2b892
developing compact routing hierarchy
2019-05-08 20:49:21 -06:00
4c6639218e
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-08 14:30:33 -06:00
e305e60ee4
minor fix on the shell interface of VPR
2019-05-08 14:29:58 -06:00
4f386de2ef
gen_xxx functions create mem-leaks because the mem is dynamically allocated inside and not freed. TBD later everywhere
2019-05-06 17:25:29 -06:00
3b62f8e024
Conversion from s to ns for the loop breaking delays
2019-05-06 16:12:30 -06:00
a5a1a376ab
Modified code for cleaner delay naming convention
2019-05-06 12:52:49 -06:00
6e6ae1cc3d
fixed bugs in CMakeLists.txt and Makefile
2019-05-03 23:03:04 -06:00
4e3487b691
Add latest abc and update ace dependence
2019-05-03 18:56:03 -06:00
70b66e0799
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-03 14:22:20 -06:00
7860042276
added before after loop breaker constraining
2019-05-03 14:00:06 -06:00
11cf30b239
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-03 11:54:35 -06:00
5a97e3e602
update Makefile t
2019-05-03 11:48:41 -06:00
4e330ee463
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-03 10:43:22 -06:00
921b694400
Bug fix sdc breaking loop of edges outside current interconnect
2019-05-03 10:42:35 -06:00
42f20eda60
Add the user matching for internal register in formal verification script generation
2019-05-03 10:24:02 -06:00
974af5a2ae
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-04-30 14:30:38 -06:00
42daadee2f
critical bug fixing
2019-04-30 14:30:17 -06:00
1ab4688339
Create no segment constraint in loop_breaker if none is given by user
2019-04-30 12:30:07 -06:00
c46c0fc97d
bug fixing for SDC generator
2019-04-26 14:07:44 -06:00
46d44fa42a
Update VPR7 X2P with new engine
2019-04-26 12:23:47 -06:00
8eeb144f32
Streamline Makefile and Travis for Mac OS
2019-04-10 15:22:20 +08:00
c4b42726c4
fixes easing thehandling by the user.
2019-03-31 07:55:05 -06:00
b06df18a89
Update rr_graph_area.c
2019-03-11 21:46:42 +08:00
213f94ddee
Correct preconfiguration
2019-01-31 16:43:47 -07:00
5e36aa82c5
fixa bug in determining mux structure
2019-01-22 13:54:50 -07:00
f3e7ae0823
Hot fix
2019-01-10 17:37:15 -07:00
b8187bbca5
fix a bug for supporting default circuit_model of LUTs and FFs
2019-01-10 15:10:05 -07:00
4ae3aa517c
go.sh replaces the paths now
2019-01-09 23:16:43 -07:00
510c27f816
Removed commercial scripts, replaced by academia ones
2019-01-09 11:56:07 -07:00
3b4fc16c60
Adding help message on the go.sh
2019-01-09 11:54:28 -07:00
66701838ff
update relative path in ARCH XML
2019-01-08 11:41:24 -07:00
b80e435548
Correct manual testbench generation bug
2019-01-07 18:03:56 -07:00
7ff245448b
Add new benchmark and modify go.sh to use it
2018-12-26 04:24:26 -07:00
21dc8a006f
Change simulator script generation (waves)
2018-12-14 14:40:04 -07:00
ee6b1d6cd6
adapt arch xml and act for demo
2018-12-13 22:46:40 -07:00
3d9e913e4e
add a benchmark fifo
2018-12-12 16:45:33 -07:00
cc5a01d476
Fix waveform generation + add benchmark and update go.sh
2018-12-11 22:21:39 -07:00
a70b0ac9ac
Correct go.sh
2018-12-11 15:51:21 -07:00
317c3b59c9
Update go.sh and upload pip_add.v
2018-12-11 15:47:05 -07:00
fb0992bd85
Update go.sh and Makefile
2018-12-11 15:31:32 -07:00
c2c4e78639
Add pip_add benchmark
2018-12-11 15:29:48 -07:00
f5ea3ff233
Add an autochecked configuration free testbench
2018-12-11 14:44:13 -07:00
72fbd8d6a8
update blif reader to identify clock signals
2018-12-10 13:28:44 -07:00
a69c2e1882
Add security in checking to avoid simulation glitch error
2018-12-10 09:46:16 -07:00
7020d9b4b6
Edit waveform generator + fix clock mapping in autochecked testbench
2018-12-09 15:48:59 -07:00
5e94b7093d
Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
2018-12-08 22:57:54 -07:00
10866d1852
Correct verilog syntax error in autocheck testbench
2018-12-08 17:40:23 -07:00
d716b67e23
Correct syntax error in autocheck testbench
2018-12-08 17:29:56 -07:00
0580d8243f
Add Autochek testbench option
2018-12-08 17:19:12 -07:00
79930982cf
Changed for the naming
2018-12-08 16:19:38 -07:00
4440066565
added the script to launch vpr with picorv
2018-12-08 16:01:58 -07:00
c130404158
add a section for picorv generation through the flow
2018-12-08 11:33:14 -07:00
4cc875a5a5
fix a bug in wired LUT
2018-12-06 18:00:17 -07:00
b3c1018e28
fixed a bug in wired LUT
2018-12-06 16:50:30 -07:00
eebdf7cb10
Add possibility to choose default value for initialization
2018-12-06 15:34:14 -07:00
b6bb419e1d
add a ModelSim option
2018-12-06 14:13:37 -07:00
fe47b3d21f
Changing arch from memory dec to scff. Get the bitstream from go.sh
2018-12-06 14:03:17 -07:00
8281b7346b
Edit auto-generated modelsim script
2018-12-05 16:15:29 -07:00
44b7f7f3d4
Correct sub_modules.v generation to include decoders.v when necessary
2018-12-05 13:52:25 -07:00
dc4accedd9
Add forgottent files + add parameter transmission from verilog_api.c
2018-12-05 11:33:14 -07:00
9a8c7b391a
Add process for modelsim script autogeneration
2018-12-05 09:20:47 -07:00
75d64db0f9
Add verilog header sub_module.v file generation
2018-12-04 18:42:47 -07:00
8ac566ecc0
Add timing and initialization for simulation
2018-12-04 17:32:09 -07:00
70751551b5
fix a bug in wired LUT support
2018-11-30 21:33:31 -07:00
e223868df8
fix bugs for wired LUTs
2018-11-27 12:46:30 -07:00
de2bc18bbb
bugs fixed for shift register benchmark
2018-11-26 16:58:45 -07:00
9611576d6a
Update on the examples to respect the new syntax
2018-11-19 15:50:29 -07:00
861c449606
support wired LUT in FPGA-SPICE and FPGA-Verilog
2018-11-15 15:57:49 -07:00
f7d7a056da
Modification of the fpga_spice_utils
2018-11-15 14:11:55 -07:00
c81d00bb51
Correction of the double free bug
2018-11-15 13:55:16 -07:00
c67ba5f58a
clean up codes
2018-09-27 14:26:08 -06:00
31c3eba111
ReadMe modifications to add the beginning of the FPGA-SPICE tutorial
...
Modifications on the addresses aswell and the different commands when they were not working.
To do still:
-create a script to change the addresses when needed
-continue the tutorial
2018-09-27 09:33:39 -06:00
681cca99a4
fix a bug in tapbuf
2018-09-21 19:00:22 -06:00
d683134b12
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00
tangxifan
Baudouin Chauviere
AurelienUoU
Ganesh Gore
giacomin
Baudouin Chauviere