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Fix waveform generation + add benchmark and update go.sh

This commit is contained in:
AurelienUoU 2018-12-11 22:21:39 -07:00
parent a70b0ac9ac
commit cc5a01d476
5 changed files with 85 additions and 3 deletions
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19
vpr7_x2p/vpr/Circuits/fifo_1bit.act Normal file
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@ -0,0 +1,19 @@
rst 0.001 0.198200
clk 0.492000 0.201600
data_in 0.5 0.2
int_reg[0] 0.261800 0.185200
int_reg[1] 0.213800 0.151200
int_reg[2] 0.172600 0.126000
int_reg[3] 0.136800 0.104000
int_reg[4] 0.106400 0.077600
int_reg[5] 0.085400 0.064000
int_reg[6] 0.066400 0.048400
data_out 0.054400 0.038800
n9 0.261800 0.047556
n14 0.213800 0.087368
n19 0.172600 0.090992
n24 0.136800 0.094640
n29 0.106400 0.097699
n34 0.085400 0.098685
n39 0.066400 0.100218
n44 0.054400 0.100885

31
vpr7_x2p/vpr/Circuits/fifo_1bit.blif Normal file
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@ -0,0 +1,31 @@
# Benchmark "fifo_1bit" written by ABC on Tue Dec 11 18:55:50 2018
.model fifo_1bit
.inputs rst clk data_in
.outputs data_out
.latch n9 int_reg[0] re clk 0
.latch n14 int_reg[1] re clk 0
.latch n19 int_reg[2] re clk 0
.latch n24 int_reg[3] re clk 0
.latch n29 int_reg[4] re clk 0
.latch n34 int_reg[5] re clk 0
.latch n39 int_reg[6] re clk 0
.latch n44 data_out re clk 0
.names data_in rst n9
10 1
.names int_reg[0] rst n14
10 1
.names int_reg[1] rst n19
10 1
.names int_reg[2] rst n24
10 1
.names int_reg[3] rst n29
10 1
.names int_reg[4] rst n34
10 1
.names int_reg[5] rst n39
10 1
.names int_reg[6] rst n44
10 1
.end

32
vpr7_x2p/vpr/Circuits/fifo_1bit.v Normal file
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@ -0,0 +1,32 @@
///////////////////////////////
// //
// fifo_1bit benchmark //
// //
///////////////////////////////
module fifo_1bit(
rst,
clk,
data_in,
data_out );
input rst;
input clk;
input data_in;
output data_out;
reg[7:0] int_reg;
assign data_out = int_reg[7];
always@(posedge clk or posedge rst) begin
if(rst) begin
int_reg <= 8'h00;
end
else begin
int_reg[0] <= data_in;
int_reg[7:1] = int_reg[6:0];
end
end
endmodule

4
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_top_netlist.c
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@ -2440,11 +2440,11 @@ void dump_verilog_top_testbench_stimuli_serial_version(FILE* fp,
fprintf(fp, " %s%s%s[%d] = ~%s%s%s[%d];\n #%.2f\n",
gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx,
gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx,
(op_clock_period * 2 * ((int)(cur_spice_net_info->probability / cur_spice_net_info->density)+ iblock) / verilog_sim_timescale));
(((float)(int)((100 * op_clock_period) / verilog_sim_timescale) / 100) * ((int)(cur_spice_net_info->probability / cur_spice_net_info->density)+ iblock)));
fprintf(fp, " %s%s%s[%d] = ~%s%s%s[%d];\n #%.2f;\n",
gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx,
gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx,
(op_clock_period * 2 * ((int)((cur_spice_net_info->density / cur_spice_net_info->probability) * 2.5 + iblock)) / verilog_sim_timescale));
(((float)(int)((100 * op_clock_period) / verilog_sim_timescale) / 100) * ((int)(cur_spice_net_info->density / cur_spice_net_info->probability) * 2.5 + iblock)));
fprintf(fp, " end \n");
fprintf(fp, "\n");
found_mapped_inpad++;

2
vpr7_x2p/vpr/go.sh
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@ -1,6 +1,6 @@
#!/bin/sh
# Example of how to run vprset circuit_name = pip_add
set circuit_name = pip_add
set circuit_name = fifo_1bit
set arch_file = ${PWD}/ARCH/k6_N10_scan_chain_tsmc40nm_TT.xml
set circuit_blif = ${PWD}/Circuits/${circuit_name}.blif
set circuit_act = ${PWD}/Circuits/${circuit_name}.act