riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
187 Commits 70 Branches 8 Tags 105 MiB
Verilog 51.9%
C++ 20.8%
Tcl 20.5%
Coq 5.7%
Python 0.5%
Other 0.5%
Go to file
AurelienUoU cc5a01d476 Fix waveform generation + add benchmark and update go.sh 2018-12-11 22:21:39 -07:00
OpenSTA@7592f12e54 Implementation of OpenSTA in the project 2018-11-08 13:13:45 -07:00
abc_with_bb_support need abc_with_bb_support for ace compilation 2018-12-09 15:45:09 -07:00
ace2 Fixing minor bugs 2018-09-06 14:25:23 -06:00
compilation Correction of the compilation to automatically get the submodules 2018-11-08 15:56:22 -07:00
docs Update index.rst 2018-12-10 13:46:38 -07:00
examples Update on the examples to respect the new syntax 2018-11-19 15:50:29 -07:00
fpga_flow removed the now useless tutorial part 2018-12-10 13:57:01 -07:00
vpr7_x2p Fix waveform generation + add benchmark and update go.sh 2018-12-11 22:21:39 -07:00
yosys Added the aliases for Yosys-ABC 2018-12-06 15:06:01 -07:00
.gitignore Update on the examples to respect the new syntax 2018-11-19 15:50:29 -07:00
.gitmodules Update .gitmodules 2018-12-10 12:07:05 -07:00
LICENSE Create LICENSE 2018-06-26 21:52:08 -07:00
Makefile Update go.sh and Makefile 2018-12-11 15:31:32 -07:00
README.md Update README.md 2018-12-05 16:27:37 -07:00
README_Benchmarks.md Correction of the global make, the fpga_flow and the doc 2018-11-20 14:47:15 -07:00

README.md

Getting Started with FPGA-SPICE

Introduction

FPGA-SPICE is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of heterogeneous architectures.

Compilation

The different ways of compiling can be found in the ./compilation folder.

We currently implemented it for:

  1. Ubuntu 18.04
  2. Red Hat 7.5
  3. MacOS High Sierra 10.13.4

Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.

Examples

You can find in the folder ./examples. This will help you get in touch with the software and test different configurations to see how FPGA-SPICE reacts to them.

./example_x.sh allows to launch the script linked to example_x.xml and .blif.

In all the examples, the CLBs are composed of LUTs, FFs and MUXs as a base.

Example 1 shows a very basic design with only 4 inputs on the LUTs, a FF and a MUX in the CLB (only 1). It implements an inverter and allows the user to see the very core of the .xml file.

Example 2 increases the complexity by having 3x3 CLBs and 4 slices per CLB. The slices provide a feedback to the input structure and input MUXs are added.