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Update go.sh and Makefile

This commit is contained in:
AurelienUoU 2018-12-11 15:31:32 -07:00
parent c2c4e78639
commit fb0992bd85
2 changed files with 10 additions and 5 deletions
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2
Makefile
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@ -2,7 +2,7 @@
# Makefile to build CAD tools in OpenFPGA inspired by Verilog-to-Routing (VTR) Framework #
##########################################################################################
SUBDIRS = ace2 vpr7_x2p yosys
SUBDIRS = abc_with_bb_support ace2 vpr7_x2p yosys
all: notifications subdirs

13
vpr7_x2p/vpr/go.sh
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@ -1,9 +1,14 @@
#!/bin/sh
# Example of how to run vpr
# Example of how to run vprset circuit_name = pip_add
set arch_file = ${PWD}/ARCH/k6_N10_scan_chain_tsmc40nm_TT.xml
set circuit_blif = ${PWD}/Circuits/${circuit_name}.blif
set circuit_act = ${PWD}/Circuits/${circuit_name}.act
set circuit_verilog = ${PWD}/Circuits/${circuit_name}_yosys.v
set spice_output = ${PWD}/spice_demo
set verilog_output = ${PWD}/verilog_demo
set modelsim_ini = /uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini
# Pack, place, and route a heterogeneous FPGA
# Packing uses the AAPack algorithm
./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_go --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_go --fpga_verilog_print_top_testbench
./vpr ${arch_file} ${circuit_blif} --full_stats --nodisp --activity_file ${circuit_act} --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ${spice_output} --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ${verilog_output} --fpga_verilog_print_top_testbench --fpga_verilog_print_top_auto_testbench ${circuit_verilog} --fpga_verilog_print_modelsim_autodeck --fpga_verilog_modelsim_ini_path ${modelsim_ini} --fpga_verilog_include_timing --fpga_verilog_init_sim