Add pip_add benchmark
This commit is contained in:
AurelienUoU
parent
f5ea3ff233
commit
c2c4e78639
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@ -0,0 +1,146 @@
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rst 0.001 0.2
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clk 0.506200 0.198800
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a_0 0.507000 0.197200
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a_1 0.502800 0.201000
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a_2 0.498400 0.196600
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a_3 0.510600 0.196600
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a_4 0.514000 0.208000
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a_5 0.517000 0.198400
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a_6 0.491200 0.201400
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a_7 0.516000 0.196400
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b_0 0.502800 0.209400
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b_1 0.490800 0.193600
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b_2 0.508000 0.194200
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b_3 0.464000 0.200600
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b_4 0.492200 0.204200
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b_5 0.505200 0.188600
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b_6 0.496400 0.193400
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b_7 0.513600 0.193000
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cin 0.499400 0.208200
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reg0_a[0] 0.238400 0.176800
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reg0_a[1] 0.246200 0.176000
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reg0_a[2] 0.225800 0.172000
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reg0_a[3] 0.233600 0.175200
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reg0_a[4] 0.241200 0.174400
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reg0_a[5] 0.241400 0.170000
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reg0_a[6] 0.236200 0.171200
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reg0_a[7] 0.244800 0.175200
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reg1_a[0] 0.185400 0.133600
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reg1_a[1] 0.194400 0.138400
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reg1_a[2] 0.177200 0.139600
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reg1_a[3] 0.183600 0.137600
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reg1_a[4] 0.191200 0.140800
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reg1_a[5] 0.191800 0.132000
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reg1_a[6] 0.189200 0.137600
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reg1_a[7] 0.192800 0.140800
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reg2_a[0] 0.148600 0.108000
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reg2_a[1] 0.154800 0.113200
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reg2_a[2] 0.138600 0.111600
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reg2_a[3] 0.145400 0.110800
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reg2_a[4] 0.149200 0.113200
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reg2_a[5] 0.153200 0.108800
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reg2_a[6] 0.151600 0.111600
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reg2_a[7] 0.152200 0.116000
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reg0_b[0] 0.236800 0.178800
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reg0_b[1] 0.233800 0.163200
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reg0_b[2] 0.243600 0.167600
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reg0_b[3] 0.215600 0.173200
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reg0_b[4] 0.226400 0.169200
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reg0_b[5] 0.240000 0.174800
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reg0_b[6] 0.224800 0.177600
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reg0_b[7] 0.245000 0.173200
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reg1_b[0] 0.188000 0.140800
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reg1_b[1] 0.185800 0.130800
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reg1_b[2] 0.193800 0.135200
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reg1_b[3] 0.165600 0.134000
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reg1_b[4] 0.180600 0.134400
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reg1_b[5] 0.188400 0.139600
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reg1_b[6] 0.174200 0.134400
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reg1_b[7] 0.193400 0.136000
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reg2_b[0] 0.149200 0.115200
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reg2_b[1] 0.145600 0.103200
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reg2_b[2] 0.151600 0.107200
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reg2_b[3] 0.128000 0.102800
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reg2_b[4] 0.142200 0.108400
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reg2_b[5] 0.147400 0.110400
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reg2_b[6] 0.138400 0.106800
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reg2_b[7] 0.152600 0.105600
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reg0_cin 0.224800 0.178400
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reg1_cin 0.174400 0.140000
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reg2_cin 0.137400 0.109200
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cout 0.119200 0.105600
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sumout_0 0.111400 0.121200
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sumout_1 0.115800 0.124000
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sumout_2 0.115600 0.126000
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sumout_3 0.115200 0.128000
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sumout_4 0.115800 0.128000
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sumout_5 0.107800 0.119200
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sumout_6 0.117000 0.129200
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sumout_7 0.115200 0.132400
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n340 0.117000 0.060696
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n212_1 0.849800 0.107643
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n213 0.062800 0.025828
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n214 0.850000 0.007413
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n215 0.138200 0.024548
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n216 0.076600 0.000554
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n344 0.115200 0.059006
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n218 0.852400 0.025645
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n57 0.238400 0.039829
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n62 0.246200 0.040694
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n67 0.225800 0.040876
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n72 0.233600 0.039321
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n77 0.241200 0.039861
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n82 0.241400 0.038668
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n87 0.236200 0.042234
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n92 0.244800 0.038625
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n97 0.185400 0.078023
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n102 0.194400 0.076567
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n107 0.177200 0.079580
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n112 0.183600 0.078646
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n117 0.191200 0.077219
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n122 0.191800 0.076600
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n127 0.189200 0.077659
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n132 0.192800 0.076702
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n137 0.148600 0.081354
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n142 0.154800 0.080450
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n147 0.138600 0.083670
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n152 0.145400 0.082242
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n157 0.149200 0.081352
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n162 0.153200 0.080003
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n167 0.151600 0.081252
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n172 0.152200 0.081070
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n177 0.236800 0.041425
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n182 0.233800 0.041591
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n187 0.243600 0.039443
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n192 0.215600 0.045786
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n197 0.226400 0.042352
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n202 0.240000 0.039313
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n207 0.224800 0.040852
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n212 0.245000 0.038637
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n217 0.188000 0.078569
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n222 0.185800 0.077003
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n227 0.193800 0.075904
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n232 0.165600 0.081545
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n237 0.180600 0.079096
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n242 0.188400 0.077479
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n247 0.174200 0.080515
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n252 0.193400 0.076404
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n257 0.149200 0.081918
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n262 0.145600 0.080884
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n267 0.151600 0.080104
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n272 0.128000 0.084941
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n277 0.142200 0.082317
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n282 0.147400 0.081677
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n287 0.138400 0.083456
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n292 0.152600 0.080287
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n297 0.224800 0.041763
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n302 0.174400 0.080624
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n307 0.137400 0.084229
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n312 0.119200 0.071604
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n316 0.111400 0.060180
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n320 0.115800 0.033704
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n324 0.115600 0.059988
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n328 0.115200 0.062886
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n275 0.853600 0.140779
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n336 0.107800 0.062509
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n332 0.115800 0.006673
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@ -0,0 +1,264 @@
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# Benchmark "pip_add" written by ABC on Fri Dec 7 14:18:10 2018
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.model pip_add
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.inputs rst clk a_0 a_1 a_2 a_3 a_4 a_5 a_6 a_7 b_0 b_1 b_2 b_3 b_4 b_5 b_6 \
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b_7 cin
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.outputs sumout_0 sumout_1 sumout_2 sumout_3 sumout_4 sumout_5 sumout_6 \
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sumout_7 cout
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.latch n57 reg0_a[0] re clk 0
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.latch n62 reg0_a[1] re clk 0
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.latch n67 reg0_a[2] re clk 0
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.latch n72 reg0_a[3] re clk 0
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.latch n77 reg0_a[4] re clk 0
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.latch n82 reg0_a[5] re clk 0
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.latch n87 reg0_a[6] re clk 0
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.latch n92 reg0_a[7] re clk 0
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.latch n97 reg1_a[0] re clk 0
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.latch n102 reg1_a[1] re clk 0
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.latch n107 reg1_a[2] re clk 0
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.latch n112 reg1_a[3] re clk 0
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.latch n117 reg1_a[4] re clk 0
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.latch n122 reg1_a[5] re clk 0
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.latch n127 reg1_a[6] re clk 0
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.latch n132 reg1_a[7] re clk 0
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.latch n137 reg2_a[0] re clk 0
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.latch n142 reg2_a[1] re clk 0
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.latch n147 reg2_a[2] re clk 0
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.latch n152 reg2_a[3] re clk 0
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.latch n157 reg2_a[4] re clk 0
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.latch n162 reg2_a[5] re clk 0
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.latch n167 reg2_a[6] re clk 0
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.latch n172 reg2_a[7] re clk 0
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.latch n177 reg0_b[0] re clk 0
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.latch n182 reg0_b[1] re clk 0
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.latch n187 reg0_b[2] re clk 0
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.latch n192 reg0_b[3] re clk 0
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.latch n197 reg0_b[4] re clk 0
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.latch n202 reg0_b[5] re clk 0
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.latch n207 reg0_b[6] re clk 0
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.latch n212 reg0_b[7] re clk 0
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.latch n217 reg1_b[0] re clk 0
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.latch n222 reg1_b[1] re clk 0
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.latch n227 reg1_b[2] re clk 0
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.latch n232 reg1_b[3] re clk 0
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.latch n237 reg1_b[4] re clk 0
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.latch n242 reg1_b[5] re clk 0
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.latch n247 reg1_b[6] re clk 0
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.latch n252 reg1_b[7] re clk 0
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.latch n257 reg2_b[0] re clk 0
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.latch n262 reg2_b[1] re clk 0
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.latch n267 reg2_b[2] re clk 0
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.latch n272 reg2_b[3] re clk 0
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.latch n277 reg2_b[4] re clk 0
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.latch n282 reg2_b[5] re clk 0
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.latch n287 reg2_b[6] re clk 0
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.latch n292 reg2_b[7] re clk 0
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.latch n297 reg0_cin re clk 0
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.latch n302 reg1_cin re clk 0
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.latch n307 reg2_cin re clk 0
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.latch n312 cout re clk 0
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.latch n316 sumout_0 re clk 0
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.latch n320 sumout_1 re clk 0
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.latch n324 sumout_2 re clk 0
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.latch n328 sumout_3 re clk 0
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.latch n332 sumout_4 re clk 0
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.latch n336 sumout_5 re clk 0
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.latch n340 sumout_6 re clk 0
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.latch n344 sumout_7 re clk 0
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.names reg2_a[6] reg2_b[6] n212_1 rst n340
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0000 1
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0110 1
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1010 1
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1100 1
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.names n216 n213 reg2_a[5] reg2_b[5] n212_1
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000- 1
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00-0 1
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--00 1
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.names n215 reg2_a[2] reg2_b[2] reg2_a[3] reg2_b[3] n214 n213
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1111-- 1
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111-1- 1
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11-1-0 1
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11--10 1
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1-11-0 1
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1-1-10 1
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1--11- 1
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.names reg2_a[1] reg2_cin reg2_a[0] reg2_b[0] reg2_b[1] n214
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000-- 1
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00-0- 1
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0-00- 1
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0---0 1
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-00-0 1
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-0-00 1
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--000 1
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.names reg2_a[4] reg2_b[4] n215
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01 1
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10 1
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.names reg2_a[4] reg2_b[4] n216
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11 1
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.names reg2_a[7] reg2_b[7] n218 rst n344
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0000 1
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0110 1
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1010 1
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1100 1
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.names n213 n216 reg2_a[6] reg2_a[5] reg2_b[5] reg2_b[6] n218
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0000-- 1
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000-0- 1
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00-0-0 1
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00--00 1
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--000- 1
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--0--0 1
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---000 1
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.names a_0 rst n57
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10 1
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.names a_1 rst n62
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10 1
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.names a_2 rst n67
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10 1
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.names a_3 rst n72
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10 1
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.names a_4 rst n77
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10 1
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.names a_5 rst n82
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10 1
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.names a_6 rst n87
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10 1
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.names a_7 rst n92
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10 1
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.names reg0_a[0] rst n97
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10 1
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.names reg0_a[1] rst n102
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10 1
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.names reg0_a[2] rst n107
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10 1
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.names reg0_a[3] rst n112
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10 1
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.names reg0_a[4] rst n117
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10 1
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.names reg0_a[5] rst n122
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10 1
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.names reg0_a[6] rst n127
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10 1
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.names reg0_a[7] rst n132
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10 1
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.names reg1_a[0] rst n137
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10 1
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.names reg1_a[1] rst n142
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10 1
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.names reg1_a[2] rst n147
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10 1
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.names reg1_a[3] rst n152
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10 1
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.names reg1_a[4] rst n157
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10 1
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.names reg1_a[5] rst n162
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10 1
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.names reg1_a[6] rst n167
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10 1
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.names reg1_a[7] rst n172
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10 1
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.names b_0 rst n177
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10 1
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.names b_1 rst n182
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10 1
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.names b_2 rst n187
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10 1
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.names b_3 rst n192
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10 1
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.names b_4 rst n197
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10 1
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.names b_5 rst n202
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10 1
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.names b_6 rst n207
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10 1
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.names b_7 rst n212
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10 1
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.names reg0_b[0] rst n217
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10 1
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.names reg0_b[1] rst n222
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10 1
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.names reg0_b[2] rst n227
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10 1
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.names reg0_b[3] rst n232
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10 1
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.names reg0_b[4] rst n237
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10 1
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.names reg0_b[5] rst n242
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10 1
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.names reg0_b[6] rst n247
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10 1
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.names reg0_b[7] rst n252
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10 1
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.names reg1_b[0] rst n257
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10 1
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.names reg1_b[1] rst n262
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10 1
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.names reg1_b[2] rst n267
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10 1
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.names reg1_b[3] rst n272
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10 1
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.names reg1_b[4] rst n277
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10 1
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.names reg1_b[5] rst n282
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10 1
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.names reg1_b[6] rst n287
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10 1
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.names reg1_b[7] rst n292
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10 1
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.names cin rst n297
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10 1
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.names reg0_cin rst n302
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10 1
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.names reg1_cin rst n307
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10 1
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.names rst reg2_a[7] reg2_b[7] n218 n312
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011- 1
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01-0 1
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0-10 1
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.names reg2_cin reg2_a[0] reg2_b[0] rst n316
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0010 1
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0100 1
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1000 1
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1110 1
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.names reg2_a[1] reg2_b[1] rst reg2_cin reg2_a[0] reg2_b[0] n320
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00011- 1
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0001-1 1
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000-11 1
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01000- 1
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0100-0 1
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010-00 1
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10000- 1
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1000-0 1
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100-00 1
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11011- 1
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1101-1 1
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110-11 1
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.names reg2_a[2] reg2_b[2] n214 rst n324
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0000 1
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0110 1
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1010 1
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1100 1
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.names reg2_a[3] reg2_b[3] n275 rst n328
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0000 1
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0110 1
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1010 1
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1100 1
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.names reg2_a[2] reg2_b[2] n214 n275
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00- 1
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0-1 1
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-01 1
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.names reg2_a[5] reg2_b[5] rst n216 n213 n336
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0001- 1
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000-1 1
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01000 1
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10000 1
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1101- 1
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110-1 1
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.names n215 rst reg2_a[3] reg2_b[3] n275 n332
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0011- 1
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001-0 1
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00-10 1
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1000- 1
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100-1 1
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10-01 1
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.end
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