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removed the now useless tutorial part

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Baudouin Chauviere 2018-12-10 13:57:01 -07:00
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54
fpga_flow/benchmarks/fpga_spice_bench.txt
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@ -1,32 +1,32 @@
## Circuit Names, fixed routing channel width,
#### One # worked, ## did not
s298.blif, 60
elliptic.blif, 60
simple_spi.blif, 60
i2c.blif, 60
pci_conf_cyc_addr_dec.blif, 60
sasc.blif, 60
usb_phy.blif, 60
steppermotordrive.blif, 60
stereovision3.blif, 60
dalu.blif, 60
C1355.blif, 60
alu4.blif, 60
priority.blif, 60
#elliptic.blif, 60
#simple_spi.blif, 60
#i2c.blif, 60
#pci_conf_cyc_addr_dec.blif, 60
#sasc.blif, 60
#usb_phy.blif, 60
#steppermotordrive.blif, 60
#stereovision3.blif, 60
#dalu.blif, 60
#C1355.blif, 60
#alu4.blif, 60
#priority.blif, 60
apex7.blif, 60
int2float.blif, 60
planet.blif, 60
alu2.blif, 60
mult32a.blif, 60
tbk.blif, 60
sqrt8ml.blif, 60
ss_pcm.blif, 60
scf.blif, 60
s820.blif, 60
ctrl.blif, 60
cavlc.blif, 60
router.blif, 60
#int2float.blif, 60
#planet.blif, 60
#alu2.blif, 60
#mult32a.blif, 60
#tbk.blif, 60
#sqrt8ml.blif, 60
#ss_pcm.blif, 60
#scf.blif, 60
#s820.blif, 60
#ctrl.blif, 60
#cavlc.blif, 60
#router.blif, 60
traffic.blif, 60
e64.blif, 60
s1488.blif, 60
fsm8_8_13.blif, 60
#e64.blif, 60
#s1488.blif, 60
#fsm8_8_13.blif, 60

1
tutorial/.gitignore vendored
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112
tutorial/01_architecture.ipynb
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{
"cells": [
{
"cell_type": "markdown",
"metadata": {},
"source": [
"# The Architecture format\n",
"A complete FPGA is specified in an architecture XML file. The FPGA specification is wrapped in an `<architecture>` tag; `v8_example_arch.xml` defines a simple FPGA.\n",
"\n",
"### [`<models>`](http://docs.verilogtorouting.org/en/latest/arch/reference/#recognized-blif-models-models)\n",
"The first element in the architecture is `<models>`, which describes `blif` circuit models that the FPGA uses. The models `.names`, `.latch`, `.input`, and `.output` are automatically recognized and don't need to be specified in this section. The `v8_example_arch.xml` architecture is simple enough to not need any additional models specified here.\n",
"\n",
"\n",
"### [`<layout>`](http://docs.verilogtorouting.org/en/latest/arch/reference/#fpga-grid-layout)\n",
"The `<layout>` element specifies how the FPGA grid will be arranged. In `v8_example_arch.xml`: `<layout auto=\"1.000000\"/>` specifies an automatic grid with an aspect ratio of 1.0. A specific width and heigh could be specified instead of the automatic layout. The rest of the `<layout>` section specifies that the perimeter will have `io` blocks, the corners will be `EMPTY` and the rest of the FPGA will be filled with `clb` blocks. Higher number priorities take precedence over lower numbers, so the `EMPTY` blocks in the corners will take precedence over the `io` blocks around the perimeter. The lowest priority `clb` blocks fill the remaining places in the grid.\n",
"\n",
"`io` and `clb` blocks are defined in the `<complexblocklist>` section.\n",
"\n",
"### [`<device>`](http://docs.verilogtorouting.org/en/latest/arch/reference/#fpga-device-information)\n",
"The `<device>` element characterizes the transistors and connections of the FPGA. `<sizing>` specifies the resistance of the minimum-width nmos and pmos transistors. `<area grid_logic_tile_area>` is used as an estimate of the size of one grid tile.\n",
"\n",
"The `<chan_width_distr>` section sets the relative widths of the routing channels in various parts of the FPGA. Here, all channels are set to be distributed uniformly. \n",
"\n",
"`<switch_block type=\"wilton\" fs=\"3\"/>` indicates a [Wilton switch block pattern](http://docs.verilogtorouting.org/en/latest/references/#wilton-phd) with a switchblock fraction (fs) of 3.\n",
"\n",
"`<connection_block input_switch_name=\"ipin_cblock\"/>` specifies the name of the connection block. The actual connection block is defined in the `<switchlist>` section.\n",
"\n",
"### [`<switchlist>`](http://docs.verilogtorouting.org/en/latest/arch/reference/#switches)\n",
"The `<switchlist>` section specifies the switches used to connect wires and pins together. The switch names defined here are used elsewhere in the `<connection_block>` and `<segmentlist>` sections in this example architecture.\n",
"\n",
"\n",
"### [`<segmentlist>`](http://docs.verilogtorouting.org/en/latest/arch/reference/#wire-segments)\n",
"`<segmentlist>` defines the wire segments in the channels between logic blocks. The `<segment>` element specifies one kind of wire to be used. `freq` is used to indicate the the usage ratio of this kind of wire with respect to all the wires. `length` is how many logic blocks the wire segment will span. `Rmetal` and `Cmetal` indicate the resistance and capacitance of the segment.\n",
"\n",
"`<mux name>` is the name of the switch used to drive the segment and is defined in the `<switchlist>` section.\n",
"\n",
"`<sb type>` is the pattern of switch blocks on the segment, and because switch blocks are between logic blocks there are one more entries in the list than the length of the segment. So for the segment with a length of 4, there are 5 entries in the pattern. `<cb type>` is the pattern of connection blocks on the segment. Connection blocks are next to logic blocks so the number of entries in the pattern equals the length of the segment.\n"
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
"## [`<complexblocklist>`](http://docs.verilogtorouting.org/en/latest/arch/reference/#complex-blocks)\n",
"In this example architecture, two complex blocks are defined: An input/output block, and a configurable logic block (CLB).\n",
"\n",
"### Input and Output block\n",
"`<pb_type name=\"io\" capacity=\"3\">` begins the definition of the I/O block. `pb_type` is the tag that indicates a primitive block is being defined, and multiple `pb_type`'s can be nested. `capacity` is only allowed in an I/O block, and indicates how many inputs or outpus the block will have.\n",
"\n",
"`<input name=\"outpad\" num_pins=\"1\"/>` defines what might be considered an *output* from the FPGA, which is why it is given the name `outpad`: signals coming out of the FPGA are routed to the *input* of this block and then sent out of the *outpad* to the outside world. Similarly, a signal from the outside world comes in the *inpad* and then sent out the *output* of the block to then be routed through the FPGA. Thus the *input* to the FPGA is defined by `<output name=\"inpad\" num_pins=\"1\"/>`. \n",
"\n",
"An I/O block can only be an input or an output, and the mode defines the behavior. `<mode name=\"inpad\">` begins the input behavior. `<pb_type name=\"inpad\" blif_model=\".input\" num_pb=\"1\">` gives the physical block a name `inpad`, associates it with the `.input` of the blif model, and indicates there is 1 of these `inpad`s in the parent pb_type of `io`.\n",
"\n",
"`<output name=\"inpad\" num_pins=\"1\"/>` says that there is one output of the block named `inpad`. The signal comes in the *inpad* and is sent *out* of this block to the rest of the FPGA.\n",
"\n",
"The `<interconnect>` section makes connections between the block's pins. `<direct name=\"inpad\" input=\"inpad.inpad\" output=\"io.inpad\">` creates a direct connection named `inpad`, connects its input to `inpad.inpad` which is the output of the `inpad` block, and connects its ouput to `io.inpad` which is the ouput of the `io` block.\n",
"\n",
"The `<delay_constant>` tag specifies the delay between the in_port and the out_port of the primitive block.\n",
"\n",
"`<mode name=\"outpad\">` defines the other mode of this block, and is analagous to the `inpad` definition.\n",
"\n",
"\n",
"\n",
"## Logic Blocks\n",
"\n",
"`<pb_type name=\"clb\">` is where the general purpuse *complex logic block* or *clb* definition begins. `<pb_type>` is the tag to define a primitive block on the FPGA. Next, the inputs and outputs to the block are defined; here there are 10 inputs, 3 outputs, and 1 clock input. The inputs and outputs have `equivalent=true` attributes, which means that they are logically equivalent and so order doesn't matter when routing.\n",
"\n",
"`<pb_type name=\"ble4\" num_pb=\"3\">` defines the *basic logic element* or *BLE* that makes up the clb. The `<pb_type name=\"ble4\" num_pb=\"3\">` attribute indicates that 3 of these BLEs called `ble4` are contained in the surrounding `clb`. The next lines define 4 inputs, one output, and one clock line.\n",
"\n",
"`<pb_type name=\"lut4\" blif_model=\".names\" num_pb=\"1\" class=\"lut\">` defines the lookup-table named `lut4`; `.names` is the BLIF keyword for lookup-table. The next two lines show 4 inputs and 1 output to the LUT. The `<delay_matrix>` attribute specifies the propogation delay through the LUT's inputs to output.\n",
"\n",
"`<pb_type name=\"ff\" blif_model=\".latch\" num_pb=\"1\" class=\"flipflop\">` defines the flip-flop in the BLE: 1 flip-flop named `ff`; `.latch` is the BLIF keyword for flip-flop. The next lines specify the I/Os and timing parameters.\n",
"\n",
"The `<interconnect>` section wires the blocks together. The input of `ble4` is connected to the input of `lut4`, the output of `lut4` is connected to the D-input of `ff`. The clk inputs are wired together. Finally, a mux is defined to set the output of `ble4` to be either the direct output of `lut4` or the latched output of `ff`.\n",
"\n",
"That completes the *ble* definition, now the *clb* needs to be completed with its `<interconnect>` section. The `<complete>` tag indicates a fully connected crossbar, so any input of the clb can be routed to any of the bles. Also, `input=\"clb.I ble4[2:0].out\"` means that there are two inputs to the crossbar: the input to the clb as well as the output of the bles, giving a feedback configuration. The output of the crossbar is connected to the inputs of the bles. Finally, the output of the bles are connected to the output of the clb.\n",
"\n",
"At the end of the top-level `pb_type` definition, the configuration of pins is specified. `<fc in_type=\"frac\" in_val=\"0.15\" out_type=\"frac\" out_val=\"0.25\"/>` shows the percentage of tracks in the channel drive the block's pins. \n",
"\n",
"`<pinlocations pattern=\"spread\"/>` says that the pins should be spread evenly around the edges of the block."
]
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {},
"outputs": [],
"source": []
}
],
"metadata": {
"kernelspec": {
"display_name": "Python 3",
"language": "python",
"name": "python3"
},
"language_info": {
"codemirror_mode": {
"name": "ipython",
"version": 3
},
"file_extension": ".py",
"mimetype": "text/x-python",
"name": "python",
"nbconvert_exporter": "python",
"pygments_lexer": "ipython3",
"version": "3.6.5"
}
},
"nbformat": 4,
"nbformat_minor": 2
}

80
tutorial/02_multimode.ipynb
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{
"cells": [
{
"cell_type": "markdown",
"metadata": {},
"source": [
"# Multimode CLB\n",
"In the I/O section of the architecture, the `<mode>` tag was used to define different modes for the block. One mode was for input, the other mode for output. Modes are also used in CLBs. Open the file `OpenFPGA/tutorial/02_multimode_arch.xml`. It defines two modes for its CLB: either a 6-LUT, or two 5-LUTs with shared inputs.\n",
"\n",
"Find the line `<pb_type name=\"clb\" area=\"53894\">` which begins the definition of the CLB. The next few lines define the inputs and outputs: 40 input pins, 20 output pins, and a clock pin. The inputs are marked with `equivalent=\"full\"` which indicates that the inputs have logical equivalence so their locations may be freely swapped. The outputs are `equivalent=\"none\"` so they may not be swapped.\n",
"\n",
"The next primitive block is `<pb_type name=\"fle\" num_pb=\"10\">` which is a fracturable logic element that contains the two different modes of this CLB. There are 10 instances of this `fle` in the CLB. Each `fle` has 6 inputs, 2 outputs, and one clock pin.\n",
"\n",
"### First Mode\n",
"`<mode name=\"n2_lut5\">` begins the definition of the first mode. Moving down the architecture file, we see that in this mode, the `fle` contains one `lut5inter` block which contains two `ble5` blocks. The `ble5` blocks have 5 inputs and 1 output. The next group of lines define the LUT and FF in `ble5`.\n",
"\n",
"Moving down to the second `<interconnect>` block:\n",
"```\n",
"<interconnect>\n",
" <direct name=\"direct1\" input=\"lut5inter.in\" output=\"ble5[0:0].in\"/>\n",
" <direct name=\"direct2\" input=\"lut5inter.in\" output=\"ble5[1:1].in\"/>\n",
" <direct name=\"direct3\" input=\"ble5[1:0].out\" output=\"lut5inter.out\"/> \n",
" <complete name=\"complete1\" input=\"lut5inter.clk\" output=\"ble5[1:0].clk\"/> \n",
"</interconnect>\n",
"```\n",
"we see that the input of `lut5inter` is connected to the inputs of both the first and second `ble5` blocks. Then the two outputs of the two `ble5` blocks go to the two outputs of `lut5inter`. Finally, there is a fully connected crossbar that connects the `lut5inter` clock input to the two `ble5` clock inputs.\n",
"\n",
"Finishing out this mode, there is the last interconnect section. Note the line: `<direct name=\"direct1\" input=\"fle.in[4:0]\" output=\"lut5inter.in\"/>`. It shows that out of the 6 `fle` input lines, only the first 5 lines are connected to `lut5inter`. The remaining line is unused.\n",
"\n",
"### Second Mode\n",
"`<mode name=\"n1_lut6\">` begins the definition of the second mode. In this mode, the `fle` block contains one block named `ble6` with 6 inputs and one output. Moving down the architecture, we see that it contains one LUT named `lut6` with 6 inputs and one output, and one flip-flop named `ff`. \n",
"\n",
"Moving down to this mode's `<interconnect>` block:\n",
"```\n",
"<interconnect>\n",
" <direct name=\"direct1\" input=\"fle.in\" output=\"ble6.in\"/>\n",
" <direct name=\"direct2\" input=\"ble6.out\" output=\"fle.out[0:0]\"/>\n",
" <direct name=\"direct3\" input=\"fle.clk\" output=\"ble6.clk\"/>\n",
"</interconnect>\n",
"```\n",
"we see that the input of `fle` is connected to the input of `ble6`, the output of `ble6` is connected to one output of `fle`, and the clock pins are wired together. The remaining output of `fle` is unused in this mode.\n",
"\n",
"The final `<interconnect>` section takes care of the wiring inside the top-level `clb` block. There is a fully connected crossbar that takes as its input the inputs to `clb` as well as the outputs from `flb` in a feedback loop. The crossbar's outputs go to `flb`'s inputs. Then a crossbar connects the clock pins. Now recall that the first mode of `clb` uses both of `flb`'s outputs, but the second mode uses only one outputs. The lines:\n",
"```\n",
" <direct name=\"clbouts1\" input=\"fle[9:0].out[0:0]\" output=\"clb.O[9:0]\"/>\n",
" <direct name=\"clbouts2\" input=\"fle[9:0].out[1:1]\" output=\"clb.O[19:10]\"/>\n",
"```\n",
"ensure that if a logic block is completely filled by 6-LUTs, then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides.\n"
]
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {},
"outputs": [],
"source": []
}
],
"metadata": {
"kernelspec": {
"display_name": "Python 3",
"language": "python",
"name": "python3"
},
"language_info": {
"codemirror_mode": {
"name": "ipython",
"version": 3
},
"file_extension": ".py",
"mimetype": "text/x-python",
"name": "python",
"nbconvert_exporter": "python",
"pygments_lexer": "ipython3",
"version": "3.6.5"
}
},
"nbformat": 4,
"nbformat_minor": 2
}

290
tutorial/02_multimode_arch.xml
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<!--
Architecture file translated from ifar repository N04K04L01.FC15FO25.AREA1DELAY1.CMOS90NM.BPTM
Simple architecture file for vpr version 8 consisting of clusters of BLEs, each BLE contains a 4-LUT+FF pair. Delay models from 90nm PTM.
-->
<architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports.
Note: This simple architecture needs no models defined here. Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) that describe them.
-->
<models>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout>
<auto_layout aspect_ratio="1.000000">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</auto_layout>
</layout>
<device>
<sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000"/>
<area grid_logic_tile_area="7238.080078"/>
<chan_width_distr>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/>
</device>
<switchlist>
<switch type="mux" name="switchblock" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="7.958000e-11" mux_trans_size="2.074780" buf_size="19.261999"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="1516.380005" Cout="0." Cin="0.000000e+00" Tdel="7.362000e-11" mux_trans_size="1.240240" buf_size="auto"/>
</switchlist>
<segmentlist>
<segment freq="1.000000" length="4" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
<mux name="switchblock"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<complexblocklist>
<!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<pb_type name="io" capacity="3">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<clock name="clock" num_pins="1"/>
<!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="9.492000e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="2.675000e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad io.clock</loc>
<loc side="top">io.outpad io.inpad io.clock</loc>
<loc side="right">io.outpad io.inpad io.clock</loc>
<loc side="bottom">io.outpad io.inpad io.clock</loc>
</pinlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<pb_type name="clb" area="53894">
<input name="I" num_pins="40" equivalent="full"/>
<output name="O" num_pins="20" equivalent="none"/>
<clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered
-->
<pb_type name="fle" num_pb="10">
<input name="in" num_pins="6"/>
<output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/>
<!-- Dual 5-LUT mode definition begin -->
<mode name="n2_lut5">
<pb_type name="lut5inter" num_pb="1">
<input name="in" num_pins="5"/>
<output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/>
<pb_type name="ble5" num_pb="2">
<input name="in" num_pins="5"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define the LUT -->
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="5" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
235e-12
235e-12
235e-12
235e-12
235e-12
</delay_matrix>
</pb_type>
<!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
</direct>
<direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]" />
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]" />
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
<direct name="direct2" input="lut5inter.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
</interconnect>
</mode>
<!-- Dual 5-LUT mode definition end -->
<!-- 6-LUT mode definition begin -->
<mode name="n1_lut6">
<!-- Define 6-LUT mode -->
<pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
261e-12
261e-12
261e-12
261e-12
261e-12
261e-12
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
<direct name="direct2" input="lut6.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
</interconnect>
</mode>
<!-- 6-LUT mode definition end -->
</pb_type>
<interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
delay within the crossbar is 95 ps.
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in" />
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification).
-->
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
</complexblocklist>
</architecture>

50
tutorial/03_blackbox.ipynb
View File

@ -1,50 +0,0 @@
{
"cells": [
{
"cell_type": "markdown",
"metadata": {},
"source": [
"# Black boxes\n",
"The <models> section is how a primitive block can implement a black-box BLIF primitive. Open the file 03_blackbox.xml in a text editor. in the `<models>` section, find the line: `<model name=\"multiply\"> `. It declares a black-box primitive with combinational logic that connects two inputs to one output.\n",
" \n",
"Now in the `<complexblocklist>` section, find the line `<pb_type name=\"mult_16x16_slice\" height=\"4\" width=\"2\">`. This begins the definition of the black box primitive. It is given a name and dimensions in block units. The inputs and outputs are defined as two 16 bit inputs and a 32 bit output.\n",
"\n",
"The line:\n",
" ```\n",
" <pb_type name=\"mult_16x16\" blif_model=\".subckt multiply\" num_pb=\"1\">\n",
" ```\n",
" defines a sub-block that implements the `multiply` logic. This block also has two 16 bit inputs and a 32 bit output. Then the delays between the two inputs to the output are defined.\n",
" \n",
" "
]
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {},
"outputs": [],
"source": []
}
],
"metadata": {
"kernelspec": {
"display_name": "Python 3",
"language": "python",
"name": "python3"
},
"language_info": {
"codemirror_mode": {
"name": "ipython",
"version": 3
},
"file_extension": ".py",
"mimetype": "text/x-python",
"name": "python",
"nbconvert_exporter": "python",
"pygments_lexer": "ipython3",
"version": "3.6.5"
}
},
"nbformat": 4,
"nbformat_minor": 2
}

200
tutorial/03_blackbox.xml
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@ -1,200 +0,0 @@
<!--
Simple architecture file illustrating the use of <models>
-->
<architecture>
<models>
<model name="multiply">
<input_ports>
<port name="a" combinational_sink_ports="out"/>
<port name="b" combinational_sink_ports="out"/>
</input_ports>
<output_ports>
<port name="out"/>
</output_ports>
</model>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout>
<auto_layout aspect_ratio="1.000000">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</auto_layout>
</layout>
<device>
<sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000"/>
<area grid_logic_tile_area="7238.080078"/>
<chan_width_distr>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/>
</device>
<switchlist>
<switch type="mux" name="switchblock" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="7.958000e-11" mux_trans_size="2.074780" buf_size="19.261999"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="1516.380005" Cout="0." Cin="0.000000e+00" Tdel="7.362000e-11" mux_trans_size="1.240240" buf_size="auto"/>
</switchlist>
<segmentlist>
<segment freq="1.000000" length="4" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
<mux name="switchblock"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<complexblocklist>
<!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<pb_type name="io" capacity="3">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<clock name="clock" num_pins="1"/>
<!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="9.492000e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="2.675000e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad io.clock</loc>
<loc side="top">io.outpad io.inpad io.clock</loc>
<loc side="right">io.outpad io.inpad io.clock</loc>
<loc side="bottom">io.outpad io.inpad io.clock</loc>
</pinlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<pb_type name="clb">
<input name="I" num_pins="10"/>
<output name="O" num_pins="3"/>
<clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. -->
<!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="3">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
2.253000e-10
2.253000e-10
2.253000e-10
2.253000e-10
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.160000e-10" port="ff.D" clock="clk"/>
<T_clock_to_Q max="1.426000e-10" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4.in"/>
<direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut4.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
</mux>
</interconnect>
</pb_type>
<!-- 4-LUT mode definition end -->
<interconnect>
<!-- Keyword 'complete' indicates a fully connected crossbar to get logical equivalence at inputs of CLB
here, the crossbar takes input from the clb and the feedback output from the ble.
crossbar output goes to the ble input. -->
<complete name="crossbar" input="clb.I ble4[2:0].out" output="ble4[2:0].in">
<delay_constant max="5.735000e-11" in_port="clb.I" out_port="ble4[2:0].in" />
<delay_constant max="5.428000e-11" in_port="ble4[2:0].out" out_port="ble4[2:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="ble4[2:0].clk">
</complete>
<direct name="clbouts1" input="ble4[2:0].out" output="clb.O"/>
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 25% of the tracks in a channel -->
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.25"/>
<pinlocations pattern="spread"/>
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
<!-- Define black-box begin -->
<pb_type name="mult_16x16_slice" width="2" height="4">
<input name="A" num_pins="16"/>
<input name="B" num_pins="16"/>
<output name="OUT" num_pins="32"/>
<pb_type name="mult_16x16" blif_model=".subckt multiply" num_pb="1">
<input name="a" num_pins="16"/>
<input name="b" num_pins="16"/>
<output name="out" num_pins="32"/>
<delay_constant max="1.667e-9" in_port="mult_16x16.a" out_port="mult_16x16.out"/>
<delay_constant max="1.667e-9" in_port="mult_16x16.b" out_port="mult_16x16.out"/>
</pb_type>
<interconnect>
<direct name="a2a" input="mult_16x16_slice.A" output="mult_16x16.a"/>
<direct name="b2b" input="mult_16x16_slice.B" output="mult_16x16.b"/>
<direct name="out2out" input="mult_16x16.out" output="mult_16x16_slice.OUT"/>
</interconnect>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</pb_type>
<!-- Define black-box ends -->
</complexblocklist>
</architecture>

189
tutorial/example_arch.xml
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<!--
Architecture file translated from ifar repository N04K04L01.FC15FO25.AREA1DELAY1.CMOS90NM.BPTM
Simple architecture file consisting of clusters of 4 BLEs, each BLE contains a 4-LUT+FF pair. Delay models from 90nm PTM.
-->
<architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports.
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch)
that describe them.
-->
<models>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout auto="1.000000"/>
<device>
<sizing R_minW_nmos="4220.930176" R_minW_pmos="11207.599609" ipin_mux_trans_size="0.983352"/>
<timing C_ipin_cblock="0.000000e+00" T_ipin_cblock="8.045000e-11"/>
<area grid_logic_tile_area="2229.320068"/>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<switchlist>
<switch type="mux" name="0" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="6.244000e-11" mux_trans_size="1.835460" buf_size="10.498600"/>
</switchlist>
<segmentlist>
<segment freq="1.000000" length="1" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
<mux name="0"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
</segmentlist>
<complexblocklist>
<!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<pb_type name="io" capacity="3">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<clock name="clock" num_pins="1"/>
<!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="9.492000e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="2.675000e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="1.0" default_out_type="frac" default_out_val="0.25"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad io.clock</loc>
<loc side="top">io.outpad io.inpad io.clock</loc>
<loc side="right">io.outpad io.inpad io.clock</loc>
<loc side="bottom">io.outpad io.inpad io.clock</loc>
</pinlocations>
<!-- Place I/Os on the sides of the FPGA -->
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<pb_type name="clb">
<input name="I" num_pins="10" equivalent="true"/>
<output name="O" num_pins="4" equivalent="true"/>
<clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. -->
<pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin -->
<mode name="n1_lut4">
<!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
2.253000e-10
2.253000e-10
2.253000e-10
2.253000e-10
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.160000e-10" port="ff.D" clock="clk"/>
<T_clock_to_Q max="1.426000e-10" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut4.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect>
</mode>
<!-- 4-LUT mode definition end -->
</pb_type>
<interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="5.735000e-11" in_port="clb.I" out_port="fle[3:0].in" />
<delay_constant max="5.428000e-11" in_port="fle[3:0].out" out_port="fle[3:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete>
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 25% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.25"/>
<pinlocations pattern="spread"/>
<!-- Place this general purpose logic block in any unspecified column -->
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
</complexblocklist>
</architecture>

14
tutorial/example_circuit.blif
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@ -1,14 +0,0 @@
.model top
.inputs pa pb pc
.outputs pd pe pf pg
.names pa pb pe
01 1
10 1
.names pa pb pc pf
001 1
110 1
.names pc pg
0 1
.names pc pd
1 1
.end

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tutorial/v8_example_arch.xml
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<!--
Architecture file translated from ifar repository N04K04L01.FC15FO25.AREA1DELAY1.CMOS90NM.BPTM
Simple architecture file for vpr version 8 consisting of clusters of BLEs, each BLE contains a 4-LUT+FF pair. Delay models from 90nm PTM.
-->
<architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports.
Note: This simple architecture needs no models defined here. Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) that describe them.
-->
<models>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout>
<auto_layout aspect_ratio="1.000000">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</auto_layout>
</layout>
<device>
<sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000"/>
<area grid_logic_tile_area="7238.080078"/>
<chan_width_distr>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/>
</device>
<switchlist>
<switch type="mux" name="switchblock" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="7.958000e-11" mux_trans_size="2.074780" buf_size="19.261999"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="1516.380005" Cout="0." Cin="0.000000e+00" Tdel="7.362000e-11" mux_trans_size="1.240240" buf_size="auto"/>
</switchlist>
<segmentlist>
<segment freq="1.000000" length="4" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
<mux name="switchblock"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<complexblocklist>
<!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<pb_type name="io" capacity="3">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<clock name="clock" num_pins="1"/>
<!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="9.492000e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="2.675000e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad io.clock</loc>
<loc side="top">io.outpad io.inpad io.clock</loc>
<loc side="right">io.outpad io.inpad io.clock</loc>
<loc side="bottom">io.outpad io.inpad io.clock</loc>
</pinlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<pb_type name="clb">
<input name="I" num_pins="10"/>
<output name="O" num_pins="3"/>
<clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. -->
<!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="3">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
2.253000e-10
2.253000e-10
2.253000e-10
2.253000e-10
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.160000e-10" port="ff.D" clock="clk"/>
<T_clock_to_Q max="1.426000e-10" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4.in"/>
<direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut4.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
</mux>
</interconnect>
</pb_type>
<!-- 4-LUT mode definition end -->
<interconnect>
<!-- Keyword 'complete' indicates a fully connected crossbar to get logical equivalence at inputs of CLB
here, the crossbar takes input from the clb and the feedback output from the ble.
crossbar output goes to the ble input. -->
<complete name="crossbar" input="clb.I ble4[2:0].out" output="ble4[2:0].in">
<delay_constant max="5.735000e-11" in_port="clb.I" out_port="ble4[2:0].in" />
<delay_constant max="5.428000e-11" in_port="ble4[2:0].out" out_port="ble4[2:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="ble4[2:0].clk">
</complete>
<direct name="clbouts1" input="ble4[2:0].out" output="clb.O"/>
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 25% of the tracks in a channel -->
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.25"/>
<pinlocations pattern="spread"/>
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
</complexblocklist>
</architecture>