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Stable, unfinished

This commit is contained in:
Baudouin Chauviere 2019-06-26 16:54:41 -06:00
parent 87ddca9f57
commit 0ce9846e47
13 changed files with 77 additions and 14 deletions
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1
vpr7_x2p/vpr/SRC/base/OptionTokens.c
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@ -84,6 +84,7 @@ struct s_TokenPair OptionBaseTokenList[] = {
/* Xifan TANG: Synthsizable Verilog */
{ "fpga_verilog", OT_FPGA_VERILOG_SYN },
{ "fpga_verilog_dir", OT_FPGA_VERILOG_SYN_DIR },
{ "fpga_verilog_explicit_mapping", OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING },
{ "fpga_verilog_print_top_testbench", OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH },
{ "fpga_verilog_print_autocheck_top_testbench", OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH },
{ "fpga_verilog_print_input_blif_testbench", OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH },

1
vpr7_x2p/vpr/SRC/base/OptionTokens.h
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@ -101,6 +101,7 @@ enum e_OptionBaseToken {
/* Xifan TANG: Verilog Generation */
OT_FPGA_VERILOG_SYN, /* Xifan TANG: Synthesizable Verilog Dump */
OT_FPGA_VERILOG_SYN_DIR, /* Xifan TANG: Synthesizable Verilog Dump */
OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING, /* Baudouin Chauviere: explicit pin mapping during verilog generation */
OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist */
OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist */
OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for the orignial input blif */

2
vpr7_x2p/vpr/SRC/base/ReadOptions.c
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@ -527,6 +527,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
return Args;
case OT_FPGA_VERILOG_SYN_DIR:
return ReadString(Args, &Options->fpga_syn_verilog_dir);
case OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING:
return Args;
case OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH:
return Args;
case OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH:

5
vpr7_x2p/vpr/SRC/base/SetupVPR.c
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@ -1088,6 +1088,7 @@ static void SetupSynVerilogOpts(t_options Options,
/* Initialize */
syn_verilog_opts->dump_syn_verilog = FALSE;
syn_verilog_opts->syn_verilog_dump_dir = NULL;
syn_verilog_opts->dump_explicit_verilog = FALSE;
syn_verilog_opts->print_top_testbench = FALSE;
syn_verilog_opts->print_autocheck_top_testbench = FALSE;
syn_verilog_opts->reference_verilog_benchmark_file = NULL;
@ -1114,6 +1115,10 @@ static void SetupSynVerilogOpts(t_options Options,
syn_verilog_opts->syn_verilog_dump_dir = my_strdup(Options.fpga_syn_verilog_dir);
}
if (Options.Count[OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING]) {
syn_verilog_opts->dump_explicit_verilog = TRUE;
}
if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH]) {
syn_verilog_opts->print_top_testbench = TRUE;
}

1
vpr7_x2p/vpr/SRC/base/vpr_api.c
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@ -194,6 +194,7 @@ void vpr_print_usage(void) {
vpr_printf(TIO_MESSAGE_INFO, "Synthesizable Verilog Generator Options:\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_dir <string>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_explicit_mapping\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_top_testbench\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_autocheck_top_testbench <reference_verilog_file_path>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_input_blif_testbench\n");

1
vpr7_x2p/vpr/SRC/base/vpr_types.h
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@ -1253,6 +1253,7 @@ struct s_spice_opts {
typedef struct s_syn_verilog_opts t_syn_verilog_opts;
struct s_syn_verilog_opts {
boolean dump_syn_verilog;
boolean dump_explicit_verilog;
char* syn_verilog_dump_dir;
boolean print_top_testbench;
boolean print_input_blif_testbench;

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
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@ -255,7 +255,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
/* Dump routing resources: switch blocks, connection blocks and channel tracks */
dump_verilog_routing_resources(sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, &vpr_setup.RoutingArch,
num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data,
vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
vpr_setup.FPGA_SPICE_Opts);
/* Dump logic blocks
* Branches to go:

1
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c
View File

@ -1195,6 +1195,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
int path_cnt) {
int L_wire;
int ix, iy;
int cur_sb_x, cur_sb_y;
int end_sb_x, end_sb_y;
t_cb* next_cb = NULL;
t_sb* next_sb = NULL;

27
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
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@ -941,7 +941,8 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* cur_rr_node,
int mux_size,
t_rr_node** drive_rr_nodes,
int switch_index) {
int switch_index,
boolean is_explicit_mapping) {
int input_cnt = 0;
t_spice_model* verilog_model = NULL;
int mux_level, path_id, cur_num_sram;
@ -1063,7 +1064,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -1382,7 +1383,8 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
const RRGSB& rr_sb,
enum e_side chan_side,
size_t chan_node_id) {
size_t chan_node_id,
boolean is_explicit_mapping) {
int num_drive_rr_nodes = 0;
t_rr_node** drive_rr_nodes = NULL;
@ -1418,7 +1420,8 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
/* Print the multiplexer, fan_in >= 2 */
dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node,
num_drive_rr_nodes, drive_rr_nodes,
cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]);
cur_rr_node->drive_switches[DEFAULT_SWITCH_ID],
is_explicit_mapping);
} /*Nothing should be done else*/
/* Free */
@ -1778,7 +1781,8 @@ static
void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
size_t module_id, size_t seg_id,
const RRGSB& rr_sb, enum e_side side) {
const RRGSB& rr_sb, enum e_side side,
boolean is_explicit_mapping) {
FILE* fp = NULL;
char* fname = NULL;
Side side_manager(side);
@ -1874,7 +1878,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
}
dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb,
side_manager.get_side(),
itrack);
itrack, is_explicit_mapping);
}
}
@ -2166,7 +2170,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
static
void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
const RRGSB& rr_sb) {
const RRGSB& rr_sb,
boolean is_explicit_mapping) {
FILE* fp = NULL;
char* fname = NULL;
@ -2284,7 +2289,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb,
side_manager.get_side(),
itrack);
itrack, is_explicit_mapping);
}
}
}
@ -3764,9 +3769,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
boolean compact_routing_hierarchy) {
t_fpga_spice_opts FPGA_SPICE_Opts) {
assert(UNI_DIRECTIONAL == routing_arch->directionality);
boolean compact_routing_hierarchy = FPGA_SPICE_Opts.compact_routing_hierarchy;
boolean explicit_port_mapping = FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog;
/* Two major tasks:
* 1. Generate sub-circuits for Routing Channels
* 2. Generate sub-circuits for Switch Boxes
@ -3832,7 +3839,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_submodule(side_manager.get_side(), iseg); ++isb) {
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_submodule(isb, side_manager.get_side(), iseg);
size_t seg_id = device_rr_gsb.get_segment_id(iseg);
dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side());
dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side(), explicit_port_mapping);
}
}
}

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h
View File

@ -132,6 +132,6 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
boolean compact_routing_hierarchy);
t_fpga_spice_opts FPGA_SPICE_Opts);
#endif

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c
View File

@ -477,7 +477,7 @@ void dump_verilog_defined_one_channel(FILE* fp,
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports_explicit(fp, global_ports_head, FALSE)) {
fprintf(fp, ",\n");
}

43
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -958,8 +958,49 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head,
/* fprintf(fp, "//----- BEGIN Global ports -----\n"); */
while(NULL != temp) {
cur_global_port = (t_spice_model_port*)(temp->dptr);
fprintf(fp, ".%s(",
if (TRUE == dump_port_type) {
fprintf(fp, "%s [0:%d] %s",
verilog_convert_port_type_to_string(cur_global_port->type),
cur_global_port->size - 1,
cur_global_port->prefix);
} else {
fprintf(fp, "%s[0:%d]",
cur_global_port->prefix,
cur_global_port->size - 1);
}
/* if this is the tail, we do not dump a comma */
if (NULL != temp->next) {
fprintf(fp, ", //---- global port \n");
}
/* Update counter */
dumped_port_cnt++;
/* Go to the next */
temp = temp->next;
}
/* fprintf(fp, "//----- END Global ports -----\n"); */
return dumped_port_cnt;
}
/* Dump all the global ports that are stored in the linked list */
int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head,
boolean dump_port_type) {
t_llist* temp = head;
t_spice_model_port* cur_global_port = NULL;
int dumped_port_cnt = 0;
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
__FILE__, __LINE__);
}
/* fprintf(fp, "//----- BEGIN Global ports -----\n"); */
while(NULL != temp) {
cur_global_port = (t_spice_model_port*)(temp->dptr);
fprintf(fp, ".%s(",
cur_global_port->prefix);
if (TRUE == dump_port_type) {
fprintf(fp, "%s [0:%d] %s",
verilog_convert_port_type_to_string(cur_global_port->type),

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
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@ -78,6 +78,9 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
int dump_verilog_global_ports(FILE* fp, t_llist* head,
boolean dump_port_type);
int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head,
boolean dump_port_type);
void dump_verilog_mux_sram_one_outport(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* cur_mux_spice_model, int mux_size,