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Changing arch from memory dec to scff. Get the bitstream from go.sh

This commit is contained in:
Baudouin Chauviere 2018-12-06 14:03:17 -07:00
parent 88af64c606
commit fe47b3d21f
3 changed files with 13 additions and 7 deletions
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13
fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml
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@ -344,12 +344,17 @@
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-->
<area grid_logic_tile_area="0"/>
<!--sram area="6" organization="standalone" circuit_model_name="sram6T"-->
<!--sram area="6" organization="scan-chain" circuit_model_name="sc_dff"-->
<sram area="6">
<!-- Choose only one organization, either the scan chain or the memory decoder -->
<sram area="6">
<verilog organization="scan-chain" circuit_model_name="sc_ff" />
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<!-- Uncomment to get the memory bank // Comment the scan-chain-->
<!-- <sram area="6">
<verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
</sram> -->
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>

5
vpr7_x2p/vpr/arch.xml
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@ -194,8 +194,9 @@
<area grid_logic_tile_area="0"/>
<sram area="6">
<verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>
<spice organization="standalone" circuit_model_name="sram6T" />
<!--<verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>-->
<verilog organization="scan-chain" circuit_model_name="static_dff" />
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<chan_width_distr>
<io width="1.000000"/>

2
vpr7_x2p/vpr/go.sh
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@ -3,7 +3,7 @@
# Pack, place, and route a heterogeneous FPGA
# Packing uses the AAPack algorithm
./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test
./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test --fpga_verilog_print_top_testbench