From fe47b3d21f64fa606259bbcff60fe3a965ef6874 Mon Sep 17 00:00:00 2001
From: Baudouin Chauviere <baudouin.chauviere@utah.edu>
Date: Thu, 6 Dec 2018 14:03:17 -0700
Subject: [PATCH] Changing arch from memory dec to scff. Get the bitstream from
 go.sh

---
 .../arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml     | 13 +++++++++----
 vpr7_x2p/vpr/arch.xml                               |  5 +++--
 vpr7_x2p/vpr/go.sh                                  |  2 +-
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml
index 51761ad07..eee87e4e5 100755
--- a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml
+++ b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml
@@ -344,12 +344,17 @@
      	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
 	  -->
 	<area grid_logic_tile_area="0"/> 
-    <!--sram area="6" organization="standalone" circuit_model_name="sram6T"-->
-    <!--sram area="6" organization="scan-chain" circuit_model_name="sc_dff"-->
-    <sram area="6">
+    
+	<!-- Choose only one organization, either the scan chain or the memory decoder -->
+	<sram area="6">
+		<verilog organization="scan-chain" circuit_model_name="sc_ff" />
+        <spice organization="standalone" circuit_model_name="sram6T" />
+    </sram>
+	<!-- Uncomment to get the memory bank // Comment the scan-chain-->
+	<!-- <sram area="6">
       <verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>
       <spice organization="standalone" circuit_model_name="sram6T" />
-    </sram>
+    </sram> -->
     <chan_width_distr>
       <io width="1.000000"/>
       <x distr="uniform" peak="1.000000"/>
diff --git a/vpr7_x2p/vpr/arch.xml b/vpr7_x2p/vpr/arch.xml
index 846f9dc4c..c39197281 100644
--- a/vpr7_x2p/vpr/arch.xml
+++ b/vpr7_x2p/vpr/arch.xml
@@ -194,8 +194,9 @@
 
     <area grid_logic_tile_area="0"/> 
     <sram area="6">
-      <verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>
-      <spice organization="standalone" circuit_model_name="sram6T" />
+      <!--<verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>-->
+      <verilog organization="scan-chain" circuit_model_name="static_dff" />
+	  <spice organization="standalone" circuit_model_name="sram6T" />
     </sram>
     <chan_width_distr>
       <io width="1.000000"/>
diff --git a/vpr7_x2p/vpr/go.sh b/vpr7_x2p/vpr/go.sh
index eb7d2eba2..e9cbbd8de 100755
--- a/vpr7_x2p/vpr/go.sh
+++ b/vpr7_x2p/vpr/go.sh
@@ -3,7 +3,7 @@
 
 # Pack, place, and route a heterogeneous FPGA
 # Packing uses the AAPack algorithm
-./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test
+./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test --fpga_verilog_print_top_testbench