riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Bug fix in Icarus requirement

This commit is contained in:
AurelienUoU 2019-05-10 14:07:32 -06:00
parent 4c6639218e
commit ff9b84d800
6 changed files with 32 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml
View File

@ -92,7 +92,7 @@
<port name="inpad"/>
</output_ports>
</model>
<!--model name="multiply">
<model name="multiply">
<input_ports>
<port name="a"/>
<port name="b"/>
@ -102,7 +102,7 @@
</output_ports>
</model>
<model name="single_port_ram">
<!--model name="single_port_ram">
<input_ports>
<port name="we"/--> <!-- control -->
<!--port name="addr"/--> <!-- address lines -->
@ -645,7 +645,7 @@
area associated with our DSP block is four times that of a logic tile, where the routing area of a logic tile was calculated above (at W = 300)
as 30481 MWTAs. Hence the (core, non-routing) area our DSP block is approximately 518,000 - 4 * 30,481 = 396,000 MWTUs.
-->
<!--pb_type name="mult_36" height="4" area="396000">
<pb_type name="mult_36" height="4" area="396000">
<input name="a" num_pins="36"/>
<input name="b" num_pins="36"/>
@ -655,18 +655,18 @@
<pb_type name="divisible_mult_18x18" num_pb="2">
<input name="a" num_pins="18"/>
<input name="b" num_pins="18"/>
<output name="out" num_pins="36"/-->
<output name="out" num_pins="36"/>
<!-- Model 9x9 delay and 18x18 delay as the same. 9x9 could be faster, but in Stratix IV
isn't, presumably because the multiplier layout is really optimized for 18x18.
-->
<!--mode name="two_mult_9x9">
<mode name="two_mult_9x9">
<pb_type name="mult_9x9_slice" num_pb="2">
<input name="A_cfg" num_pins="9"/>
<input name="B_cfg" num_pins="9"/>
<output name="OUT_cfg" num_pins="18"/>
<pb_type name="mult_9x9" blif_model=".subckt multiply" num_pb="1">
<pb_type name="mult_9x9" blif_model=".subckt multiply9" num_pb="1">
<input name="a" num_pins="9"/>
<input name="b" num_pins="9"/>
<output name="out" num_pins="18"/>
@ -705,7 +705,7 @@
<input name="B_cfg" num_pins="18"/>
<output name="OUT_cfg" num_pins="36"/>
<pb_type name="mult_18x18" blif_model=".subckt multiply" num_pb="1" >
<pb_type name="mult_18x18" blif_model=".subckt multiply18" num_pb="1" >
<input name="a" num_pins="18"/>
<input name="b" num_pins="18"/>
<output name="out" num_pins="36"/>
@ -739,11 +739,11 @@
<power method="sum-of-children"/>
</pb_type>
<interconnect-->
<interconnect>
<!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier.
Subtract 72.5 ps delay, which is already in the connection block input mux, leading
-->
<!--direct name="a2a" input="mult_36.a" output="divisible_mult_18x18[1:0].a">
<direct name="a2a" input="mult_36.a" output="divisible_mult_18x18[1:0].a">
<delay_constant max="134e-12" in_port="mult_36.a" out_port="divisible_mult_18x18[1:0].a"/>
</direct>
<direct name="b2b" input="mult_36.b" output="divisible_mult_18x18[1:0].b">
@ -761,7 +761,7 @@
<input name="B_cfg" num_pins="36"/>
<output name="OUT_cfg" num_pins="72"/>
<pb_type name="mult_36x36" blif_model=".subckt multiply" num_pb="1">
<pb_type name="mult_36x36" blif_model=".subckt multiply36" num_pb="1">
<input name="a" num_pins="36"/>
<input name="b" num_pins="36"/>
<output name="out" num_pins="72"/>
@ -784,12 +784,12 @@
<static_power power_per_instance="0.0"/>
</power>
</pb_type>
<interconnect-->
<interconnect>
<!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier.
Subtract 72.5 ps delay, which is already in the connection block input mux, leading
to a 134 ps delay.
-->
<!--direct name="a2a" input="mult_36.a" output="mult_36x36_slice.A_cfg">
<direct name="a2a" input="mult_36.a" output="mult_36x36_slice.A_cfg">
<delay_constant max="134e-12" in_port="mult_36.a" out_port="mult_36x36_slice.A_cfg"/>
</direct>
<direct name="b2b" input="mult_36.b" output="mult_36x36_slice.B_cfg">
@ -803,14 +803,14 @@
</mode>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<pinlocations pattern="spread"/-->
<pinlocations pattern="spread"/>
<!-- Place this multiplier block every 8 columns from (and including) the sixth column -->
<!--gridlocations>
<gridlocations>
<loc type="col" start="6" repeat="8" priority="2"/>
</gridlocations>
<power method="sum-of-children"/>
</pb_type-->
</pb_type>
<!-- Define fracturable multiplier end -->
<!-- Define fracturable memory begin -->

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c
View File

@ -272,7 +272,7 @@ void dump_verilog_timeout_and_vcd(FILE * fp,
fprintf(fp, " // Begin Icarus requirement\n");
fprintf(fp, "`ifdef %s\n", icarus_simulator_flag);
fprintf(fp, " initial begin\n");
fprintf(fp, " $dumpfile(%s_autochecked.vcd);\n", circuit_name);
fprintf(fp, " $dumpfile(\"%s_autochecked.vcd\");\n", circuit_name);
fprintf(fp, " $dumpvars(1, %s%s);\n", circuit_name,
modelsim_autocheck_testbench_module_postfix);
fprintf(fp, " end\n\n");

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c
View File

@ -192,9 +192,9 @@ void dump_verilog_timeout_and_vcd(FILE * fp,
fprintf(fp, " // Begin Icarus requirement\n");
fprintf(fp, "`ifdef %s\n", icarus_simulator_flag);
fprintf(fp, " initial begin\n");
fprintf(fp, " $dumpfile(%s_autochecked.vcd);\n", circuit_name);
fprintf(fp, " $dumpfile(\"%s_formal.vcd\");\n", circuit_name);
fprintf(fp, " $dumpvars(1, %s%s);\n", circuit_name,
modelsim_autocheck_testbench_module_postfix);
formal_random_top_tb_postfix);
fprintf(fp, " end\n\n");
fprintf(fp, " initial begin\n");
fprintf(fp, " $display(\"Simulation start\");\n");

12
vpr7_x2p/vpr/VerilogNetlists/adder.v
View File

@ -8,12 +8,12 @@ input [0:0] cin, // Input cin
output [0:0] cout, // Output carry
output [0:0] sumout // Output sum
);
wire[1:0] int_calc;
//wire[1:0] int_calc;
assign int_calc = a + b + cin;
assign cout = int_calc[1];
assign sumout = int_calc[0];
// assign sumout = a ^ b ^ cin;
// assign cout = a & b + a & cin + b & cin;
//assign int_calc = a + b + cin;
//assign cout = int_calc[1];
//assign sumout = int_calc[0];
assign sumout = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule

2
vpr7_x2p/vpr/VerilogNetlists/io.v
View File

@ -2,7 +2,7 @@
//------ Verilog file: io.v -----//
//------ Author: Xifan TANG -----//
module iopad(
input zin, // Set output to be Z
//input zin, // Set output to be Z
input dout, // Data output
output din, // Data input
inout pad, // bi-directional pad

13
vpr7_x2p/vpr/go_fpga_verilog.sh
View File

@ -3,13 +3,14 @@
# Set variables
# For FPGA-Verilog ONLY
set verilog_output_dirname = OpenFPGA_Branch
set verilog_output_dirpath = /var/tmp/AA_simu/
set benchmark = s298_prevpr
set verilog_output_dirname = ${benchmark}_Verilog
set verilog_output_dirpath = $PWD
set modelsim_ini_file = /uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini
# VPR critical inputs
#set arch_xml_file = ARCH/k6_N10_MD_tsmc40nm_chain_TT.xml
#set arch_xml_file = ARCH/k8_N10_SC_tsmc40nm_chain_TT_stratixIV_lookalike.xml
set arch_xml_file = ARCH/k8_N10_sram_chain_FC_tsmc40_stratix4_auto.xml
set arch_xml_file = ARCH/k6_N10_sram_chain_HC_template.xml
#set arch_xml_file = ARCH/ed_stdcell.xml
#set arch_xml_file = ARCH/k6_N10_sram_chain_FC_tsmc40.xml
#set arch_xml_file = ARCH/k6_N10_SC_tsmc40nm_chain_TT.xml
@ -18,9 +19,9 @@ set arch_xml_file = ARCH/k8_N10_sram_chain_FC_tsmc40_stratix4_auto.xml
#set verilog_reference = ${PWD}/Circuits/alu4_K6_N10_ace.v
#set blif_file = Circuits/shiftReg.blif
#set act_file = Circuits/shiftReg.act
set blif_file = Circuits/s298_prevpr.blif
set act_file = Circuits/s298_prevpr.act
set verilog_reference = ${PWD}/Circuits/s298_prevpr.v
set blif_file = Circuits/$benchmark.blif
set act_file = Circuits/$benchmark.act
set verilog_reference = ${PWD}/Circuits/$benchmark.v
#set blif_file = Circuits/frisc.blif
#set act_file = Circuits/frisc.act
#set blif_file = Circuits/elliptic.blif