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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb

This commit is contained in:
tangxifan 2019-05-08 14:30:33 -06:00
parent e305e60ee4 4f386de2ef
commit 4c6639218e
6 changed files with 72 additions and 68 deletions
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4
vpr7_x2p/libarchfpga/Makefile
View File

@ -47,10 +47,10 @@ libarchfpga.a: $(OBJ) ../libpcre/libpcre.a ../libprinthandler/libprinthandler.a
cp ../libprinthandler/libprinthandler.a $@
ar rcs $@ $(OBJ)
../pcre/libpcre.a:
../libpcre/libpcre.a:
@ cd ../libpcre && make
../printhandler/libprinthandler.a:
../libprinthandler/libprinthandler.a:
@ cd ../libprinthandler && make
# Enable a second round of expansion so that we may include

16
vpr7_x2p/libarchfpga/SRC/include/physical_types.h
View File

@ -319,10 +319,10 @@ struct s_interconnect {
char *output_string;
/* Baudouin Chauviere: SDC generation */
char *loop_breaker_string;
char *loop_breaker_delay_first_segment_min;
char *loop_breaker_delay_first_segment_max;
char *loop_breaker_delay_second_segment_min;
char *loop_breaker_delay_second_segment_max;
char *loop_breaker_delay_before_min;
char *loop_breaker_delay_before_max;
char *loop_breaker_delay_after_min;
char *loop_breaker_delay_after_max;
/* END */
t_pin_to_pin_annotation *annotations; /* [0..num_annotations-1] */
@ -549,10 +549,10 @@ struct s_pb_graph_edge {
boolean is_disabled;
int nb_mux;
int nb_pin;
char* delay_first_segment_max;
char* delay_second_segment_max;
char* delay_first_segment_min;
char* delay_second_segment_min;
char* loop_breaker_delay_before_max;
char* loop_breaker_delay_after_max;
char* loop_breaker_delay_before_min;
char* loop_breaker_delay_after_min;
/* END */
};
typedef struct s_pb_graph_edge t_pb_graph_edge;

12
vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c
View File

@ -1412,30 +1412,30 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {
}
ezxml_set_attr(Cur, "loop_breaker", NULL);
Cur2 = FindFirstElement(Cur, "delay_first_segment", FALSE);
Cur2 = FindFirstElement(Cur, "loop_breaker_delay_before", FALSE);
if (NULL != Cur2) {
Prop = FindProperty(Cur2, "min", FALSE);
if (NULL != Prop) {
mode->interconnect[i].loop_breaker_delay_first_segment_min = my_strdup(Prop);
mode->interconnect[i].loop_breaker_delay_before_min = my_strdup(Prop);
ezxml_set_attr(Cur2, "min", NULL);
}
Prop = FindProperty(Cur2, "max", FALSE);
if (NULL != Prop) {
mode->interconnect[i].loop_breaker_delay_first_segment_max = my_strdup(Prop);
mode->interconnect[i].loop_breaker_delay_before_max = my_strdup(Prop);
ezxml_set_attr(Cur2, "max", NULL);
}
FreeNode(Cur2);
}
Cur2 = FindFirstElement(Cur, "delay_second_segment", FALSE);
Cur2 = FindFirstElement(Cur, "loop_breaker_delay_after", FALSE);
if (NULL != Cur2) {
Prop = FindProperty(Cur2, "min", FALSE);
if (NULL != Prop) {
mode->interconnect[i].loop_breaker_delay_second_segment_min = my_strdup(Prop);
mode->interconnect[i].loop_breaker_delay_after_min = my_strdup(Prop);
ezxml_set_attr(Cur2, "min", NULL);
}
Prop = FindProperty(Cur2, "max", FALSE);
if (NULL != Prop) {
mode->interconnect[i].loop_breaker_delay_second_segment_max = my_strdup(Prop);
mode->interconnect[i].loop_breaker_delay_after_max = my_strdup(Prop);
ezxml_set_attr(Cur2, "max", NULL);
}
FreeNode(Cur2);

26
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c
View File

@ -251,22 +251,24 @@ void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
sprintf(set_disable_path, "%s/%s_%d_", input_buffer_path, input_buffer_name,
des_pb_graph_pin->input_edges[iedge]->nb_pin);
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_first_segment_min) {
fprintf (fp, "set_min_delay -from %s -to %s/%s %s \n", from_path, set_disable_path, input_buffer_in,
des_pb_graph_pin->input_edges[iedge]->delay_first_segment_min);
if (NULL != des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_before_min) {
fprintf (fp, "set_min_delay -from %s -to %s/%s %f \n", from_path, set_disable_path, input_buffer_in,
pow(10,9)*atof(des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_before_min));
}
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_first_segment_max) {
fprintf (fp, "set_max_delay -from %s -to %s/%s %s \n", from_path, set_disable_path, input_buffer_in,
des_pb_graph_pin->input_edges[iedge]->delay_first_segment_max);
if (NULL != des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_before_max) {
fprintf (fp, "set_max_delay -from %s -to %s/%s %f \n", from_path, set_disable_path, input_buffer_in,
pow(10,9)*atof(des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_before_max));
}
fprintf (fp, "set_disable_timing -from %s -to %s %s \n", input_buffer_in, input_buffer_out, set_disable_path);
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_second_segment_min) {
fprintf (fp, "set_min_delay -from %s/%s -to %s %s \n", set_disable_path, input_buffer_out,
to_path, des_pb_graph_pin->input_edges[iedge]->delay_second_segment_min);
if (NULL != des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_after_min) {
fprintf (fp, "set_min_delay -from %s/%s -to %s %f \n", set_disable_path, input_buffer_out,
to_path,
pow(10,9)*atof(des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_after_min));
}
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_second_segment_max) {
fprintf (fp, "set_max_delay -from %s/%s -to %s %s \n", set_disable_path, input_buffer_out,
to_path, des_pb_graph_pin->input_edges[iedge]->delay_second_segment_max);
if (NULL != des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_after_max) {
fprintf (fp, "set_max_delay -from %s/%s -to %s %f \n", set_disable_path, input_buffer_out,
to_path,
pow(10,9)*atof(des_pb_graph_pin->input_edges[iedge]->loop_breaker_delay_after_max));
}
my_free(input_buffer_path);
my_free(set_disable_path);

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c
View File

@ -64,6 +64,7 @@ void dump_verilog_one_sb_chan_pin(FILE* fp,
enum PORTS port_type) {
int track_idx, side;
int x_start, y_start;
char* pin_name;
t_rr_type chan_rr_type;
/* Check the file handler */
@ -86,11 +87,12 @@ void dump_verilog_one_sb_chan_pin(FILE* fp,
&(chan_rr_type),
&x_start, &y_start);
assert (chan_rr_type == cur_rr_node->type);
/* Print the pin of the cur_rr_node */
fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(cur_rr_node,
/* Print the pin of the cur_rr_node */
pin_name = gen_verilog_routing_channel_one_pin_name(cur_rr_node,
x_start, y_start, track_idx,
port_type));
port_type);
fprintf(fp, "%s", pin_name);
free(pin_name);
return;
}

72
vpr7_x2p/vpr/SRC/pack/pb_type_graph.c
View File

@ -2071,21 +2071,21 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num,
if (cur_interc == cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE;
if (NULL != cur_interc->loop_breaker_delay_first_segment_min) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min
= cur_interc->loop_breaker_delay_first_segment_min;
if (NULL != cur_interc->loop_breaker_delay_before_min) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_min
= cur_interc->loop_breaker_delay_before_min;
}
if (NULL != cur_interc->loop_breaker_delay_first_segment_max) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max
= cur_interc->loop_breaker_delay_first_segment_max;
if (NULL != cur_interc->loop_breaker_delay_before_max) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_max
= cur_interc->loop_breaker_delay_before_max;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_min) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min
= cur_interc->loop_breaker_delay_second_segment_min;
if (NULL != cur_interc->loop_breaker_delay_after_min) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_min
= cur_interc->loop_breaker_delay_after_min;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_max) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max
= cur_interc->loop_breaker_delay_second_segment_max;
if (NULL != cur_interc->loop_breaker_delay_after_max) {
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_max
= cur_interc->loop_breaker_delay_after_max;
}
}
}
@ -2097,21 +2097,21 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num,
if (cur_interc == cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE;
if (NULL != cur_interc->loop_breaker_delay_first_segment_min) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min
= cur_interc->loop_breaker_delay_first_segment_min;
if (NULL != cur_interc->loop_breaker_delay_before_min) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_min
= cur_interc->loop_breaker_delay_before_min;
}
if (NULL != cur_interc->loop_breaker_delay_first_segment_max) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max
= cur_interc->loop_breaker_delay_first_segment_max;
if (NULL != cur_interc->loop_breaker_delay_before_max) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_max
= cur_interc->loop_breaker_delay_before_max;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_min) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min
= cur_interc->loop_breaker_delay_second_segment_min;
if (NULL != cur_interc->loop_breaker_delay_after_min) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_min
= cur_interc->loop_breaker_delay_after_min;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_max) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max
= cur_interc->loop_breaker_delay_second_segment_max;
if (NULL != cur_interc->loop_breaker_delay_after_max) {
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_max
= cur_interc->loop_breaker_delay_after_max;
}
}
}
@ -2123,21 +2123,21 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num,
if (cur_interc == cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE;
if (NULL != cur_interc->loop_breaker_delay_first_segment_min) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min
= cur_interc->loop_breaker_delay_first_segment_min;
if (NULL != cur_interc->loop_breaker_delay_before_min) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_min
= cur_interc->loop_breaker_delay_before_min;
}
if (NULL != cur_interc->loop_breaker_delay_first_segment_max) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max
= cur_interc->loop_breaker_delay_first_segment_max;
if (NULL != cur_interc->loop_breaker_delay_before_max) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_max
= cur_interc->loop_breaker_delay_before_max;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_min) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min
= cur_interc->loop_breaker_delay_second_segment_min;
if (NULL != cur_interc->loop_breaker_delay_after_min) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_min
= cur_interc->loop_breaker_delay_after_min;
}
if (NULL != cur_interc->loop_breaker_delay_second_segment_max) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max
= cur_interc->loop_breaker_delay_second_segment_max;
if (NULL != cur_interc->loop_breaker_delay_after_max) {
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_max
= cur_interc->loop_breaker_delay_after_max;
}
}
}