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Merge branch 'tileable_routing' into dev

This commit is contained in:
tangxifan 2019-07-10 12:05:43 -06:00
parent 737cc2874f 57ae5dbbec
commit c6a4d29ed8
2 changed files with 15 additions and 2 deletions
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13
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
View File

@ -1324,6 +1324,10 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
clock_t t_end;
float run_time_sec;
clock_t t_start_profiling;
clock_t t_end_profiling;
float run_time_sec_profiling = 0.;
/* Start time count */
t_start = clock();
@ -1342,8 +1346,15 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
LL_num_rr_nodes, LL_rr_node,
LL_rr_node_indices,
num_segments, LL_rr_indexed_data);
/* For profiling */
t_start_profiling = clock();
/* sort drive_rr_nodes */
sort_rr_gsb_drive_rr_nodes(rr_gsb);
/* End time count */
t_end_profiling = clock();
run_time_sec_profiling += (float)(t_end_profiling - t_start_profiling) / CLOCKS_PER_SEC;
/* Add to device_rr_gsb */
DeviceCoordinator sb_coordinator = rr_gsb.get_sb_coordinator();
LL_device_rr_gsb.add_rr_gsb(sb_coordinator, rr_gsb);
@ -1360,6 +1371,8 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
vpr_printf(TIO_MESSAGE_INFO, "Backannotation of Switch Block took %g seconds\n\n", run_time_sec);
vpr_printf(TIO_MESSAGE_INFO, "Edge sorting for Switch Block took %g seconds\n\n", run_time_sec_profiling);
if (TRUE == output_sb_xml) {
create_dir_path(sb_xml_dir);

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -1019,7 +1019,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
/* Get X-channel CB coordinator */
const DeviceCoordinator cbx_coordinator = rr_gsb.get_cb_coordinator(CHANX);
/* X - channels [1...nx][0..ny]*/
if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_x()))
if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_y()))
&&(true == rr_gsb.is_cb_exist(CHANX))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX, is_explicit_mapping);
}
@ -1027,7 +1027,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
/* Get X-channel CB coordinator */
const DeviceCoordinator cby_coordinator = rr_gsb.get_cb_coordinator(CHANY);
/* Y - channels [1...ny][0..nx]*/
if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_x()))
if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_y()))
&&(true == rr_gsb.is_cb_exist(CHANY))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY, is_explicit_mapping);
}