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bug fixing for rectangle FPGA sizes

This commit is contained in:
tangxifan 2019-07-09 20:47:52 -06:00
parent edfe3144c3
commit 57ae5dbbec
1 changed files with 2 additions and 2 deletions
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4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
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@ -986,7 +986,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
/* Get X-channel CB coordinator */
const DeviceCoordinator cbx_coordinator = rr_gsb.get_cb_coordinator(CHANX);
/* X - channels [1...nx][0..ny]*/
if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_x()))
if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_y()))
&&(true == rr_gsb.is_cb_exist(CHANX))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX);
}
@ -994,7 +994,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
/* Get X-channel CB coordinator */
const DeviceCoordinator cby_coordinator = rr_gsb.get_cb_coordinator(CHANY);
/* Y - channels [1...ny][0..nx]*/
if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_x()))
if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_y()))
&&(true == rr_gsb.is_cb_exist(CHANY))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY);
}