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rename rr_switch_block to rr_gsb, a generic block

This commit is contained in:
tangxifan 2019-06-06 17:41:01 -06:00
parent 8c1e7b799f
commit ce9fc5696c
21 changed files with 361 additions and 335 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c
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@ -30,6 +30,8 @@
#include "verilog_api.h"
#include "fpga_bitstream.h"
#include "fpga_x2p_api.h"
/* Top-level API of FPGA-SPICE */
void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup,
t_arch Arch) {

5
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.h
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@ -1,5 +1,8 @@
#ifndef FPGA_X2P_API_H
#define FPGA_X2P_API_H
void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup,
t_arch Arch);
#endif

17
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c
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@ -38,6 +38,8 @@
#include "fpga_x2p_router.h"
#include "fpga_x2p_unique_routing.h"
#include "fpga_x2p_backannotate_utils.h"
/* Get initial value of a Latch/FF output*/
int get_ff_output_init_val(t_logical_block* ff_logical_block) {
assert((0 == ff_logical_block->init_val)||(1 == ff_logical_block->init_val));
@ -45,6 +47,7 @@ int get_ff_output_init_val(t_logical_block* ff_logical_block) {
return ff_logical_block->init_val;
}
static
int determine_rr_node_default_prev_node(t_rr_node* cur_rr_node) {
int default_prev_node = DEFAULT_PREV_NODE;
@ -653,6 +656,7 @@ void get_rr_node_side_and_index_in_cb_info(t_rr_node* cur_rr_node,
/***** Recursively Backannotate parasitic_net_num for a rr_node*****/
static
void rec_backannotate_rr_node_net_num(int LL_num_rr_nodes,
t_rr_node* LL_rr_node,
int src_node_index) {
@ -1352,6 +1356,7 @@ void back_annotate_rr_node_map_info() {
return;
}
static
void rec_sync_pb_post_routing_vpack_net_num(t_pb* cur_pb) {
int ipb, jpb, select_mode_index;
int iport, ipin, node_index;
@ -1423,6 +1428,7 @@ void rec_sync_pb_post_routing_vpack_net_num(t_pb* cur_pb) {
* while the top-level type_descriptor consider 8 io in counting the pins
* so we just update the vpack_net_num and net_num in all the hierachy level
*/
static
void update_one_io_grid_pack_net_num(int x, int y) {
int iblk, blk_id;
t_type_ptr type = NULL;
@ -1456,6 +1462,7 @@ void update_one_io_grid_pack_net_num(int x, int y) {
* which potentially changes the packing results (net_num and vpack_net_num) in local routing
* The following functions are to update the local routing results to match them with routing results
*/
static
void update_one_grid_pack_net_num(int x, int y) {
int iblk, blk_id, ipin, iedge, jedge, inode;
int pin_global_rr_node_id, vpack_net_id, class_id;
@ -1601,6 +1608,7 @@ void update_grid_pbs_post_route_rr_graph() {
/* In this function, we update the vpack_net_num in global rr_graph
* from the temp_net_num stored in the top_pb_graph_head
*/
static
void update_one_unused_grid_output_pins_parasitic_nets(int ix, int iy) {
int iport, ipin;
int pin_global_rr_node_id, class_id, type_pin_index;
@ -1651,6 +1659,7 @@ void update_one_unused_grid_output_pins_parasitic_nets(int ix, int iy) {
* are absorbed into CLBs during packing, therefore they are invisible in
* clb_nets. But indeed, they exist in global routing as parasitic nets.
*/
static
void update_one_used_grid_pb_pins_parasitic_nets(t_phy_pb* cur_pb,
int ix, int iy) {
int ipin, cur_pin;
@ -1715,6 +1724,7 @@ void update_one_used_grid_pb_pins_parasitic_nets(t_phy_pb* cur_pb,
}
static
void update_one_grid_pb_pins_parasitic_nets(int ix, int iy) {
int iblk;
@ -1745,7 +1755,7 @@ void update_one_grid_pb_pins_parasitic_nets(int ix, int iy) {
return;
}
static
void update_grid_pb_pins_parasitic_nets() {
int ix, iy;
t_type_ptr type = NULL;
@ -2684,6 +2694,7 @@ void rec_annotate_pb_type_primitive_node_physical_mode_pin(t_pb_type* top_pb_typ
/* Annotate the physical_mode_pin in pb_type ports,
* Go recursively until we reach a primtiive node
*/
static
void rec_annotate_phy_pb_type_primitive_node_physical_mode_pin(t_pb_type* top_pb_type,
t_pb_type* cur_pb_type) {
int phy_mode_idx, ipb, iport;
@ -2740,6 +2751,7 @@ void rec_annotate_phy_pb_type_primitive_node_physical_mode_pin(t_pb_type* top_pb
/* Go recursively visiting each primitive node in the pb_graph_node
* Label the primitive node with a placement index which is unique at the top-level node
*/
static
void rec_mark_pb_graph_node_primitive_placement_index_in_top_node(t_pb_graph_node* cur_pb_graph_node) {
int imode, ipb, jpb;
t_pb_type* cur_pb_type = NULL;
@ -2928,6 +2940,7 @@ void alloc_and_load_phy_pb_for_mapped_block(int num_mapped_blocks, t_block* mapp
* 4. Create the wired LUTs in logical block array
* 5. Create new vpack nets to rewire the logical blocks
*/
static
void rec_backannotate_one_pb_wired_luts_and_adapt_graph(t_pb* cur_pb,
int* L_num_logical_blocks, t_net** L_logical_block,
int* L_num_vpack_nets, t_net** L_vpack_net) {
@ -3024,6 +3037,7 @@ void backannotate_pb_wired_luts(int num_mapped_blocks, t_block* mapped_block,
return;
}
static
int find_matched_block_id_for_one_grid(int x, int y) {
int iblk, jblk, blk_id;
boolean already_exist = FALSE;
@ -3058,6 +3072,7 @@ int find_matched_block_id_for_one_grid(int x, int y) {
/* Some IO blocks has an invalid BLOCK ID but with a >0 usage
* We go through the block list and find the missing block ID
*/
static
void annotate_grid_block_info() {
int ix, iy;
t_type_ptr type = NULL;

3
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h
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@ -1,3 +1,5 @@
#ifndef FPGA_X2P_BACKANNOTATE_UTILS_H
#define FPGA_X2P_BACKANNOTATE_UTILS_H
int get_ff_output_init_val(t_logical_block* ff_logical_block);
@ -103,3 +105,4 @@ void spice_backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch,
boolean read_activity_file,
boolean parasitic_net_estimation);
#endif

2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c
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@ -46,4 +46,4 @@ char* fpga_spice_bitstream_routing_log_file_postfix = "_routing_bitstream.log";
char* default_sdc_folder = "SDC/";
DeviceRRChan device_rr_chan;
DeviceRRSwitchBlock device_rr_switch_block;
DeviceRRGSB device_rr_gsb;

2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h
View File

@ -41,6 +41,6 @@ extern char* fpga_spice_bitstream_logic_block_log_file_postfix;
extern char* fpga_spice_bitstream_routing_log_file_postfix;
extern DeviceRRChan device_rr_chan;
extern DeviceRRSwitchBlock device_rr_switch_block;
extern DeviceRRGSB device_rr_gsb;
#endif

9
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c
View File

@ -32,6 +32,7 @@
#include "fpga_x2p_pbtypes_utils.h"
#include "verilog_api.h"
#include "fpga_x2p_unique_routing.h"
#include "fpga_x2p_setup.h"
/***** Subroutines Declarations *****/
@ -1400,10 +1401,10 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup,
/* Assign Gobal variable: build the Routing Resource Channels */
device_rr_chan = build_device_rr_chan(num_rr_nodes, rr_node, rr_node_indices, Arch->num_segments, rr_indexed_data);
device_rr_switch_block = build_device_rr_switch_blocks(vpr_setup.FPGA_SPICE_Opts.output_sb_xml,
vpr_setup.FPGA_SPICE_Opts.sb_xml_dir,
num_rr_nodes, rr_node, rr_node_indices,
Arch->num_segments, rr_indexed_data);
device_rr_gsb = build_device_rr_gsb(vpr_setup.FPGA_SPICE_Opts.output_sb_xml,
vpr_setup.FPGA_SPICE_Opts.sb_xml_dir,
num_rr_nodes, rr_node, rr_node_indices,
Arch->num_segments, rr_indexed_data);
/* Rotatable will be done in the next step
identify_rotatable_switch_blocks();

58
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
View File

@ -799,13 +799,13 @@ DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node,
* For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs
*/
static
RRSwitchBlock build_rr_switch_block(DeviceCoordinator& device_range,
RRGSB build_rr_switch_block(DeviceCoordinator& device_range,
size_t sb_x, size_t sb_y,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices, int num_segments,
t_rr_indexed_data* LL_rr_indexed_data) {
/* Create an object to return */
RRSwitchBlock rr_switch_block;
RRGSB rr_switch_block;
/* Check */
assert(sb_x <= device_range.get_x());
@ -1014,14 +1014,16 @@ RRSwitchBlock build_rr_switch_block(DeviceCoordinator& device_range,
opin_grid_side[1] = NUM_SIDES;
}
/* Build the connection block */
return rr_switch_block;
}
/* Rotate the Switch block and try to add to rotatable mirrors */
static
RRSwitchBlock rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
const RRSwitchBlock& rr_switch_block) {
RRSwitchBlock rotated_rr_switch_block;
RRGSB rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
const RRGSB& rr_switch_block) {
RRGSB rotated_rr_switch_block;
rotated_rr_switch_block.set(rr_switch_block);
size_t Fco_offset = 1;
@ -1174,27 +1176,27 @@ RRSwitchBlock rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
* Each switch block in the FPGA fabric will be an instance of these modules.
* We maintain a map from each instance to each module
*/
DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* sb_xml_dir,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices, int num_segments,
t_rr_indexed_data* LL_rr_indexed_data) {
DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices, int num_segments,
t_rr_indexed_data* LL_rr_indexed_data) {
/* Create an object */
DeviceRRSwitchBlock LL_device_rr_switch_block;
DeviceRRGSB LL_drive_rr_gsb;
/* Initialize */
DeviceCoordinator sb_range((size_t)nx, (size_t)ny);
DeviceCoordinator reserve_range((size_t)nx + 1, (size_t)ny + 1);
LL_device_rr_switch_block.reserve(reserve_range);
LL_drive_rr_gsb.reserve(reserve_range);
/* For each switch block, determine the size of array */
for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) {
RRSwitchBlock rr_sb = build_rr_switch_block(sb_range, ix, iy,
RRGSB rr_sb = build_rr_switch_block(sb_range, ix, iy,
LL_num_rr_nodes, LL_rr_node,
LL_rr_node_indices,
num_segments, LL_rr_indexed_data);
DeviceCoordinator sb_coordinator = rr_sb.get_coordinator();
LL_device_rr_switch_block.add_rr_switch_block(sb_coordinator, rr_sb);
LL_drive_rr_gsb.add_rr_switch_block(sb_coordinator, rr_sb);
}
}
/* Report number of unique mirrors */
@ -1202,13 +1204,13 @@ DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* s
"Backannotated %d switch blocks.\n",
(nx + 1) * (ny + 1) );
LL_device_rr_switch_block.build_segment_ids();
LL_drive_rr_gsb.build_segment_ids();
vpr_printf(TIO_MESSAGE_INFO,
"Detect %lu routing segments used by switch blocks.\n",
LL_device_rr_switch_block.get_num_segments());
LL_drive_rr_gsb.get_num_segments());
if (TRUE == output_sb_xml) {
write_device_rr_switch_block_to_xml(sb_xml_dir, LL_device_rr_switch_block);
write_device_rr_gsb_to_xml(sb_xml_dir, LL_drive_rr_gsb);
/* Skip rotating mirror searching */
vpr_printf(TIO_MESSAGE_INFO,
@ -1218,24 +1220,24 @@ DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* s
}
/* Build a list of unique modules for each Switch Block */
LL_device_rr_switch_block.build_unique_mirror();
LL_drive_rr_gsb.build_unique_mirror();
/* Report number of unique mirrors */
vpr_printf(TIO_MESSAGE_INFO,
"Detect %d independent switch blocks from %d switch blocks.\n",
LL_device_rr_switch_block.get_num_unique_mirror(), (nx + 1) * (ny + 1) );
LL_drive_rr_gsb.get_num_unique_mirror(), (nx + 1) * (ny + 1) );
/* Build a list of unique modules for each side of each Switch Block */
LL_device_rr_switch_block.build_unique_module();
LL_drive_rr_gsb.build_unique_module();
/* Report number of unique mirrors */
for (size_t side = 0; side < LL_device_rr_switch_block.get_max_num_sides(); ++side) {
for (size_t side = 0; side < LL_drive_rr_gsb.get_max_num_sides(); ++side) {
Side side_manager(side);
/* get segment ids */
for (size_t iseg = 0; iseg < LL_device_rr_switch_block.get_num_segments(); ++iseg) {
for (size_t iseg = 0; iseg < LL_drive_rr_gsb.get_num_segments(); ++iseg) {
vpr_printf(TIO_MESSAGE_INFO,
"For side %s, segment id %lu: Detect %d independent switch blocks from %d switch blocks.\n",
side_manager.to_string(), LL_device_rr_switch_block.get_segment_id(iseg),
LL_device_rr_switch_block.get_num_unique_module(side_manager.get_side(), iseg),
side_manager.to_string(), LL_drive_rr_gsb.get_segment_id(iseg),
LL_drive_rr_gsb.get_num_unique_module(side_manager.get_side(), iseg),
(nx + 1) * (ny + 1) );
}
}
@ -1247,10 +1249,10 @@ DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* s
for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) {
RRSwitchBlock rr_sb = LL_device_rr_switch_block.get_switch_block(ix, iy);
RRSwitchBlock rotated_rr_sb = rotate_rr_switch_block_for_mirror(sb_range, rr_sb);
RRGSB rr_sb = LL_drive_rr_gsb.get_switch_block(ix, iy);
RRGSB rotated_rr_sb = rotate_rr_switch_block_for_mirror(sb_range, rr_sb);
DeviceCoordinator sb_coordinator = rr_sb.get_coordinator();
LL_device_rr_switch_block.add_rotatable_mirror(sb_coordinator, rotated_rr_sb);
LL_drive_rr_gsb.add_rotatable_mirror(sb_coordinator, rotated_rr_sb);
if (TRUE == output_sb_xml) {
std::string fname_prefix(sb_xml_dir);
@ -1267,9 +1269,9 @@ DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* s
/* Skip rotating mirror searching */
vpr_printf(TIO_MESSAGE_INFO,
"Detect %d rotatable unique switch blocks from %d switch blocks.\n",
LL_device_rr_switch_block.get_num_rotatable_mirror(), (nx + 1) * (ny + 1) );
LL_drive_rr_gsb.get_num_rotatable_mirror(), (nx + 1) * (ny + 1) );
return LL_device_rr_switch_block;
return LL_drive_rr_gsb;
}

8
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h
View File

@ -14,10 +14,10 @@ DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node,
* Each switch block in the FPGA fabric will be an instance of these modules.
* We maintain a map from each instance to each module
*/
DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* sb_xml_dir,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices, int num_segments,
t_rr_indexed_data* LL_rr_indexed_data);
DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices, int num_segments,
t_rr_indexed_data* LL_rr_indexed_data);
/* Rotatable will be done in the next step
identify_rotatable_switch_blocks();

344
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp
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File diff suppressed because it is too large Load Diff

60
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h
View File

@ -129,10 +129,10 @@ class DeviceRRChan {
* num_reserved_conf_bits: number of reserved configuration bits this switch block requires (mainly due to RRAM-based multiplexers)
* num_conf_bits: number of configuration bits this switch block requires
*/
class RRSwitchBlock {
class RRGSB {
public: /* Contructors */
RRSwitchBlock(const RRSwitchBlock&);/* Copy constructor */
RRSwitchBlock();/* Default constructor */
RRGSB(const RRGSB&);/* Copy constructor */
RRGSB();/* Default constructor */
public: /* Accessors */
size_t get_x() const; /* get the x coordinator of this switch block */
size_t get_y() const; /* get the y coordinator of this switch block */
@ -162,11 +162,11 @@ class RRSwitchBlock {
size_t get_conf_bits_lsb() const;
size_t get_conf_bits_msb() const;
bool is_node_imply_short_connection(t_rr_node* src_node) const; /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */
bool is_side_mirror(RRSwitchBlock& cand, enum e_side side) const; /* check if a side of candidate SB is a mirror of the current one */
bool is_side_segment_mirror(RRSwitchBlock& cand, enum e_side side, size_t seg_id) const; /* check if all the routing segments of a side of candidate SB is a mirror of the current one */
bool is_mirror(RRSwitchBlock& cand) const; /* check if the candidate SB is a mirror of the current one */
bool is_mirrorable(RRSwitchBlock& cand) const; /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */
size_t get_hint_rotate_offset(RRSwitchBlock& cand) const; /* Determine an initial offset in rotating the candidate Switch Block to find a mirror matching*/
bool is_side_mirror(RRGSB& cand, enum e_side side) const; /* check if a side of candidate SB is a mirror of the current one */
bool is_side_segment_mirror(RRGSB& cand, enum e_side side, size_t seg_id) const; /* check if all the routing segments of a side of candidate SB is a mirror of the current one */
bool is_mirror(RRGSB& cand) const; /* check if the candidate SB is a mirror of the current one */
bool is_mirrorable(RRGSB& cand) const; /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */
size_t get_hint_rotate_offset(RRGSB& cand) const; /* Determine an initial offset in rotating the candidate Switch Block to find a mirror matching*/
public: /* Cooridinator conversion */
DeviceCoordinator get_side_block_coordinator(enum e_side side) const;
public: /* Verilog writer */
@ -175,7 +175,7 @@ class RRSwitchBlock {
char* gen_verilog_side_module_name(enum e_side side, size_t seg_id) const;
char* gen_verilog_side_instance_name(enum e_side side, size_t seg_id) const;
public: /* Mutators */
void set(const RRSwitchBlock& src); /* get a copy from a source */
void set(const RRGSB& src); /* get a copy from a source */
void set_coordinator(size_t x, size_t y);
void init_num_sides(size_t num_sides); /* Allocate the vectors with the given number of sides */
void add_chan_node(enum e_side node_side, RRChan& rr_chan, std::vector<enum PORTS> rr_chan_dir); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
@ -206,7 +206,7 @@ class RRSwitchBlock {
private: /* Internal Mutators */
void mirror_side_chan_node_direction(enum e_side side); /* Mirror the node direction and port direction of routing track nodes on a side */
private: /* internal functions */
bool is_node_mirror (RRSwitchBlock& cand, enum e_side node_side, size_t track_id) const;
bool is_node_mirror (RRGSB& cand, enum e_side node_side, size_t track_id) const;
size_t get_track_id_first_short_connection(enum e_side node_side) const;
bool validate_num_sides() const;
bool validate_side(enum e_side side) const;
@ -232,40 +232,40 @@ class RRSwitchBlock {
/* Object Device Routing Resource Switch Block
* This includes:
* 1. a collection of RRSwitch blocks, each of which can be used to instance Switch blocks in the top-level netlists
* 2. a collection of unique mirrors of RRSwitchBlocks, which can be used to output Verilog / SPICE modules
* 3. a colleciton of unique rotatable of RRSwitchBlocks, which can be used to output Verilog / SPICE modules
* The rotatable RRSwitchBlocks are more generic mirrors, which allow SwitchBlocks to be wired by rotating the pins,
* 2. a collection of unique mirrors of RRGSBs, which can be used to output Verilog / SPICE modules
* 3. a colleciton of unique rotatable of RRGSBs, which can be used to output Verilog / SPICE modules
* The rotatable RRGSBs are more generic mirrors, which allow SwitchBlocks to be wired by rotating the pins,
* further reduce the number of Verilog/SPICE modules outputted. This will lead to rapid layout generation
*/
class DeviceRRSwitchBlock {
class DeviceRRGSB {
public: /* Contructors */
public: /* Accessors */
DeviceCoordinator get_switch_block_range() const; /* get the max coordinator of the switch block array */
RRSwitchBlock get_switch_block(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */
RRSwitchBlock get_switch_block(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */
RRGSB get_switch_block(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */
RRGSB get_switch_block(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */
size_t get_num_unique_module(enum e_side side, size_t seg_index) const; /* get the number of unique mirrors of switch blocks */
size_t get_num_unique_mirror() const; /* get the number of unique mirrors of switch blocks */
size_t get_num_rotatable_mirror() const; /* get the number of rotatable mirrors of switch blocks */
RRSwitchBlock get_unique_side_module(size_t index, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */
RRSwitchBlock get_unique_mirror(size_t index) const; /* Get a rr switch block which a unique mirror */
RRSwitchBlock get_unique_mirror(DeviceCoordinator& coordinator) const; /* Get a rr switch block which a unique mirror */
RRSwitchBlock get_rotatable_mirror(size_t index) const; /* Get a rr switch block which a unique mirror */
RRGSB get_unique_side_module(size_t index, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */
RRGSB get_unique_mirror(size_t index) const; /* Get a rr switch block which a unique mirror */
RRGSB get_unique_mirror(DeviceCoordinator& coordinator) const; /* Get a rr switch block which a unique mirror */
RRGSB get_rotatable_mirror(size_t index) const; /* Get a rr switch block which a unique mirror */
size_t get_max_num_sides() const; /* Get the maximum number of sides across the switch blocks */
size_t get_num_segments() const; /* Get the size of segment_ids */
size_t get_segment_id(size_t index) const; /* Get a segment id */
public: /* Mutators */
void set_rr_switch_block_num_reserved_conf_bits(DeviceCoordinator& coordinator, size_t num_reserved_conf_bits); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
void set_rr_switch_block_conf_bits_lsb(DeviceCoordinator& coordinator, size_t conf_bits_lsb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
void set_rr_switch_block_conf_bits_msb(DeviceCoordinator& coordinator, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
void set_sb_num_reserved_conf_bits(DeviceCoordinator& coordinator, size_t num_reserved_conf_bits); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
void set_sb_conf_bits_lsb(DeviceCoordinator& coordinator, size_t conf_bits_lsb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
void set_sb_conf_bits_msb(DeviceCoordinator& coordinator, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
void reserve(DeviceCoordinator& coordinator); /* Pre-allocate the rr_switch_block array that the device requires */
void reserve_unique_module_id(DeviceCoordinator& coordinator); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */
void resize_upon_need(DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */
void add_rr_switch_block(DeviceCoordinator& coordinator, RRSwitchBlock& rr_sb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void add_rr_switch_block(DeviceCoordinator& coordinator, RRGSB& rr_sb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void build_unique_mirror(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void build_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */
void add_rotatable_mirror(DeviceCoordinator& coordinator, RRSwitchBlock& rr_sb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void add_unique_side_segment_module(DeviceCoordinator& coordinator, RRSwitchBlock& rr_sb, enum e_side side, size_t seg_id);
void add_unique_side_module(DeviceCoordinator& coordinator, RRSwitchBlock& rr_sb, enum e_side side);
void add_rotatable_mirror(DeviceCoordinator& coordinator, RRGSB& rr_sb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void add_unique_side_segment_module(DeviceCoordinator& coordinator, RRGSB& rr_sb, enum e_side side, size_t seg_id);
void add_unique_side_module(DeviceCoordinator& coordinator, RRGSB& rr_sb, enum e_side side);
void build_segment_ids(); /* build a map of segment_ids */
void clear(); /* clean the content */
void clear_unique_module(); /* clean the content */
@ -280,14 +280,14 @@ class DeviceRRSwitchBlock {
bool validate_unique_module_index(size_t index, enum e_side side, size_t seg_index) const; /* Validate if the index in the range of unique_module vector */
bool validate_segment_index(size_t index) const;
private: /* Internal Data */
std::vector< std::vector<RRSwitchBlock> > rr_switch_block_;
std::vector< std::vector<RRGSB> > rr_gsb;
std::vector< std::vector< std::vector< std::vector<size_t> > > > rr_sb_unique_module_id_; /* A map from rr_switch_block to its unique_side_module [0..x][0..y][0..num_sides][num_seg-1]*/
std::vector< std::vector <std::vector<DeviceCoordinator> > > unique_module_; /* For each side of switch block, we identify a list of unique modules based on its connection. This is a matrix [0..num_sides-1][0..num_seg-1][0..num_module], num_sides will the max number of sides of all the rr_switch_blocks */
std::vector< std::vector<size_t> > rr_switch_block_mirror_id_; /* A map from rr_switch_block to its unique mirror */
std::vector< std::vector<size_t> > rr_gsbmirror_id_; /* A map from rr_switch_block to its unique mirror */
std::vector<DeviceCoordinator> unique_mirror_;
std::vector< std::vector<size_t> > rr_switch_block_rotatable_mirror_id_; /* A map from rr_switch_block to its unique mirror */
std::vector< std::vector<size_t> > rr_gsbrotatable_mirror_id_; /* A map from rr_switch_block to its unique mirror */
std::vector<DeviceCoordinator> rotatable_mirror_;
std::vector<size_t> segment_ids_;

10
vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.cpp
View File

@ -10,7 +10,7 @@
#include "fpga_x2p_utils.h"
void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb) {
void write_rr_switch_block_to_xml(std::string fname_prefix, RRGSB& rr_sb) {
/* Prepare file name */
std::string fname(fname_prefix);
fname += rr_sb.gen_verilog_module_name();
@ -116,20 +116,20 @@ void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb
}
/* Output each rr_switch_block to a XML file */
void write_device_rr_switch_block_to_xml(char* sb_xml_dir,
DeviceRRSwitchBlock& LL_device_rr_switch_block) {
void write_device_rr_gsb_to_xml(char* sb_xml_dir,
DeviceRRGSB& LL_device_rr_gsb) {
std::string fname_prefix(sb_xml_dir);
/* Add slash if needed */
if ('/' != fname_prefix.back()) {
fname_prefix += '/';
}
DeviceCoordinator sb_range = LL_device_rr_switch_block.get_switch_block_range();
DeviceCoordinator sb_range = LL_device_rr_gsb.get_switch_block_range();
/* For each switch block, an XML file will be outputted */
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRSwitchBlock rr_sb = LL_device_rr_switch_block.get_switch_block(ix, iy);
RRGSB rr_sb = LL_device_rr_gsb.get_switch_block(ix, iy);
write_rr_switch_block_to_xml(fname_prefix, rr_sb);
}
}

4
vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.h
View File

@ -1,8 +1,8 @@
#ifndef WRITE_RR_BLOCKS_H
#define WRITE_RR_BLOCKS_H
void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb);
void write_rr_switch_block_to_xml(std::string fname_prefix, RRGSB& rr_sb);
void write_device_rr_switch_block_to_xml(char* sb_xml_dir, DeviceRRSwitchBlock& LL_device_rr_switch_block);
void write_device_rr_gsb_to_xml(char* sb_xml_dir, DeviceRRGSB& LL_device_rr_gsb);
#endif

10
vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c
View File

@ -36,7 +36,7 @@
/* Generate bitstream for a multiplexer of a switch block */
static
void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* cur_rr_node,
int mux_size,
@ -211,7 +211,7 @@ void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp,
static
void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_sram_orgz_info* cur_sram_orgz_info,
enum e_side chan_side,
t_rr_node* cur_rr_node) {
@ -342,7 +342,7 @@ void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp,
*/
static
void fpga_spice_generate_bitstream_routing_switch_box_subckt(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_sram_orgz_info* cur_sram_orgz_info) {
/* Check */
/* Check the file handler*/
@ -675,10 +675,10 @@ void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log
/* Switch Boxes*/
vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Switch blocks...\n");
if (TRUE == compact_routing_hierarchy) {
DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
fpga_spice_generate_bitstream_routing_switch_box_subckt(fp,
rr_sb, cur_sram_orgz_info);
}

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -749,7 +749,7 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
static
void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
RRSwitchBlock& rr_sb) {
RRGSB& rr_sb) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -766,7 +766,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
/* If we have an mirror SB, we should the module name of the mirror !!! */
DeviceCoordinator coordinator = rr_sb.get_coordinator();
RRSwitchBlock unique_mirror = device_rr_switch_block.get_unique_mirror(coordinator);
RRGSB unique_mirror = device_rr_gsb.get_unique_mirror(coordinator);
fprintf(fp, "%s ", unique_mirror.gen_verilog_module_name());
fprintf(fp, "%s ", rr_sb.gen_verilog_instance_name());
fprintf(fp, "(");
@ -850,7 +850,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
static
void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
/* Check the file handler*/
if (NULL == fp) {
@ -861,7 +861,7 @@ void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_i
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, rr_sb);
}
}

70
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c
View File

@ -245,7 +245,7 @@ void free_wire_L_llist(t_llist* rr_path_cnt) {
*/
static
void verilog_generate_one_report_timing_within_sb(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node) {
/* Check the file handler */
@ -371,7 +371,7 @@ void verilog_generate_one_report_timing_sb_to_cb(FILE* fp,
*/
static
void verilog_generate_one_report_timing_sb_to_cb(FILE* fp,
RRSwitchBlock& src_sb,
RRGSB& src_sb,
t_rr_node* src_rr_node,
t_cb* des_cb_info,
t_rr_node* des_rr_node) {
@ -413,9 +413,9 @@ void verilog_generate_one_report_timing_sb_to_cb(FILE* fp,
*/
static
void verilog_generate_one_report_timing_sb_to_sb(FILE* fp,
RRSwitchBlock& src_sb,
RRGSB& src_sb,
t_rr_node* src_rr_node,
RRSwitchBlock& des_sb,
RRGSB& des_sb,
t_rr_node* des_rr_node) {
/* Check the file handler */
if (NULL == fp) {
@ -597,9 +597,9 @@ void build_ending_rr_node_for_one_sb_wire(t_rr_node* wire_rr_node,
*/
static
void verilog_generate_report_timing_one_sb_thru_segments(FILE* fp,
RRSwitchBlock src_sb,
RRGSB src_sb,
t_rr_node* src_rr_node,
RRSwitchBlock des_sb,
RRGSB des_sb,
t_rr_node* des_rr_node,
char* rpt_name) {
/* Check the file handler */
@ -692,13 +692,13 @@ void verilog_generate_report_timing_one_sb_thru_segments(FILE* fp,
*/
static
void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp,
RRSwitchBlock& src_sb,
RRGSB& src_sb,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node,
char* rpt_name) {
t_cb* next_cb = NULL;
DeviceCoordinator next_sb_coordinator;
RRSwitchBlock next_sb;
RRGSB next_sb;
/* Check the file handler */
if (NULL == fp) {
@ -719,7 +719,7 @@ void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp,
case CHANY:
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_switch_block.get_switch_block(next_sb_coordinator);
next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator);
verilog_generate_one_report_timing_sb_to_sb(fp, src_sb, src_rr_node,
next_sb, src_rr_node);
break;
@ -801,7 +801,7 @@ void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp,
static
void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
t_syn_verilog_opts fpga_verilog_opts,
RRSwitchBlock& src_sb,
RRGSB& src_sb,
t_rr_node* drive_rr_node,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node,
@ -812,7 +812,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
t_cb* next_cb = NULL;
char* rpt_name = NULL;
DeviceCoordinator next_sb_coordinator;
RRSwitchBlock next_sb;
RRGSB next_sb;
/* Check the file handler */
if (NULL == fp) {
@ -947,7 +947,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
case CHANY:
/* Get the coordinate of ending CB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_switch_block.get_switch_block(next_sb_coordinator);
next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator);
end_sb_x = next_sb.get_x();
end_sb_y = next_sb.get_y();
break;
@ -966,7 +966,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
/* Follow the graph above, go through X channel */
for (int ix = src_sb.get_x(); ix < end_sb_x; ix++) {
DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y);
RRSwitchBlock begin_sb = device_rr_switch_block.get_switch_block(begin_sb_coordinator);
RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator);
/* If this is the ending point, we add a ending segment */
if (ix == end_sb_x - 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
@ -978,7 +978,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
DeviceCoordinator end_sb_coordinator(ix + 1, cur_sb_y);
RRSwitchBlock end_sb = device_rr_switch_block.get_switch_block(end_sb_coordinator);
RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator);
verilog_generate_report_timing_one_sb_thru_segments(fp,
begin_sb, src_rr_node,
end_sb, src_rr_node,
@ -989,7 +989,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
/* Follow the graph above, go through Y channel */
for (int iy = src_sb.get_y(); iy < end_sb_y; iy++) {
DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy);
RRSwitchBlock begin_sb = device_rr_switch_block.get_switch_block(begin_sb_coordinator);
RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator);
/* If this is the ending point, we add a ending segment */
if (iy == end_sb_y - 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
@ -1000,7 +1000,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
DeviceCoordinator end_sb_coordinator(cur_sb_x, iy + 1);
RRSwitchBlock end_sb = device_rr_switch_block.get_switch_block(end_sb_coordinator);
RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator);
verilog_generate_report_timing_one_sb_thru_segments(fp,
begin_sb, src_rr_node,
end_sb, src_rr_node,
@ -1011,7 +1011,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
/* Follow the graph above, go through X channel */
for (int ix = src_sb.get_x() - 1; ix > end_sb_x; ix--) {
DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y);
RRSwitchBlock begin_sb = device_rr_switch_block.get_switch_block(begin_sb_coordinator);
RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator);
/* If this is the ending point, we add a ending segment */
if (ix == end_sb_x + 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
@ -1022,7 +1022,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
DeviceCoordinator end_sb_coordinator(ix - 1, cur_sb_y);
RRSwitchBlock end_sb = device_rr_switch_block.get_switch_block(end_sb_coordinator);
RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator);
verilog_generate_report_timing_one_sb_thru_segments(fp,
begin_sb, src_rr_node,
end_sb, src_rr_node,
@ -1033,7 +1033,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
/* Follow the graph above, go through Y channel */
for (int iy = src_sb.get_y() - 1; iy > end_sb_y; iy--) {
DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy);
RRSwitchBlock begin_sb = device_rr_switch_block.get_switch_block(begin_sb_coordinator);
RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator);
/* If this is the ending point, we add a ending segment */
if (iy == end_sb_y + 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
@ -1044,7 +1044,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
DeviceCoordinator end_sb_coordinator(cur_sb_x, iy - 1);
RRSwitchBlock end_sb = device_rr_switch_block.get_switch_block(end_sb_coordinator);
RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator);
verilog_generate_report_timing_one_sb_thru_segments(fp,
begin_sb, src_rr_node,
end_sb, src_rr_node,
@ -1310,14 +1310,14 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
*/
static
void dump_verilog_sb_through_routing_pins(FILE* fp,
RRSwitchBlock& src_rr_sb,
RRGSB& src_rr_sb,
t_rr_node* src_rr_node,
t_rr_node* des_rr_node) {
size_t cur_sb_x, cur_sb_y;
size_t end_sb_x, end_sb_y;
t_cb* next_cb;
DeviceCoordinator next_sb_coordinator;
RRSwitchBlock next_sb;
RRGSB next_sb;
/* Check the file handler */
if (NULL == fp) {
@ -1432,7 +1432,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
case CHANY:
/* Get the coordinate of ending CB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_switch_block.get_switch_block(next_sb_coordinator);
next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator);
end_sb_x = next_sb.get_x();
end_sb_y = next_sb.get_y();
break;
@ -1454,7 +1454,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(ix, cur_sb_y);
RRSwitchBlock inter_sb = device_rr_switch_block.get_switch_block(inter_sb_coordinator);
RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -1473,7 +1473,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(cur_sb_x, iy);
RRSwitchBlock inter_sb = device_rr_switch_block.get_switch_block(inter_sb_coordinator);
RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -1492,7 +1492,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(ix, cur_sb_y);
RRSwitchBlock inter_sb = device_rr_switch_block.get_switch_block(inter_sb_coordinator);
RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -1511,7 +1511,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(cur_sb_x, iy);
RRSwitchBlock inter_sb = device_rr_switch_block.get_switch_block(inter_sb_coordinator);
RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
@ -1751,7 +1751,7 @@ static
void verilog_generate_one_routing_wire_report_timing(FILE* fp,
t_trpt_opts sdc_opts,
int L_wire,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_rr_node* wire_rr_node,
t_rr_node* LL_rr_node) {
int path_cnt = 0;
@ -1784,7 +1784,7 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
DeviceCoordinator next_sb_coordinator;
/* Reciever could be IPIN or CHANX or CHANY */
int inode = wire_rr_node->edges[jedge];
RRSwitchBlock next_sb;
RRGSB next_sb;
t_cb* next_cb = NULL;
/* Find the SB/CB block that it belongs to */
switch (LL_rr_node[inode].type) {
@ -1831,7 +1831,7 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
case CHANY:
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(wire_rr_node, &(LL_rr_node[inode]));
next_sb = device_rr_switch_block.get_switch_block(next_sb_coordinator);
next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator);
/* This will not be the longest path unless the cb is close to the ending SB */
if ((TRUE == sdc_opts.longest_path_only)
&& ((next_sb.get_x() != (size_t)x_end) || (next_sb.get_y() != (size_t)y_end))) {
@ -2055,10 +2055,10 @@ void verilog_generate_routing_wires_report_timing(FILE* fp,
}
if (TRUE == sdc_opts.compact_routing_hierarchy) {
DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
for (size_t side = 0; side < rr_sb.get_num_sides(); side++) {
Side side_manager(side);
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {
@ -2195,7 +2195,7 @@ void verilog_generate_sb_report_timing(t_trpt_opts sdc_opts,
static
void verilog_generate_one_routing_segmental_report_timing(FILE* fp,
t_syn_verilog_opts fpga_verilog_opts,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_rr_node* wire_rr_node,
t_rr_node* LL_rr_node,
int* path_cnt) {
@ -2386,10 +2386,10 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts,
"Generating TCL script to report timing for routing wires\n");
/* We start from a SB[x][y] */
DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
Side side_manager(side);
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {

54
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -661,7 +661,7 @@ void dump_verilog_switch_box_chan_port(FILE* fp,
static
void dump_verilog_unique_switch_box_chan_port(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
enum e_side chan_side,
t_rr_node* cur_rr_node,
enum PORTS cur_rr_node_direction) {
@ -703,7 +703,7 @@ void dump_verilog_unique_switch_box_chan_port(FILE* fp,
*/
static
void dump_verilog_unique_switch_box_short_interc(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
enum e_side chan_side,
t_rr_node* cur_rr_node,
int actual_fan_in,
@ -1134,7 +1134,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
static
void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
enum e_side chan_side,
t_rr_node* cur_rr_node,
int mux_size,
@ -1410,7 +1410,7 @@ int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_in
/* Count the number of configuration bits of a rr_node*/
static
size_t count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRSwitchBlock& rr_sb, enum e_side chan_side,
RRGSB& rr_sb, enum e_side chan_side,
t_rr_node* cur_rr_node) {
size_t num_conf_bits = 0;
int switch_idx = 0;
@ -1485,7 +1485,7 @@ int count_verilog_switch_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sra
/* Count the number of reserved configuration bits of a rr_node*/
static
size_t count_verilog_switch_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRSwitchBlock& rr_sb, enum e_side chan_side,
RRGSB& rr_sb, enum e_side chan_side,
t_rr_node* cur_rr_node) {
size_t num_reserved_conf_bits = 0;
int switch_idx = 0;
@ -1578,7 +1578,7 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
static
void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
enum e_side chan_side,
t_rr_node* cur_rr_node) {
int num_drive_rr_nodes = 0;
@ -1660,7 +1660,7 @@ int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_
/* Count the number of configuration bits of a Switch Box */
static
size_t count_verilog_switch_box_side_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRSwitchBlock& rr_sb, enum e_side side, size_t seg_id) {
RRGSB& rr_sb, enum e_side side, size_t seg_id) {
size_t num_reserved_conf_bits = 0;
size_t temp_num_reserved_conf_bits = 0;
Side side_manager(side);
@ -1695,7 +1695,7 @@ size_t count_verilog_switch_box_side_reserved_conf_bits(t_sram_orgz_info* cur_sr
/* Count the number of configuration bits of a Switch Box */
static
size_t count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRSwitchBlock& rr_sb) {
RRGSB& rr_sb) {
size_t num_reserved_conf_bits = 0;
size_t temp_num_reserved_conf_bits = 0;
@ -1744,7 +1744,7 @@ int count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
/* Count the number of configuration bits of a Switch Box */
static
size_t count_verilog_switch_box_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
enum e_side side, size_t seg_id) {
size_t num_conf_bits = 0;
Side side_manager(side);
@ -1775,7 +1775,7 @@ size_t count_verilog_switch_box_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_i
/* Count the number of configuration bits of a Switch Box */
static
size_t count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRSwitchBlock& rr_sb) {
RRGSB& rr_sb) {
size_t num_conf_bits = 0;
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
@ -1792,7 +1792,7 @@ size_t count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
static
void update_routing_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
RRSwitchBlock& rr_sb) {
RRGSB& rr_sb) {
int cur_num_bl, cur_num_wl;
get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_num_bl, &cur_num_wl);
@ -1807,9 +1807,9 @@ void update_routing_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
/* Estimate the sram_verilog_model->cnt */
int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
device_rr_switch_block.set_rr_switch_block_num_reserved_conf_bits(sb_coordinator, num_reserved_conf_bits);
device_rr_switch_block.set_rr_switch_block_conf_bits_lsb(sb_coordinator, cur_num_sram);
device_rr_switch_block.set_rr_switch_block_conf_bits_msb(sb_coordinator, cur_num_sram + num_conf_bits - 1);
device_rr_gsb.set_sb_num_reserved_conf_bits(sb_coordinator, num_reserved_conf_bits);
device_rr_gsb.set_sb_conf_bits_lsb(sb_coordinator, cur_num_sram);
device_rr_gsb.set_sb_conf_bits_msb(sb_coordinator, cur_num_sram + num_conf_bits - 1);
/* Update the counter */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_conf_bits);
@ -1824,7 +1824,7 @@ void update_routing_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
*/
static
void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
enum e_side sb_side,
size_t seg_id,
boolean dump_port_type) {
@ -1946,7 +1946,7 @@ static
void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
size_t module_id, size_t seg_id,
RRSwitchBlock& rr_sb, enum e_side side) {
RRGSB& rr_sb, enum e_side side) {
FILE* fp = NULL;
char* fname = NULL;
Side side_manager(side);
@ -2092,7 +2092,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
static
void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
RRSwitchBlock& rr_sb) {
RRGSB& rr_sb) {
FILE* fp = NULL;
char* fname = NULL;
@ -2333,7 +2333,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
static
void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
RRSwitchBlock& rr_sb) {
RRGSB& rr_sb) {
FILE* fp = NULL;
char* fname = NULL;
@ -3453,30 +3453,30 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
t_sram_orgz_info* stamped_sram_orgz_info = snapshot_sram_orgz_info(cur_sram_orgz_info);
/* Output unique side modules */
for (size_t side = 0; side < device_rr_switch_block.get_max_num_sides(); ++side) {
for (size_t side = 0; side < device_rr_gsb.get_max_num_sides(); ++side) {
Side side_manager(side);
for (size_t iseg = 0; iseg < device_rr_switch_block.get_num_segments(); ++iseg) {
for (size_t isb = 0; isb < device_rr_switch_block.get_num_unique_module(side_manager.get_side(), iseg); ++isb) {
RRSwitchBlock unique_mirror = device_rr_switch_block.get_unique_side_module(isb, side_manager.get_side(), iseg);
size_t seg_id = device_rr_switch_block.get_segment_id(iseg);
for (size_t iseg = 0; iseg < device_rr_gsb.get_num_segments(); ++iseg) {
for (size_t isb = 0; isb < device_rr_gsb.get_num_unique_module(side_manager.get_side(), iseg); ++isb) {
RRGSB unique_mirror = device_rr_gsb.get_unique_side_module(isb, side_manager.get_side(), iseg);
size_t seg_id = device_rr_gsb.get_segment_id(iseg);
dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side());
}
}
}
/* Output unique modules */
for (size_t isb = 0; isb < device_rr_switch_block.get_num_unique_mirror(); ++isb) {
RRSwitchBlock unique_mirror = device_rr_switch_block.get_unique_mirror(isb);
for (size_t isb = 0; isb < device_rr_gsb.get_num_unique_mirror(); ++isb) {
RRGSB unique_mirror = device_rr_gsb.get_unique_mirror(isb);
dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror);
}
/* Restore sram_orgz_info to the base */
copy_sram_orgz_info (cur_sram_orgz_info, stamped_sram_orgz_info);
DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
update_routing_switch_box_conf_bits(cur_sram_orgz_info, rr_sb);
}
}

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -1011,11 +1011,11 @@ void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp) {
exit(1);
}
DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
/* Print comments */
fprintf(fp,
"########################################################\n");
@ -1167,11 +1167,11 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp) {
exit(1);
}
DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
/* We start from a SB[x][y] */
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
/* Print comments */
fprintf(fp,
"##################################################\n");

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c
View File

@ -60,7 +60,7 @@ void dump_verilog_sdc_file_header(FILE* fp,
}
void dump_verilog_one_sb_chan_pin(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_rr_node* cur_rr_node,
enum PORTS port_type) {
int track_idx;
@ -135,7 +135,7 @@ void dump_verilog_one_sb_chan_pin(FILE* fp,
/* Output the pin name of a routing wire in a SB */
void dump_verilog_one_sb_routing_pin(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_rr_node* cur_rr_node) {
int side;
@ -398,7 +398,7 @@ DeviceCoordinator get_chan_node_ending_sb_coordinator(t_rr_node* src_rr_node,
}
DeviceCoordinator sb_coordinator(next_sb_x, next_sb_y);
RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(sb_coordinator);
RRGSB rr_sb = device_rr_gsb.get_switch_block(sb_coordinator);
/* Double check if src_rr_node is in the list */
enum e_side side;
int index;
@ -552,7 +552,7 @@ t_sb* get_chan_rr_node_ending_sb(t_rr_node* src_rr_node,
/* Restore the disabled timing for the sb wire */
void restore_disable_timing_one_sb_output(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_rr_node* wire_rr_node) {
/* Check the file handler */
if (NULL == fp) {
@ -604,7 +604,7 @@ void restore_disable_timing_one_sb_output(FILE* fp,
/* Restore the disabled timing for the sb wire */
void set_disable_timing_one_sb_output(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_rr_node* wire_rr_node) {
/* Check the file handler */
if (NULL == fp) {

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h
View File

@ -9,7 +9,7 @@ void dump_verilog_sdc_file_header(FILE* fp,
char* usage);
void dump_verilog_one_sb_chan_pin(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_rr_node* cur_rr_node,
enum PORTS port_type);
@ -19,7 +19,7 @@ void dump_verilog_one_sb_chan_pin(FILE* fp,
enum PORTS port_type);
void dump_verilog_one_sb_routing_pin(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_rr_node* cur_rr_node);
void dump_verilog_one_sb_routing_pin(FILE* fp,
@ -36,7 +36,7 @@ t_sb* get_chan_rr_node_ending_sb(t_rr_node* src_rr_node,
t_rr_node* end_rr_node);
void restore_disable_timing_one_sb_output(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_rr_node* wire_rr_node);
void restore_disable_timing_one_sb_output(FILE* fp,
@ -44,7 +44,7 @@ void restore_disable_timing_one_sb_output(FILE* fp,
t_rr_node* wire_rr_node);
void set_disable_timing_one_sb_output(FILE* fp,
RRSwitchBlock& rr_sb,
RRGSB& rr_sb,
t_rr_node* wire_rr_node);
void set_disable_timing_one_sb_output(FILE* fp,

4
vpr7_x2p/vpr/go_fpga_verilog.sh
View File

@ -39,8 +39,8 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname\_compact
# Run VPR
#valgrind
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl
echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl"
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname\_compact --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl
echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname\_compact --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl"