diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index a9278760c..858607a58 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -30,6 +30,8 @@ #include "verilog_api.h" #include "fpga_bitstream.h" +#include "fpga_x2p_api.h" + /* Top-level API of FPGA-SPICE */ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, t_arch Arch) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.h index 898344745..28d0e65d2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.h @@ -1,5 +1,8 @@ - +#ifndef FPGA_X2P_API_H +#define FPGA_X2P_API_H void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, t_arch Arch); +#endif + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c index 304cb8c59..d72b582af 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c @@ -38,6 +38,8 @@ #include "fpga_x2p_router.h" #include "fpga_x2p_unique_routing.h" +#include "fpga_x2p_backannotate_utils.h" + /* Get initial value of a Latch/FF output*/ int get_ff_output_init_val(t_logical_block* ff_logical_block) { assert((0 == ff_logical_block->init_val)||(1 == ff_logical_block->init_val)); @@ -45,6 +47,7 @@ int get_ff_output_init_val(t_logical_block* ff_logical_block) { return ff_logical_block->init_val; } +static int determine_rr_node_default_prev_node(t_rr_node* cur_rr_node) { int default_prev_node = DEFAULT_PREV_NODE; @@ -653,6 +656,7 @@ void get_rr_node_side_and_index_in_cb_info(t_rr_node* cur_rr_node, /***** Recursively Backannotate parasitic_net_num for a rr_node*****/ +static void rec_backannotate_rr_node_net_num(int LL_num_rr_nodes, t_rr_node* LL_rr_node, int src_node_index) { @@ -1352,6 +1356,7 @@ void back_annotate_rr_node_map_info() { return; } +static void rec_sync_pb_post_routing_vpack_net_num(t_pb* cur_pb) { int ipb, jpb, select_mode_index; int iport, ipin, node_index; @@ -1423,6 +1428,7 @@ void rec_sync_pb_post_routing_vpack_net_num(t_pb* cur_pb) { * while the top-level type_descriptor consider 8 io in counting the pins * so we just update the vpack_net_num and net_num in all the hierachy level */ +static void update_one_io_grid_pack_net_num(int x, int y) { int iblk, blk_id; t_type_ptr type = NULL; @@ -1456,6 +1462,7 @@ void update_one_io_grid_pack_net_num(int x, int y) { * which potentially changes the packing results (net_num and vpack_net_num) in local routing * The following functions are to update the local routing results to match them with routing results */ +static void update_one_grid_pack_net_num(int x, int y) { int iblk, blk_id, ipin, iedge, jedge, inode; int pin_global_rr_node_id, vpack_net_id, class_id; @@ -1601,6 +1608,7 @@ void update_grid_pbs_post_route_rr_graph() { /* In this function, we update the vpack_net_num in global rr_graph * from the temp_net_num stored in the top_pb_graph_head */ +static void update_one_unused_grid_output_pins_parasitic_nets(int ix, int iy) { int iport, ipin; int pin_global_rr_node_id, class_id, type_pin_index; @@ -1651,6 +1659,7 @@ void update_one_unused_grid_output_pins_parasitic_nets(int ix, int iy) { * are absorbed into CLBs during packing, therefore they are invisible in * clb_nets. But indeed, they exist in global routing as parasitic nets. */ +static void update_one_used_grid_pb_pins_parasitic_nets(t_phy_pb* cur_pb, int ix, int iy) { int ipin, cur_pin; @@ -1715,6 +1724,7 @@ void update_one_used_grid_pb_pins_parasitic_nets(t_phy_pb* cur_pb, } +static void update_one_grid_pb_pins_parasitic_nets(int ix, int iy) { int iblk; @@ -1745,7 +1755,7 @@ void update_one_grid_pb_pins_parasitic_nets(int ix, int iy) { return; } - +static void update_grid_pb_pins_parasitic_nets() { int ix, iy; t_type_ptr type = NULL; @@ -2684,6 +2694,7 @@ void rec_annotate_pb_type_primitive_node_physical_mode_pin(t_pb_type* top_pb_typ /* Annotate the physical_mode_pin in pb_type ports, * Go recursively until we reach a primtiive node */ +static void rec_annotate_phy_pb_type_primitive_node_physical_mode_pin(t_pb_type* top_pb_type, t_pb_type* cur_pb_type) { int phy_mode_idx, ipb, iport; @@ -2740,6 +2751,7 @@ void rec_annotate_phy_pb_type_primitive_node_physical_mode_pin(t_pb_type* top_pb /* Go recursively visiting each primitive node in the pb_graph_node * Label the primitive node with a placement index which is unique at the top-level node */ +static void rec_mark_pb_graph_node_primitive_placement_index_in_top_node(t_pb_graph_node* cur_pb_graph_node) { int imode, ipb, jpb; t_pb_type* cur_pb_type = NULL; @@ -2928,6 +2940,7 @@ void alloc_and_load_phy_pb_for_mapped_block(int num_mapped_blocks, t_block* mapp * 4. Create the wired LUTs in logical block array * 5. Create new vpack nets to rewire the logical blocks */ +static void rec_backannotate_one_pb_wired_luts_and_adapt_graph(t_pb* cur_pb, int* L_num_logical_blocks, t_net** L_logical_block, int* L_num_vpack_nets, t_net** L_vpack_net) { @@ -3024,6 +3037,7 @@ void backannotate_pb_wired_luts(int num_mapped_blocks, t_block* mapped_block, return; } +static int find_matched_block_id_for_one_grid(int x, int y) { int iblk, jblk, blk_id; boolean already_exist = FALSE; @@ -3058,6 +3072,7 @@ int find_matched_block_id_for_one_grid(int x, int y) { /* Some IO blocks has an invalid BLOCK ID but with a >0 usage * We go through the block list and find the missing block ID */ +static void annotate_grid_block_info() { int ix, iy; t_type_ptr type = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h index 511b18d34..466f24bed 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h @@ -1,3 +1,5 @@ +#ifndef FPGA_X2P_BACKANNOTATE_UTILS_H +#define FPGA_X2P_BACKANNOTATE_UTILS_H int get_ff_output_init_val(t_logical_block* ff_logical_block); @@ -103,3 +105,4 @@ void spice_backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch, boolean read_activity_file, boolean parasitic_net_estimation); +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c index cc73027d3..400be99bc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c @@ -46,4 +46,4 @@ char* fpga_spice_bitstream_routing_log_file_postfix = "_routing_bitstream.log"; char* default_sdc_folder = "SDC/"; DeviceRRChan device_rr_chan; -DeviceRRSwitchBlock device_rr_switch_block; +DeviceRRGSB device_rr_gsb; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h index 8f39a70e9..7c36b917e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h @@ -41,6 +41,6 @@ extern char* fpga_spice_bitstream_logic_block_log_file_postfix; extern char* fpga_spice_bitstream_routing_log_file_postfix; extern DeviceRRChan device_rr_chan; -extern DeviceRRSwitchBlock device_rr_switch_block; +extern DeviceRRGSB device_rr_gsb; #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index 6f15433a0..98f52812b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -32,6 +32,7 @@ #include "fpga_x2p_pbtypes_utils.h" #include "verilog_api.h" #include "fpga_x2p_unique_routing.h" + #include "fpga_x2p_setup.h" /***** Subroutines Declarations *****/ @@ -1400,10 +1401,10 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup, /* Assign Gobal variable: build the Routing Resource Channels */ device_rr_chan = build_device_rr_chan(num_rr_nodes, rr_node, rr_node_indices, Arch->num_segments, rr_indexed_data); - device_rr_switch_block = build_device_rr_switch_blocks(vpr_setup.FPGA_SPICE_Opts.output_sb_xml, - vpr_setup.FPGA_SPICE_Opts.sb_xml_dir, - num_rr_nodes, rr_node, rr_node_indices, - Arch->num_segments, rr_indexed_data); + device_rr_gsb = build_device_rr_gsb(vpr_setup.FPGA_SPICE_Opts.output_sb_xml, + vpr_setup.FPGA_SPICE_Opts.sb_xml_dir, + num_rr_nodes, rr_node, rr_node_indices, + Arch->num_segments, rr_indexed_data); /* Rotatable will be done in the next step identify_rotatable_switch_blocks(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index c5e54391b..2834492e3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -799,13 +799,13 @@ DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node, * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs */ static -RRSwitchBlock build_rr_switch_block(DeviceCoordinator& device_range, +RRGSB build_rr_switch_block(DeviceCoordinator& device_range, size_t sb_x, size_t sb_y, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, int num_segments, t_rr_indexed_data* LL_rr_indexed_data) { /* Create an object to return */ - RRSwitchBlock rr_switch_block; + RRGSB rr_switch_block; /* Check */ assert(sb_x <= device_range.get_x()); @@ -1014,14 +1014,16 @@ RRSwitchBlock build_rr_switch_block(DeviceCoordinator& device_range, opin_grid_side[1] = NUM_SIDES; } + /* Build the connection block */ + return rr_switch_block; } /* Rotate the Switch block and try to add to rotatable mirrors */ static -RRSwitchBlock rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range, - const RRSwitchBlock& rr_switch_block) { - RRSwitchBlock rotated_rr_switch_block; +RRGSB rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range, + const RRGSB& rr_switch_block) { + RRGSB rotated_rr_switch_block; rotated_rr_switch_block.set(rr_switch_block); size_t Fco_offset = 1; @@ -1174,27 +1176,27 @@ RRSwitchBlock rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range, * Each switch block in the FPGA fabric will be an instance of these modules. * We maintain a map from each instance to each module */ -DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* sb_xml_dir, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, int num_segments, - t_rr_indexed_data* LL_rr_indexed_data) { +DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, int num_segments, + t_rr_indexed_data* LL_rr_indexed_data) { /* Create an object */ - DeviceRRSwitchBlock LL_device_rr_switch_block; + DeviceRRGSB LL_drive_rr_gsb; /* Initialize */ DeviceCoordinator sb_range((size_t)nx, (size_t)ny); DeviceCoordinator reserve_range((size_t)nx + 1, (size_t)ny + 1); - LL_device_rr_switch_block.reserve(reserve_range); + LL_drive_rr_gsb.reserve(reserve_range); /* For each switch block, determine the size of array */ for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) { for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) { - RRSwitchBlock rr_sb = build_rr_switch_block(sb_range, ix, iy, + RRGSB rr_sb = build_rr_switch_block(sb_range, ix, iy, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, num_segments, LL_rr_indexed_data); DeviceCoordinator sb_coordinator = rr_sb.get_coordinator(); - LL_device_rr_switch_block.add_rr_switch_block(sb_coordinator, rr_sb); + LL_drive_rr_gsb.add_rr_switch_block(sb_coordinator, rr_sb); } } /* Report number of unique mirrors */ @@ -1202,13 +1204,13 @@ DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* s "Backannotated %d switch blocks.\n", (nx + 1) * (ny + 1) ); - LL_device_rr_switch_block.build_segment_ids(); + LL_drive_rr_gsb.build_segment_ids(); vpr_printf(TIO_MESSAGE_INFO, "Detect %lu routing segments used by switch blocks.\n", - LL_device_rr_switch_block.get_num_segments()); + LL_drive_rr_gsb.get_num_segments()); if (TRUE == output_sb_xml) { - write_device_rr_switch_block_to_xml(sb_xml_dir, LL_device_rr_switch_block); + write_device_rr_gsb_to_xml(sb_xml_dir, LL_drive_rr_gsb); /* Skip rotating mirror searching */ vpr_printf(TIO_MESSAGE_INFO, @@ -1218,24 +1220,24 @@ DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* s } /* Build a list of unique modules for each Switch Block */ - LL_device_rr_switch_block.build_unique_mirror(); + LL_drive_rr_gsb.build_unique_mirror(); /* Report number of unique mirrors */ vpr_printf(TIO_MESSAGE_INFO, "Detect %d independent switch blocks from %d switch blocks.\n", - LL_device_rr_switch_block.get_num_unique_mirror(), (nx + 1) * (ny + 1) ); + LL_drive_rr_gsb.get_num_unique_mirror(), (nx + 1) * (ny + 1) ); /* Build a list of unique modules for each side of each Switch Block */ - LL_device_rr_switch_block.build_unique_module(); + LL_drive_rr_gsb.build_unique_module(); /* Report number of unique mirrors */ - for (size_t side = 0; side < LL_device_rr_switch_block.get_max_num_sides(); ++side) { + for (size_t side = 0; side < LL_drive_rr_gsb.get_max_num_sides(); ++side) { Side side_manager(side); /* get segment ids */ - for (size_t iseg = 0; iseg < LL_device_rr_switch_block.get_num_segments(); ++iseg) { + for (size_t iseg = 0; iseg < LL_drive_rr_gsb.get_num_segments(); ++iseg) { vpr_printf(TIO_MESSAGE_INFO, "For side %s, segment id %lu: Detect %d independent switch blocks from %d switch blocks.\n", - side_manager.to_string(), LL_device_rr_switch_block.get_segment_id(iseg), - LL_device_rr_switch_block.get_num_unique_module(side_manager.get_side(), iseg), + side_manager.to_string(), LL_drive_rr_gsb.get_segment_id(iseg), + LL_drive_rr_gsb.get_num_unique_module(side_manager.get_side(), iseg), (nx + 1) * (ny + 1) ); } } @@ -1247,10 +1249,10 @@ DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* s for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) { for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) { - RRSwitchBlock rr_sb = LL_device_rr_switch_block.get_switch_block(ix, iy); - RRSwitchBlock rotated_rr_sb = rotate_rr_switch_block_for_mirror(sb_range, rr_sb); + RRGSB rr_sb = LL_drive_rr_gsb.get_switch_block(ix, iy); + RRGSB rotated_rr_sb = rotate_rr_switch_block_for_mirror(sb_range, rr_sb); DeviceCoordinator sb_coordinator = rr_sb.get_coordinator(); - LL_device_rr_switch_block.add_rotatable_mirror(sb_coordinator, rotated_rr_sb); + LL_drive_rr_gsb.add_rotatable_mirror(sb_coordinator, rotated_rr_sb); if (TRUE == output_sb_xml) { std::string fname_prefix(sb_xml_dir); @@ -1267,9 +1269,9 @@ DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* s /* Skip rotating mirror searching */ vpr_printf(TIO_MESSAGE_INFO, "Detect %d rotatable unique switch blocks from %d switch blocks.\n", - LL_device_rr_switch_block.get_num_rotatable_mirror(), (nx + 1) * (ny + 1) ); + LL_drive_rr_gsb.get_num_rotatable_mirror(), (nx + 1) * (ny + 1) ); - return LL_device_rr_switch_block; + return LL_drive_rr_gsb; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h index 457e5c84e..e0df9c185 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h @@ -14,10 +14,10 @@ DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node, * Each switch block in the FPGA fabric will be an instance of these modules. * We maintain a map from each instance to each module */ -DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* sb_xml_dir, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, int num_segments, - t_rr_indexed_data* LL_rr_indexed_data); +DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, int num_segments, + t_rr_indexed_data* LL_rr_indexed_data); /* Rotatable will be done in the next step identify_rotatable_switch_blocks(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index 5e712987b..7dcffc452 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -500,9 +500,9 @@ bool DeviceRRChan::valid_module_id(t_rr_type chan_type, size_t module_id) const return false; } -/* Member Functions of Class RRSwitchBlock*/ +/* Member Functions of Class RRGSB*/ /* Constructor for an empty object */ -RRSwitchBlock::RRSwitchBlock() { +RRGSB::RRGSB() { /* Set a clean start! */ coordinator_.set(0, 0); chan_node_direction_.clear(); @@ -521,7 +521,7 @@ RRSwitchBlock::RRSwitchBlock() { } /* Copy constructor */ -RRSwitchBlock::RRSwitchBlock(const RRSwitchBlock& src) { +RRGSB::RRGSB(const RRGSB& src) { /* Copy coordinator */ this->set(src); return; @@ -530,35 +530,35 @@ RRSwitchBlock::RRSwitchBlock(const RRSwitchBlock& src) { /* Accessors */ /* get the x coordinator of this switch block */ -size_t RRSwitchBlock::get_x() const { +size_t RRGSB::get_x() const { return coordinator_.get_x(); } /* get the y coordinator of this switch block */ -size_t RRSwitchBlock::get_y() const { +size_t RRGSB::get_y() const { return coordinator_.get_y(); } /* Get the number of sides of this SB */ -DeviceCoordinator RRSwitchBlock::get_coordinator() const { +DeviceCoordinator RRGSB::get_coordinator() const { return coordinator_; } /* Get the number of sides of this SB */ -size_t RRSwitchBlock::get_num_sides() const { +size_t RRGSB::get_num_sides() const { assert (validate_num_sides()); return chan_node_direction_.size(); } /* Get the number of routing tracks on a side */ -size_t RRSwitchBlock::get_chan_width(enum e_side side) const { +size_t RRGSB::get_chan_width(enum e_side side) const { Side side_manager(side); assert(side_manager.validate()); return chan_node_[side_manager.to_size_t()].get_chan_width(); } /* Get the maximum number of routing tracks on all sides */ -size_t RRSwitchBlock::get_max_chan_width() const { +size_t RRGSB::get_max_chan_width() const { size_t max_chan_width = 0; for (size_t side = 0; side < get_num_sides(); ++side) { Side side_manager(side); @@ -568,7 +568,7 @@ size_t RRSwitchBlock::get_max_chan_width() const { } /* Get the direction of a rr_node at a given side and track_id */ -enum PORTS RRSwitchBlock::get_chan_node_direction(enum e_side side, size_t track_id) const { +enum PORTS RRGSB::get_chan_node_direction(enum e_side side, size_t track_id) const { Side side_manager(side); assert(side_manager.validate()); @@ -582,7 +582,7 @@ enum PORTS RRSwitchBlock::get_chan_node_direction(enum e_side side, size_t track } /* get a RRChan at a given side and track_id */ -RRChan RRSwitchBlock::get_chan(enum e_side side) const { +RRChan RRGSB::get_chan(enum e_side side) const { Side side_manager(side); assert(side_manager.validate()); @@ -593,7 +593,7 @@ RRChan RRSwitchBlock::get_chan(enum e_side side) const { } /* get a rr_node at a given side and track_id */ -t_rr_node* RRSwitchBlock::get_chan_node(enum e_side side, size_t track_id) const { +t_rr_node* RRGSB::get_chan_node(enum e_side side, size_t track_id) const { Side side_manager(side); assert(side_manager.validate()); @@ -607,7 +607,7 @@ t_rr_node* RRSwitchBlock::get_chan_node(enum e_side side, size_t track_id) const } /* get the segment id of a channel rr_node */ -size_t RRSwitchBlock::get_chan_node_segment(enum e_side side, size_t track_id) const { +size_t RRGSB::get_chan_node_segment(enum e_side side, size_t track_id) const { Side side_manager(side); assert(side_manager.validate()); @@ -622,14 +622,14 @@ size_t RRSwitchBlock::get_chan_node_segment(enum e_side side, size_t track_id) c /* Get the number of IPIN rr_nodes on a side */ -size_t RRSwitchBlock::get_num_ipin_nodes(enum e_side side) const { +size_t RRGSB::get_num_ipin_nodes(enum e_side side) const { Side side_manager(side); assert(side_manager.validate()); return ipin_node_[side_manager.to_size_t()].size(); } /* get a opin_node at a given side and track_id */ -t_rr_node* RRSwitchBlock::get_ipin_node(enum e_side side, size_t node_id) const { +t_rr_node* RRGSB::get_ipin_node(enum e_side side, size_t node_id) const { Side side_manager(side); assert(side_manager.validate()); @@ -643,7 +643,7 @@ t_rr_node* RRSwitchBlock::get_ipin_node(enum e_side side, size_t node_id) const } /* get the grid_side of a opin_node at a given side and track_id */ -enum e_side RRSwitchBlock::get_ipin_node_grid_side(enum e_side side, size_t node_id) const { +enum e_side RRGSB::get_ipin_node_grid_side(enum e_side side, size_t node_id) const { Side side_manager(side); assert(side_manager.validate()); @@ -657,7 +657,7 @@ enum e_side RRSwitchBlock::get_ipin_node_grid_side(enum e_side side, size_t node } /* get the grid side of a opin_rr_node */ -enum e_side RRSwitchBlock::get_ipin_node_grid_side(t_rr_node* ipin_node) const { +enum e_side RRGSB::get_ipin_node_grid_side(t_rr_node* ipin_node) const { enum e_side side; int index; @@ -670,14 +670,14 @@ enum e_side RRSwitchBlock::get_ipin_node_grid_side(t_rr_node* ipin_node) const { /* Get the number of OPIN rr_nodes on a side */ -size_t RRSwitchBlock::get_num_opin_nodes(enum e_side side) const { +size_t RRGSB::get_num_opin_nodes(enum e_side side) const { Side side_manager(side); assert(side_manager.validate()); return opin_node_[side_manager.to_size_t()].size(); } /* get a opin_node at a given side and track_id */ -t_rr_node* RRSwitchBlock::get_opin_node(enum e_side side, size_t node_id) const { +t_rr_node* RRGSB::get_opin_node(enum e_side side, size_t node_id) const { Side side_manager(side); assert(side_manager.validate()); @@ -691,7 +691,7 @@ t_rr_node* RRSwitchBlock::get_opin_node(enum e_side side, size_t node_id) const } /* get the grid_side of a opin_node at a given side and track_id */ -enum e_side RRSwitchBlock::get_opin_node_grid_side(enum e_side side, size_t node_id) const { +enum e_side RRGSB::get_opin_node_grid_side(enum e_side side, size_t node_id) const { Side side_manager(side); assert(side_manager.validate()); @@ -705,7 +705,7 @@ enum e_side RRSwitchBlock::get_opin_node_grid_side(enum e_side side, size_t node } /* get the grid side of a opin_rr_node */ -enum e_side RRSwitchBlock::get_opin_node_grid_side(t_rr_node* opin_node) const { +enum e_side RRGSB::get_opin_node_grid_side(t_rr_node* opin_node) const { enum e_side side; int index; @@ -717,7 +717,7 @@ enum e_side RRSwitchBlock::get_opin_node_grid_side(t_rr_node* opin_node) const { } /* Get the node index in the array, return -1 if not found */ -int RRSwitchBlock::get_node_index(t_rr_node* node, +int RRGSB::get_node_index(t_rr_node* node, enum e_side node_side, enum PORTS node_direction) const { size_t cnt; @@ -767,7 +767,7 @@ int RRSwitchBlock::get_node_index(t_rr_node* node, } /* Check if the node exist in the opposite side of this Switch Block */ -bool RRSwitchBlock::is_node_exist_opposite_side(t_rr_node* node, +bool RRGSB::is_node_exist_opposite_side(t_rr_node* node, enum e_side node_side) const { Side side_manager(node_side); int index; @@ -787,7 +787,7 @@ bool RRSwitchBlock::is_node_exist_opposite_side(t_rr_node* node, } /* Get the side of a node in this SB */ -void RRSwitchBlock::get_node_side_and_index(t_rr_node* node, +void RRGSB::get_node_side_and_index(t_rr_node* node, enum PORTS node_direction, enum e_side* node_side, int* node_index) const { @@ -822,42 +822,42 @@ void RRSwitchBlock::get_node_side_and_index(t_rr_node* node, return; } -size_t RRSwitchBlock::get_num_reserved_conf_bits() const { +size_t RRGSB::get_num_reserved_conf_bits() const { if (false == validate_num_reserved_conf_bits()) { return 0; } return reserved_conf_bits_msb_ - reserved_conf_bits_lsb_ + 1; } -size_t RRSwitchBlock::get_reserved_conf_bits_lsb() const { +size_t RRGSB::get_reserved_conf_bits_lsb() const { if (false == validate_num_reserved_conf_bits()) { return 0; } return reserved_conf_bits_lsb_; } -size_t RRSwitchBlock::get_reserved_conf_bits_msb() const { +size_t RRGSB::get_reserved_conf_bits_msb() const { if (false == validate_num_reserved_conf_bits()) { return 0; } return reserved_conf_bits_msb_; } -size_t RRSwitchBlock::get_num_conf_bits() const { +size_t RRGSB::get_num_conf_bits() const { if (false == validate_num_conf_bits()) { return 0; } return conf_bits_msb_ - conf_bits_lsb_ + 1; } -size_t RRSwitchBlock::get_conf_bits_lsb() const { +size_t RRGSB::get_conf_bits_lsb() const { if (false == validate_num_conf_bits()) { return 0; } return conf_bits_lsb_; } -size_t RRSwitchBlock::get_conf_bits_msb() const { +size_t RRGSB::get_conf_bits_msb() const { if (false == validate_num_conf_bits()) { return 0; } @@ -865,7 +865,7 @@ size_t RRSwitchBlock::get_conf_bits_msb() const { } /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */ -bool RRSwitchBlock::is_node_imply_short_connection(t_rr_node* src_node) const { +bool RRGSB::is_node_imply_short_connection(t_rr_node* src_node) const { assert((CHANX == src_node->type) || (CHANY == src_node->type)); @@ -889,7 +889,7 @@ bool RRSwitchBlock::is_node_imply_short_connection(t_rr_node* src_node) const { * Number of channel/opin/ipin rr_nodes are same * If all above are satisfied, the two switch blocks may be mirrors ! */ -bool RRSwitchBlock::is_mirrorable(RRSwitchBlock& cand) const { +bool RRGSB::is_mirrorable(RRGSB& cand) const { /* check the numbers of sides */ if (get_num_sides() != cand.get_num_sides()) { return false; @@ -935,7 +935,7 @@ bool RRSwitchBlock::is_mirrorable(RRSwitchBlock& cand) const { /* Determine an initial offset in rotating the candidate Switch Block to find a mirror matching * We try to find the offset in track_id where the two Switch Blocks have their first short connections */ -size_t RRSwitchBlock::get_hint_rotate_offset(RRSwitchBlock& cand) const { +size_t RRGSB::get_hint_rotate_offset(RRGSB& cand) const { size_t offset_hint = size_t(-1); assert (get_num_sides() == cand.get_num_sides()); @@ -960,7 +960,7 @@ size_t RRSwitchBlock::get_hint_rotate_offset(RRSwitchBlock& cand) const { } /* check if all the routing segments of a side of candidate SB is a mirror of the current one */ -bool RRSwitchBlock::is_side_segment_mirror(RRSwitchBlock& cand, enum e_side side, size_t seg_id) const { +bool RRGSB::is_side_segment_mirror(RRGSB& cand, enum e_side side, size_t seg_id) const { /* Create a side manager */ Side side_manager(side); @@ -1023,7 +1023,7 @@ bool RRSwitchBlock::is_side_segment_mirror(RRSwitchBlock& cand, enum e_side side * 5. check if pin class id and pin id are same * If all above are satisfied, the side of the two switch blocks are mirrors! */ -bool RRSwitchBlock::is_side_mirror(RRSwitchBlock& cand, enum e_side side) const { +bool RRGSB::is_side_mirror(RRGSB& cand, enum e_side side) const { /* get a list of segments */ std::vector seg_ids = get_chan(side).get_segment_ids(); @@ -1050,7 +1050,7 @@ bool RRSwitchBlock::is_side_mirror(RRSwitchBlock& cand, enum e_side side) const * 5. check if pin class id and pin id are same * If all above are satisfied, the two switch blocks are mirrors! */ -bool RRSwitchBlock::is_mirror(RRSwitchBlock& cand) const { +bool RRGSB::is_mirror(RRGSB& cand) const { /* check the numbers of sides */ if (get_num_sides() != cand.get_num_sides()) { return false; @@ -1076,7 +1076,7 @@ bool RRSwitchBlock::is_mirror(RRSwitchBlock& cand) const { } /* Public Accessors: Cooridinator conversion */ -DeviceCoordinator RRSwitchBlock::get_side_block_coordinator(enum e_side side) const { +DeviceCoordinator RRGSB::get_side_block_coordinator(enum e_side side) const { Side side_manager(side); assert(side_manager.validate()); DeviceCoordinator ret(get_x(), get_y()); @@ -1111,7 +1111,7 @@ DeviceCoordinator RRSwitchBlock::get_side_block_coordinator(enum e_side side) co } /* Public Accessors Verilog writer */ -char* RRSwitchBlock::gen_verilog_module_name() const { +char* RRGSB::gen_verilog_module_name() const { char* ret = NULL; std::string x_str = std::to_string(get_x()); std::string y_str = std::to_string(get_y()); @@ -1126,7 +1126,7 @@ char* RRSwitchBlock::gen_verilog_module_name() const { return ret; } -char* RRSwitchBlock::gen_verilog_instance_name() const { +char* RRGSB::gen_verilog_instance_name() const { char* ret = NULL; std::string x_str = std::to_string(get_x()); std::string y_str = std::to_string(get_y()); @@ -1142,7 +1142,7 @@ char* RRSwitchBlock::gen_verilog_instance_name() const { } /* Public Accessors Verilog writer */ -char* RRSwitchBlock::gen_verilog_side_module_name(enum e_side side, size_t seg_id) const { +char* RRGSB::gen_verilog_side_module_name(enum e_side side, size_t seg_id) const { char* ret = NULL; Side side_manager(side); @@ -1163,7 +1163,7 @@ char* RRSwitchBlock::gen_verilog_side_module_name(enum e_side side, size_t seg_i return ret; } -char* RRSwitchBlock::gen_verilog_side_instance_name(enum e_side side, size_t seg_id) const { +char* RRGSB::gen_verilog_side_instance_name(enum e_side side, size_t seg_id) const { char* ret = NULL; Side side_manager(side); @@ -1187,7 +1187,7 @@ char* RRSwitchBlock::gen_verilog_side_instance_name(enum e_side side, size_t seg /* Public mutators */ /* get a copy from a source */ -void RRSwitchBlock::set(const RRSwitchBlock& src) { +void RRGSB::set(const RRGSB& src) { /* Copy coordinator */ this->set_coordinator(src.get_coordinator().get_x(), src.get_coordinator().get_y()); @@ -1233,13 +1233,13 @@ void RRSwitchBlock::set(const RRSwitchBlock& src) { /* Set the coordinator (x,y) for the switch block */ -void RRSwitchBlock::set_coordinator(size_t x, size_t y) { +void RRGSB::set_coordinator(size_t x, size_t y) { coordinator_.set(x, y); return; } /* Allocate the vectors with the given number of sides */ -void RRSwitchBlock::init_num_sides(size_t num_sides) { +void RRGSB::init_num_sides(size_t num_sides) { /* Initialize the vectors */ chan_node_.resize(num_sides); chan_node_direction_.resize(num_sides); @@ -1251,7 +1251,7 @@ void RRSwitchBlock::init_num_sides(size_t num_sides) { } /* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ -void RRSwitchBlock::add_chan_node(enum e_side node_side, RRChan& rr_chan, std::vector rr_chan_dir) { +void RRGSB::add_chan_node(enum e_side node_side, RRChan& rr_chan, std::vector rr_chan_dir) { Side side_manager(node_side); /* Validate: 1. side is valid, the type of node is valid */ assert(validate_side(node_side)); @@ -1267,7 +1267,7 @@ void RRSwitchBlock::add_chan_node(enum e_side node_side, RRChan& rr_chan, std::v } /* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ -void RRSwitchBlock::add_ipin_node(t_rr_node* node, enum e_side node_side, enum e_side grid_side) { +void RRGSB::add_ipin_node(t_rr_node* node, enum e_side node_side, enum e_side grid_side) { Side side_manager(node_side); assert(validate_side(node_side)); /* push pack the dedicated element in the vector */ @@ -1278,7 +1278,7 @@ void RRSwitchBlock::add_ipin_node(t_rr_node* node, enum e_side node_side, enum e } /* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ -void RRSwitchBlock::add_opin_node(t_rr_node* node, enum e_side node_side, enum e_side grid_side) { +void RRGSB::add_opin_node(t_rr_node* node, enum e_side node_side, enum e_side grid_side) { Side side_manager(node_side); assert(validate_side(node_side)); /* push pack the dedicated element in the vector */ @@ -1288,7 +1288,7 @@ void RRSwitchBlock::add_opin_node(t_rr_node* node, enum e_side node_side, enum e return; } -void RRSwitchBlock::set_num_reserved_conf_bits(size_t num_reserved_conf_bits) { +void RRGSB::set_num_reserved_conf_bits(size_t num_reserved_conf_bits) { /* For zero bits: make it invalid */ if ( 0 == num_reserved_conf_bits ) { reserved_conf_bits_lsb_ = 1; @@ -1301,18 +1301,18 @@ void RRSwitchBlock::set_num_reserved_conf_bits(size_t num_reserved_conf_bits) { return; } -void RRSwitchBlock::set_conf_bits_lsb(size_t conf_bits_lsb) { +void RRGSB::set_conf_bits_lsb(size_t conf_bits_lsb) { conf_bits_lsb_ = conf_bits_lsb; return; } -void RRSwitchBlock::set_conf_bits_msb(size_t conf_bits_msb) { +void RRGSB::set_conf_bits_msb(size_t conf_bits_msb) { conf_bits_msb_ = conf_bits_msb; return; } /* rotate the channel nodes with the same direction on one side by a given offset */ -void RRSwitchBlock::rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset) { +void RRGSB::rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset) { Side side_manager(side); assert(validate_side(side)); @@ -1329,7 +1329,7 @@ void RRSwitchBlock::rotate_side_chan_node_by_direction(enum e_side side, enum e_ } /* rotate the channel nodes with the same direction on one side by a given offset */ -void RRSwitchBlock::counter_rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset) { +void RRGSB::counter_rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset) { Side side_manager(side); assert(validate_side(side)); @@ -1348,7 +1348,7 @@ void RRSwitchBlock::counter_rotate_side_chan_node_by_direction(enum e_side side, /* rotate all the channel nodes by a given offset */ -void RRSwitchBlock::rotate_side_chan_node(enum e_side side, size_t offset) { +void RRGSB::rotate_side_chan_node(enum e_side side, size_t offset) { Side side_manager(side); /* Partition the chan nodes on this side, depending on its length */ /* skip this side if there is no nodes */ @@ -1367,7 +1367,7 @@ void RRSwitchBlock::rotate_side_chan_node(enum e_side side, size_t offset) { /* rotate all the channel nodes by a given offset */ -void RRSwitchBlock::rotate_chan_node(size_t offset) { +void RRGSB::rotate_chan_node(size_t offset) { /* Rotate chan nodes on each side */ for (size_t side = 0; side < get_num_sides(); ++side) { Side side_manager(side); @@ -1381,7 +1381,7 @@ void RRSwitchBlock::rotate_chan_node(size_t offset) { * Routing Channel nodes are divided into different groups using segment ids * each group is rotated separatedly */ -void RRSwitchBlock::rotate_chan_node_in_group(size_t offset) { +void RRGSB::rotate_chan_node_in_group(size_t offset) { /* Rotate chan nodes on each side */ for (size_t side = 0; side < get_num_sides(); ++side) { Side side_manager(side); @@ -1428,7 +1428,7 @@ void RRSwitchBlock::rotate_chan_node_in_group(size_t offset) { * OPIN nodes are divided into different groups depending on their grid * each group is rotated separatedly */ -void RRSwitchBlock::rotate_side_opin_node_in_group(enum e_side side, size_t offset) { +void RRGSB::rotate_side_opin_node_in_group(enum e_side side, size_t offset) { /* Rotate opin nodes on each side */ Side side_manager(side); size_t rotate_begin = 0; @@ -1480,7 +1480,7 @@ void RRSwitchBlock::rotate_side_opin_node_in_group(enum e_side side, size_t offs * OPIN nodes are divided into different groups depending on their grid * each group is rotated separatedly */ -void RRSwitchBlock::rotate_opin_node_in_group(size_t offset) { +void RRGSB::rotate_opin_node_in_group(size_t offset) { /* Rotate opin nodes on each side */ for (size_t side = 0; side < get_num_sides(); ++side) { Side side_manager(side); @@ -1491,21 +1491,21 @@ void RRSwitchBlock::rotate_opin_node_in_group(size_t offset) { } /* rotate all the channel and opin nodes by a given offset */ -void RRSwitchBlock::rotate(size_t offset) { +void RRGSB::rotate(size_t offset) { rotate_chan_node(offset); rotate_opin_node_in_group(offset); return; } /* rotate one side of the channel and opin nodes by a given offset */ -void RRSwitchBlock::rotate_side(enum e_side side, size_t offset) { +void RRGSB::rotate_side(enum e_side side, size_t offset) { rotate_side_chan_node(side, offset); rotate_side_opin_node_in_group(side, offset); return; } /* Mirror the node direction and port direction of routing track nodes on a side */ -void RRSwitchBlock::mirror_side_chan_node_direction(enum e_side side) { +void RRGSB::mirror_side_chan_node_direction(enum e_side side) { assert(validate_side(side)); Side side_manager(side); @@ -1514,7 +1514,7 @@ void RRSwitchBlock::mirror_side_chan_node_direction(enum e_side side) { } /* swap the chan rr_nodes on two sides */ -void RRSwitchBlock::swap_chan_node(enum e_side src_side, enum e_side des_side) { +void RRGSB::swap_chan_node(enum e_side src_side, enum e_side des_side) { Side src_side_manager(src_side); Side des_side_manager(des_side); std::swap(chan_node_[src_side_manager.to_size_t()], chan_node_[des_side_manager.to_size_t()]); @@ -1523,7 +1523,7 @@ void RRSwitchBlock::swap_chan_node(enum e_side src_side, enum e_side des_side) { } /* swap the OPIN rr_nodes on two sides */ -void RRSwitchBlock::swap_opin_node(enum e_side src_side, enum e_side des_side) { +void RRGSB::swap_opin_node(enum e_side src_side, enum e_side des_side) { Side src_side_manager(src_side); Side des_side_manager(des_side); std::swap(opin_node_[src_side_manager.to_size_t()], opin_node_[des_side_manager.to_size_t()]); @@ -1532,7 +1532,7 @@ void RRSwitchBlock::swap_opin_node(enum e_side src_side, enum e_side des_side) { } /* swap the IPIN rr_nodes on two sides */ -void RRSwitchBlock::swap_ipin_node(enum e_side src_side, enum e_side des_side) { +void RRGSB::swap_ipin_node(enum e_side src_side, enum e_side des_side) { Side src_side_manager(src_side); Side des_side_manager(des_side); std::swap(ipin_node_[src_side_manager.to_size_t()], ipin_node_[des_side_manager.to_size_t()]); @@ -1541,7 +1541,7 @@ void RRSwitchBlock::swap_ipin_node(enum e_side src_side, enum e_side des_side) { } /* Reverse the vector of the OPIN rr_nodes on a side */ -void RRSwitchBlock::reverse_opin_node(enum e_side side) { +void RRGSB::reverse_opin_node(enum e_side side) { Side side_manager(side); std::reverse(opin_node_[side_manager.to_size_t()].begin(), opin_node_[side_manager.to_size_t()].end()); std::reverse(opin_node_grid_side_[side_manager.to_size_t()].begin(), opin_node_grid_side_[side_manager.to_size_t()].end()); @@ -1549,14 +1549,14 @@ void RRSwitchBlock::reverse_opin_node(enum e_side side) { } /* Reverse the vector of the OPIN rr_nodes on a side */ -void RRSwitchBlock::reverse_ipin_node(enum e_side side) { +void RRGSB::reverse_ipin_node(enum e_side side) { Side side_manager(side); std::reverse(ipin_node_[side_manager.to_size_t()].begin(), ipin_node_[side_manager.to_size_t()].end()); std::reverse(ipin_node_grid_side_[side_manager.to_size_t()].begin(), ipin_node_grid_side_[side_manager.to_size_t()].end()); return; } -void RRSwitchBlock::clear() { +void RRGSB::clear() { /* Clean all the vectors */ assert(validate_num_sides()); /* Clear the inner vector of each matrix */ @@ -1586,7 +1586,7 @@ void RRSwitchBlock::clear() { } /* Clean the chan_width of a side */ -void RRSwitchBlock::clear_chan_nodes(enum e_side node_side) { +void RRGSB::clear_chan_nodes(enum e_side node_side) { Side side_manager(node_side); assert(validate_side(node_side)); @@ -1596,7 +1596,7 @@ void RRSwitchBlock::clear_chan_nodes(enum e_side node_side) { } /* Clean the number of IPINs of a side */ -void RRSwitchBlock::clear_ipin_nodes(enum e_side node_side) { +void RRGSB::clear_ipin_nodes(enum e_side node_side) { Side side_manager(node_side); assert(validate_side(node_side)); @@ -1606,7 +1606,7 @@ void RRSwitchBlock::clear_ipin_nodes(enum e_side node_side) { } /* Clean the number of OPINs of a side */ -void RRSwitchBlock::clear_opin_nodes(enum e_side node_side) { +void RRGSB::clear_opin_nodes(enum e_side node_side) { Side side_manager(node_side); assert(validate_side(node_side)); @@ -1616,7 +1616,7 @@ void RRSwitchBlock::clear_opin_nodes(enum e_side node_side) { } /* Clean chan/opin/ipin nodes at one side */ -void RRSwitchBlock::clear_one_side(enum e_side node_side) { +void RRGSB::clear_one_side(enum e_side node_side) { clear_chan_nodes(node_side); clear_ipin_nodes(node_side); clear_opin_nodes(node_side); @@ -1633,7 +1633,7 @@ void RRSwitchBlock::clear_one_side(enum e_side node_side) { * 2. OPIN or IPIN: should have the same side and index * 3. each drive_rr_switch should be the same */ -bool RRSwitchBlock::is_node_mirror(RRSwitchBlock& cand, +bool RRGSB::is_node_mirror(RRGSB& cand, enum e_side node_side, size_t track_id) const { /* Ensure rr_nodes are either the output of short-connection or multiplexer */ @@ -1682,7 +1682,7 @@ bool RRSwitchBlock::is_node_mirror(RRSwitchBlock& cand, return true; } -size_t RRSwitchBlock::get_track_id_first_short_connection(enum e_side node_side) const { +size_t RRGSB::get_track_id_first_short_connection(enum e_side node_side) const { assert(validate_side(node_side)); /* Walk through chan_nodes and find the first short connection */ @@ -1696,7 +1696,7 @@ size_t RRSwitchBlock::get_track_id_first_short_connection(enum e_side node_side) } /* Validate if the number of sides are consistent among internal data arrays ! */ -bool RRSwitchBlock::validate_num_sides() const { +bool RRGSB::validate_num_sides() const { size_t num_sides = chan_node_direction_.size(); if ( num_sides != chan_node_.size() ) { @@ -1723,7 +1723,7 @@ bool RRSwitchBlock::validate_num_sides() const { } /* Check if the side valid in the context: does the switch block have the side? */ -bool RRSwitchBlock::validate_side(enum e_side side) const { +bool RRGSB::validate_side(enum e_side side) const { Side side_manager(side); if ( side_manager.to_size_t() < get_num_sides() ) { return true; @@ -1732,7 +1732,7 @@ bool RRSwitchBlock::validate_side(enum e_side side) const { } /* Check the track_id is valid for chan_node_ and chan_node_direction_ */ -bool RRSwitchBlock::validate_track_id(enum e_side side, size_t track_id) const { +bool RRGSB::validate_track_id(enum e_side side, size_t track_id) const { Side side_manager(side); if (false == validate_side(side)) { @@ -1747,7 +1747,7 @@ bool RRSwitchBlock::validate_track_id(enum e_side side, size_t track_id) const { } /* Check the opin_node_id is valid for opin_node_ and opin_node_grid_side_ */ -bool RRSwitchBlock::validate_opin_node_id(enum e_side side, size_t node_id) const { +bool RRGSB::validate_opin_node_id(enum e_side side, size_t node_id) const { Side side_manager(side); if (false == validate_side(side)) { @@ -1762,7 +1762,7 @@ bool RRSwitchBlock::validate_opin_node_id(enum e_side side, size_t node_id) cons } /* Check the ipin_node_id is valid for opin_node_ and opin_node_grid_side_ */ -bool RRSwitchBlock::validate_ipin_node_id(enum e_side side, size_t node_id) const { +bool RRGSB::validate_ipin_node_id(enum e_side side, size_t node_id) const { Side side_manager(side); if (false == validate_side(side)) { @@ -1777,7 +1777,7 @@ bool RRSwitchBlock::validate_ipin_node_id(enum e_side side, size_t node_id) cons } /* Validate the number of configuration bits, MSB should be no less than the LSB !!! */ -bool RRSwitchBlock::validate_num_conf_bits() const { +bool RRGSB::validate_num_conf_bits() const { if (conf_bits_msb_ >= conf_bits_lsb_) { return true; } @@ -1785,7 +1785,7 @@ bool RRSwitchBlock::validate_num_conf_bits() const { } /* Validate the number of configuration bits, MSB should be no less than the LSB !!! */ -bool RRSwitchBlock::validate_num_reserved_conf_bits() const { +bool RRGSB::validate_num_reserved_conf_bits() const { if (reserved_conf_bits_msb_ >= reserved_conf_bits_lsb_) { return true; } @@ -1796,25 +1796,25 @@ bool RRSwitchBlock::validate_num_reserved_conf_bits() const { /* Accessors */ /* get the max coordinator of the switch block array */ -DeviceCoordinator DeviceRRSwitchBlock::get_switch_block_range() const { +DeviceCoordinator DeviceRRGSB::get_switch_block_range() const { size_t max_y = 0; /* Get the largest size of sub-arrays */ - for (size_t x = 0; x < rr_switch_block_.size(); ++x) { - max_y = std::max(max_y, rr_switch_block_[x].size()); + for (size_t x = 0; x < rr_gsb.size(); ++x) { + max_y = std::max(max_y, rr_gsb[x].size()); } - DeviceCoordinator coordinator(rr_switch_block_.size(), max_y); + DeviceCoordinator coordinator(rr_gsb.size(), max_y); return coordinator; } /* Get a rr switch block in the array with a coordinator */ -RRSwitchBlock DeviceRRSwitchBlock::get_switch_block(DeviceCoordinator& coordinator) const { +RRGSB DeviceRRGSB::get_switch_block(DeviceCoordinator& coordinator) const { assert(validate_coordinator(coordinator)); - return rr_switch_block_[coordinator.get_x()][coordinator.get_y()]; + return rr_gsb[coordinator.get_x()][coordinator.get_y()]; } /* get the number of unique side modules of switch blocks */ -size_t DeviceRRSwitchBlock::get_num_unique_module(enum e_side side, size_t seg_index) const { +size_t DeviceRRGSB::get_num_unique_module(enum e_side side, size_t seg_index) const { Side side_manager(side); assert(validate_side(side)); assert(validate_segment_index(seg_index)); @@ -1822,70 +1822,70 @@ size_t DeviceRRSwitchBlock::get_num_unique_module(enum e_side side, size_t seg_i } /* Get a rr switch block in the array with a coordinator */ -RRSwitchBlock DeviceRRSwitchBlock::get_switch_block(size_t x, size_t y) const { +RRGSB DeviceRRGSB::get_switch_block(size_t x, size_t y) const { DeviceCoordinator coordinator(x, y); return get_switch_block(coordinator); } /* get the number of unique mirrors of switch blocks */ -size_t DeviceRRSwitchBlock::get_num_unique_mirror() const { +size_t DeviceRRGSB::get_num_unique_mirror() const { return unique_mirror_.size(); } /* get the number of rotatable mirrors of switch blocks */ -size_t DeviceRRSwitchBlock::get_num_rotatable_mirror() const { +size_t DeviceRRGSB::get_num_rotatable_mirror() const { return rotatable_mirror_.size(); } /* Get a rr switch block which is a unique module of a side of SB */ -RRSwitchBlock DeviceRRSwitchBlock::get_unique_side_module(size_t index, enum e_side side, size_t seg_id) const { +RRGSB DeviceRRGSB::get_unique_side_module(size_t index, enum e_side side, size_t seg_id) const { assert (validate_unique_module_index(index, side, seg_id)); Side side_manager(side); assert (validate_side(side)); - return rr_switch_block_[unique_module_[side_manager.to_size_t()][seg_id][index].get_x()][unique_module_[side_manager.to_size_t()][seg_id][index].get_y()]; + return rr_gsb[unique_module_[side_manager.to_size_t()][seg_id][index].get_x()][unique_module_[side_manager.to_size_t()][seg_id][index].get_y()]; } /* Get a rr switch block which a unique mirror */ -RRSwitchBlock DeviceRRSwitchBlock::get_unique_mirror(size_t index) const { +RRGSB DeviceRRGSB::get_unique_mirror(size_t index) const { assert (validate_unique_mirror_index(index)); - return rr_switch_block_[unique_mirror_[index].get_x()][unique_mirror_[index].get_y()]; + return rr_gsb[unique_mirror_[index].get_x()][unique_mirror_[index].get_y()]; } /* Give a coordinator of a rr switch block, and return its unique mirror */ -RRSwitchBlock DeviceRRSwitchBlock::get_unique_mirror(DeviceCoordinator& coordinator) const { +RRGSB DeviceRRGSB::get_unique_mirror(DeviceCoordinator& coordinator) const { assert(validate_coordinator(coordinator)); - size_t unique_mirror_id = rr_switch_block_mirror_id_[coordinator.get_x()][coordinator.get_y()]; + size_t unique_mirror_id = rr_gsbmirror_id_[coordinator.get_x()][coordinator.get_y()]; return get_unique_mirror(unique_mirror_id); } /* Get a rr switch block which a unique mirror */ -RRSwitchBlock DeviceRRSwitchBlock::get_rotatable_mirror(size_t index) const { +RRGSB DeviceRRGSB::get_rotatable_mirror(size_t index) const { assert (validate_rotatable_mirror_index(index)); - return rr_switch_block_[rotatable_mirror_[index].get_x()][rotatable_mirror_[index].get_y()]; + return rr_gsb[rotatable_mirror_[index].get_x()][rotatable_mirror_[index].get_y()]; } /* Get the maximum number of sides across the switch blocks */ -size_t DeviceRRSwitchBlock::get_max_num_sides() const { +size_t DeviceRRGSB::get_max_num_sides() const { size_t max_num_sides = 0; - for (size_t ix = 0; ix < rr_switch_block_.size(); ++ix) { - for (size_t iy = 0; iy < rr_switch_block_[ix].size(); ++iy) { - max_num_sides = std::max(max_num_sides, rr_switch_block_[ix][iy].get_num_sides()); + for (size_t ix = 0; ix < rr_gsb.size(); ++ix) { + for (size_t iy = 0; iy < rr_gsb[ix].size(); ++iy) { + max_num_sides = std::max(max_num_sides, rr_gsb[ix][iy].get_num_sides()); } } return max_num_sides; } /* Get the size of segment_ids */ -size_t DeviceRRSwitchBlock::get_num_segments() const { +size_t DeviceRRGSB::get_num_segments() const { return segment_ids_.size(); } /* Get a segment id */ -size_t DeviceRRSwitchBlock::get_segment_id(size_t index) const { +size_t DeviceRRGSB::get_segment_id(size_t index) const { assert(validate_segment_index(index)); return segment_ids_[index]; } @@ -1893,48 +1893,48 @@ size_t DeviceRRSwitchBlock::get_segment_id(size_t index) const { /* Public Mutators */ /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ -void DeviceRRSwitchBlock::set_rr_switch_block_num_reserved_conf_bits(DeviceCoordinator& coordinator, size_t num_reserved_conf_bits) { +void DeviceRRGSB::set_sb_num_reserved_conf_bits(DeviceCoordinator& coordinator, size_t num_reserved_conf_bits) { assert(validate_coordinator(coordinator)); - rr_switch_block_[coordinator.get_x()][coordinator.get_y()].set_num_reserved_conf_bits(num_reserved_conf_bits); + rr_gsb[coordinator.get_x()][coordinator.get_y()].set_num_reserved_conf_bits(num_reserved_conf_bits); return; } /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ -void DeviceRRSwitchBlock::set_rr_switch_block_conf_bits_lsb(DeviceCoordinator& coordinator, size_t conf_bits_lsb) { +void DeviceRRGSB::set_sb_conf_bits_lsb(DeviceCoordinator& coordinator, size_t conf_bits_lsb) { assert(validate_coordinator(coordinator)); - rr_switch_block_[coordinator.get_x()][coordinator.get_y()].set_conf_bits_lsb(conf_bits_lsb); + rr_gsb[coordinator.get_x()][coordinator.get_y()].set_conf_bits_lsb(conf_bits_lsb); return; } /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ -void DeviceRRSwitchBlock::set_rr_switch_block_conf_bits_msb(DeviceCoordinator& coordinator, size_t conf_bits_msb) { +void DeviceRRGSB::set_sb_conf_bits_msb(DeviceCoordinator& coordinator, size_t conf_bits_msb) { assert(validate_coordinator(coordinator)); - rr_switch_block_[coordinator.get_x()][coordinator.get_y()].set_conf_bits_msb(conf_bits_msb); + rr_gsb[coordinator.get_x()][coordinator.get_y()].set_conf_bits_msb(conf_bits_msb); return; } /* Pre-allocate the rr_switch_block array that the device requires */ -void DeviceRRSwitchBlock::reserve(DeviceCoordinator& coordinator) { - rr_switch_block_.resize(coordinator.get_x()); +void DeviceRRGSB::reserve(DeviceCoordinator& coordinator) { + rr_gsb.resize(coordinator.get_x()); rr_sb_unique_module_id_.resize(coordinator.get_x()); - rr_switch_block_mirror_id_.resize(coordinator.get_x()); - rr_switch_block_rotatable_mirror_id_.resize(coordinator.get_x()); + rr_gsbmirror_id_.resize(coordinator.get_x()); + rr_gsbrotatable_mirror_id_.resize(coordinator.get_x()); for (size_t x = 0; x < coordinator.get_x(); ++x) { - rr_switch_block_[x].resize(coordinator.get_y()); + rr_gsb[x].resize(coordinator.get_y()); rr_sb_unique_module_id_[x].resize(coordinator.get_y()); - rr_switch_block_mirror_id_[x].resize(coordinator.get_y()); - rr_switch_block_rotatable_mirror_id_[x].resize(coordinator.get_y()); + rr_gsbmirror_id_[x].resize(coordinator.get_y()); + rr_gsbrotatable_mirror_id_[x].resize(coordinator.get_y()); } return; } /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ -void DeviceRRSwitchBlock::reserve_unique_module_id(DeviceCoordinator& coordinator) { - RRSwitchBlock rr_sb = get_switch_block(coordinator); +void DeviceRRGSB::reserve_unique_module_id(DeviceCoordinator& coordinator) { + RRGSB rr_sb = get_switch_block(coordinator); rr_sb_unique_module_id_[coordinator.get_x()][coordinator.get_y()].resize(rr_sb.get_num_sides()); for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { @@ -1946,47 +1946,47 @@ void DeviceRRSwitchBlock::reserve_unique_module_id(DeviceCoordinator& coordinato } /* Resize rr_switch_block array is needed*/ -void DeviceRRSwitchBlock::resize_upon_need(DeviceCoordinator& coordinator) { - if (coordinator.get_x() + 1 > rr_switch_block_.size()) { - rr_switch_block_.resize(coordinator.get_x() + 1); +void DeviceRRGSB::resize_upon_need(DeviceCoordinator& coordinator) { + if (coordinator.get_x() + 1 > rr_gsb.size()) { + rr_gsb.resize(coordinator.get_x() + 1); rr_sb_unique_module_id_.resize(coordinator.get_x() + 1); - rr_switch_block_mirror_id_.resize(coordinator.get_x() + 1); - rr_switch_block_rotatable_mirror_id_.resize(coordinator.get_x() + 1); + rr_gsbmirror_id_.resize(coordinator.get_x() + 1); + rr_gsbrotatable_mirror_id_.resize(coordinator.get_x() + 1); } - if (coordinator.get_y() + 1 > rr_switch_block_[coordinator.get_x()].size()) { - rr_switch_block_[coordinator.get_x()].resize(coordinator.get_y() + 1); + if (coordinator.get_y() + 1 > rr_gsb[coordinator.get_x()].size()) { + rr_gsb[coordinator.get_x()].resize(coordinator.get_y() + 1); rr_sb_unique_module_id_[coordinator.get_x()].resize(coordinator.get_y() + 1); - rr_switch_block_mirror_id_[coordinator.get_x()].resize(coordinator.get_y() + 1); - rr_switch_block_rotatable_mirror_id_[coordinator.get_x()].resize(coordinator.get_y() + 1); + rr_gsbmirror_id_[coordinator.get_x()].resize(coordinator.get_y() + 1); + rr_gsbrotatable_mirror_id_[coordinator.get_x()].resize(coordinator.get_y() + 1); } return; } /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ -void DeviceRRSwitchBlock::add_rr_switch_block(DeviceCoordinator& coordinator, - RRSwitchBlock& rr_sb) { +void DeviceRRGSB::add_rr_switch_block(DeviceCoordinator& coordinator, + RRGSB& rr_sb) { /* Resize upon needs*/ resize_upon_need(coordinator); /* Add the switch block into array */ - rr_switch_block_[coordinator.get_x()][coordinator.get_y()] = rr_sb; + rr_gsb[coordinator.get_x()][coordinator.get_y()] = rr_sb; return; } /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ -void DeviceRRSwitchBlock::build_unique_mirror() { +void DeviceRRGSB::build_unique_mirror() { /* Make sure a clean start */ clear_mirror(); - for (size_t ix = 0; ix < rr_switch_block_.size(); ++ix) { - for (size_t iy = 0; iy < rr_switch_block_[ix].size(); ++iy) { + for (size_t ix = 0; ix < rr_gsb.size(); ++ix) { + for (size_t iy = 0; iy < rr_gsb[ix].size(); ++iy) { bool is_unique_mirror = true; - RRSwitchBlock* rr_sb = &(rr_switch_block_[ix][iy]); + RRGSB* rr_sb = &(rr_gsb[ix][iy]); /* Traverse the unique_mirror list and check it is an mirror of another */ for (size_t mirror_id = 0; mirror_id < get_num_unique_mirror(); ++mirror_id) { @@ -2000,7 +2000,7 @@ void DeviceRRSwitchBlock::build_unique_mirror() { /* This is a mirror, raise the flag and we finish */ is_unique_mirror = false; /* Record the id of unique mirror */ - rr_switch_block_mirror_id_[ix][iy] = mirror_id; + rr_gsbmirror_id_[ix][iy] = mirror_id; break; } } @@ -2009,7 +2009,7 @@ void DeviceRRSwitchBlock::build_unique_mirror() { DeviceCoordinator coordinator(ix, iy); unique_mirror_.push_back(coordinator); /* Record the id of unique mirror */ - rr_switch_block_mirror_id_[ix][iy] = unique_mirror_.size() - 1; + rr_gsbmirror_id_[ix][iy] = unique_mirror_.size() - 1; } } } @@ -2017,7 +2017,7 @@ void DeviceRRSwitchBlock::build_unique_mirror() { } /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ -void DeviceRRSwitchBlock::build_unique_module() { +void DeviceRRGSB::build_unique_module() { /* Make sure a clean start */ clear_unique_module(); @@ -2027,10 +2027,10 @@ void DeviceRRSwitchBlock::build_unique_module() { unique_module_[side].resize(segment_ids_.size()); } - for (size_t ix = 0; ix < rr_switch_block_.size(); ++ix) { - for (size_t iy = 0; iy < rr_switch_block_[ix].size(); ++iy) { + for (size_t ix = 0; ix < rr_gsb.size(); ++ix) { + for (size_t iy = 0; iy < rr_gsb[ix].size(); ++iy) { DeviceCoordinator coordinator(ix, iy); - RRSwitchBlock rr_sb = rr_switch_block_[ix][iy]; + RRGSB rr_sb = rr_gsb[ix][iy]; /* reserve the rr_sb_unique_module_id */ reserve_unique_module_id(coordinator); @@ -2046,8 +2046,8 @@ void DeviceRRSwitchBlock::build_unique_module() { } -void DeviceRRSwitchBlock::add_rotatable_mirror(DeviceCoordinator& coordinator, - RRSwitchBlock& rotated_rr_sb) { +void DeviceRRGSB::add_rotatable_mirror(DeviceCoordinator& coordinator, + RRGSB& rotated_rr_sb) { bool is_rotatable_mirror = true; /* add rotatable mirror support */ @@ -2060,7 +2060,7 @@ void DeviceRRSwitchBlock::add_rotatable_mirror(DeviceCoordinator& coordinator, /* This is a mirror, raise the flag and we finish */ is_rotatable_mirror = false; /* Record the id of unique mirror */ - rr_switch_block_rotatable_mirror_id_[coordinator.get_x()][coordinator.get_y()] = mirror_id; + rr_gsbrotatable_mirror_id_[coordinator.get_x()][coordinator.get_y()] = mirror_id; break; } } @@ -2069,7 +2069,7 @@ void DeviceRRSwitchBlock::add_rotatable_mirror(DeviceCoordinator& coordinator, if (true == is_rotatable_mirror) { rotatable_mirror_.push_back(coordinator); /* Record the id of unique mirror */ - rr_switch_block_rotatable_mirror_id_[coordinator.get_x()][coordinator.get_y()] = rotatable_mirror_.size() - 1; + rr_gsbrotatable_mirror_id_[coordinator.get_x()][coordinator.get_y()] = rotatable_mirror_.size() - 1; /* printf("Detect a rotatable mirror: SB[%lu][%lu]\n", coordinator.get_x(), coordinator.get_y()); */ @@ -2078,8 +2078,8 @@ void DeviceRRSwitchBlock::add_rotatable_mirror(DeviceCoordinator& coordinator, return; } -void DeviceRRSwitchBlock::add_unique_side_segment_module(DeviceCoordinator& coordinator, - RRSwitchBlock& rr_sb, +void DeviceRRGSB::add_unique_side_segment_module(DeviceCoordinator& coordinator, + RRGSB& rr_sb, enum e_side side, size_t seg_id) { bool is_unique_side_module = true; @@ -2115,8 +2115,8 @@ void DeviceRRSwitchBlock::add_unique_side_segment_module(DeviceCoordinator& coor * If it is similar to any module[side][i] in the list, we build a link from the rr_sb to the unique_module * Otherwise, we add the module to the unique_module list */ -void DeviceRRSwitchBlock::add_unique_side_module(DeviceCoordinator& coordinator, - RRSwitchBlock& rr_sb, +void DeviceRRGSB::add_unique_side_module(DeviceCoordinator& coordinator, + RRGSB& rr_sb, enum e_side side) { Side side_manager(side); @@ -2128,11 +2128,11 @@ void DeviceRRSwitchBlock::add_unique_side_module(DeviceCoordinator& coordinator, } /* build a map of segment_ids */ -void DeviceRRSwitchBlock::build_segment_ids() { +void DeviceRRGSB::build_segment_ids() { /* go through each rr_sb, each side and find the segment_ids */ - for (size_t ix = 0; ix < rr_switch_block_.size(); ++ix) { - for (size_t iy = 0; iy < rr_switch_block_[ix].size(); ++iy) { - RRSwitchBlock* rr_sb = &(rr_switch_block_[ix][iy]); + for (size_t ix = 0; ix < rr_gsb.size(); ++ix) { + for (size_t iy = 0; iy < rr_gsb[ix].size(); ++iy) { + RRGSB* rr_sb = &(rr_gsb[ix][iy]); for (size_t side = 0 ; side < rr_sb->get_num_sides(); ++side) { Side side_manager(side); /* get a list of segment_ids in this side */ @@ -2155,18 +2155,18 @@ void DeviceRRSwitchBlock::build_segment_ids() { } /* clean the content */ -void DeviceRRSwitchBlock::clear() { +void DeviceRRGSB::clear() { /* clean rr_switch_block array */ - for (size_t x = 0; x < rr_switch_block_.size(); ++x) { - rr_switch_block_[x].clear(); - rr_switch_block_mirror_id_[x].clear(); - rr_switch_block_rotatable_mirror_id_[x].clear(); + for (size_t x = 0; x < rr_gsb.size(); ++x) { + rr_gsb[x].clear(); + rr_gsbmirror_id_[x].clear(); + rr_gsbrotatable_mirror_id_[x].clear(); } - rr_switch_block_.clear(); + rr_gsb.clear(); - rr_switch_block_mirror_id_.clear(); + rr_gsbmirror_id_.clear(); - rr_switch_block_rotatable_mirror_id_.clear(); + rr_gsbrotatable_mirror_id_.clear(); /* clean rr_sb_unique_side_module_id */ for (size_t x = 0; x < rr_sb_unique_module_id_.size(); ++x) { @@ -2191,7 +2191,7 @@ void DeviceRRSwitchBlock::clear() { } /* clean the content related to unique_mirrors */ -void DeviceRRSwitchBlock::clear_unique_module() { +void DeviceRRGSB::clear_unique_module() { /* clean unique_side_module_ */ for (size_t side = 0; side < unique_module_.size(); ++side) { unique_module_[side].clear(); @@ -2201,7 +2201,7 @@ void DeviceRRSwitchBlock::clear_unique_module() { } /* clean the content related to unique_mirrors */ -void DeviceRRSwitchBlock::clear_mirror() { +void DeviceRRGSB::clear_mirror() { /* clean unique mirror */ unique_mirror_.clear(); @@ -2209,14 +2209,14 @@ void DeviceRRSwitchBlock::clear_mirror() { } /* clean the content related to rotatable_mirrors */ -void DeviceRRSwitchBlock::clear_rotatable_mirror() { +void DeviceRRGSB::clear_rotatable_mirror() { /* clean unique mirror */ rotatable_mirror_.clear(); return; } /* clean the content related to segment_ids */ -void DeviceRRSwitchBlock::clear_segment_ids() { +void DeviceRRGSB::clear_segment_ids() { /* clean segment_ids_ */ segment_ids_.clear(); @@ -2225,18 +2225,18 @@ void DeviceRRSwitchBlock::clear_segment_ids() { /* Validate if the (x,y) is the range of this device */ -bool DeviceRRSwitchBlock::validate_coordinator(DeviceCoordinator& coordinator) const { - if (coordinator.get_x() >= rr_switch_block_.capacity()) { +bool DeviceRRGSB::validate_coordinator(DeviceCoordinator& coordinator) const { + if (coordinator.get_x() >= rr_gsb.capacity()) { return false; } - if (coordinator.get_y() >= rr_switch_block_[coordinator.get_x()].capacity()) { + if (coordinator.get_y() >= rr_gsb[coordinator.get_x()].capacity()) { return false; } return true; } /* Validate if the index in the range of unique_mirror vector*/ -bool DeviceRRSwitchBlock::validate_side(enum e_side side) const { +bool DeviceRRGSB::validate_side(enum e_side side) const { Side side_manager(side); if (side_manager.to_size_t() >= unique_module_.size()) { return false; @@ -2245,7 +2245,7 @@ bool DeviceRRSwitchBlock::validate_side(enum e_side side) const { } /* Validate if the index in the range of unique_mirror vector*/ -bool DeviceRRSwitchBlock::validate_unique_mirror_index(size_t index) const { +bool DeviceRRGSB::validate_unique_mirror_index(size_t index) const { if (index >= unique_mirror_.size()) { return false; } @@ -2253,7 +2253,7 @@ bool DeviceRRSwitchBlock::validate_unique_mirror_index(size_t index) const { } /* Validate if the index in the range of unique_mirror vector*/ -bool DeviceRRSwitchBlock::validate_rotatable_mirror_index(size_t index) const { +bool DeviceRRGSB::validate_rotatable_mirror_index(size_t index) const { if (index >= rotatable_mirror_.size()) { return false; } @@ -2261,7 +2261,7 @@ bool DeviceRRSwitchBlock::validate_rotatable_mirror_index(size_t index) const { } /* Validate if the index in the range of unique_mirror vector*/ -bool DeviceRRSwitchBlock::validate_unique_module_index(size_t index, enum e_side side, size_t seg_index) const { +bool DeviceRRGSB::validate_unique_module_index(size_t index, enum e_side side, size_t seg_index) const { assert( validate_side(side)); assert( validate_segment_index(seg_index)); Side side_manager(side); @@ -2272,7 +2272,7 @@ bool DeviceRRSwitchBlock::validate_unique_module_index(size_t index, enum e_side return true; } -bool DeviceRRSwitchBlock::validate_segment_index(size_t index) const { +bool DeviceRRGSB::validate_segment_index(size_t index) const { if (index >= segment_ids_.size()) { return false; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h index 1f1034239..4df6f28ad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h @@ -129,10 +129,10 @@ class DeviceRRChan { * num_reserved_conf_bits: number of reserved configuration bits this switch block requires (mainly due to RRAM-based multiplexers) * num_conf_bits: number of configuration bits this switch block requires */ -class RRSwitchBlock { +class RRGSB { public: /* Contructors */ - RRSwitchBlock(const RRSwitchBlock&);/* Copy constructor */ - RRSwitchBlock();/* Default constructor */ + RRGSB(const RRGSB&);/* Copy constructor */ + RRGSB();/* Default constructor */ public: /* Accessors */ size_t get_x() const; /* get the x coordinator of this switch block */ size_t get_y() const; /* get the y coordinator of this switch block */ @@ -162,11 +162,11 @@ class RRSwitchBlock { size_t get_conf_bits_lsb() const; size_t get_conf_bits_msb() const; bool is_node_imply_short_connection(t_rr_node* src_node) const; /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */ - bool is_side_mirror(RRSwitchBlock& cand, enum e_side side) const; /* check if a side of candidate SB is a mirror of the current one */ - bool is_side_segment_mirror(RRSwitchBlock& cand, enum e_side side, size_t seg_id) const; /* check if all the routing segments of a side of candidate SB is a mirror of the current one */ - bool is_mirror(RRSwitchBlock& cand) const; /* check if the candidate SB is a mirror of the current one */ - bool is_mirrorable(RRSwitchBlock& cand) const; /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */ - size_t get_hint_rotate_offset(RRSwitchBlock& cand) const; /* Determine an initial offset in rotating the candidate Switch Block to find a mirror matching*/ + bool is_side_mirror(RRGSB& cand, enum e_side side) const; /* check if a side of candidate SB is a mirror of the current one */ + bool is_side_segment_mirror(RRGSB& cand, enum e_side side, size_t seg_id) const; /* check if all the routing segments of a side of candidate SB is a mirror of the current one */ + bool is_mirror(RRGSB& cand) const; /* check if the candidate SB is a mirror of the current one */ + bool is_mirrorable(RRGSB& cand) const; /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */ + size_t get_hint_rotate_offset(RRGSB& cand) const; /* Determine an initial offset in rotating the candidate Switch Block to find a mirror matching*/ public: /* Cooridinator conversion */ DeviceCoordinator get_side_block_coordinator(enum e_side side) const; public: /* Verilog writer */ @@ -175,7 +175,7 @@ class RRSwitchBlock { char* gen_verilog_side_module_name(enum e_side side, size_t seg_id) const; char* gen_verilog_side_instance_name(enum e_side side, size_t seg_id) const; public: /* Mutators */ - void set(const RRSwitchBlock& src); /* get a copy from a source */ + void set(const RRGSB& src); /* get a copy from a source */ void set_coordinator(size_t x, size_t y); void init_num_sides(size_t num_sides); /* Allocate the vectors with the given number of sides */ void add_chan_node(enum e_side node_side, RRChan& rr_chan, std::vector rr_chan_dir); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */ @@ -206,7 +206,7 @@ class RRSwitchBlock { private: /* Internal Mutators */ void mirror_side_chan_node_direction(enum e_side side); /* Mirror the node direction and port direction of routing track nodes on a side */ private: /* internal functions */ - bool is_node_mirror (RRSwitchBlock& cand, enum e_side node_side, size_t track_id) const; + bool is_node_mirror (RRGSB& cand, enum e_side node_side, size_t track_id) const; size_t get_track_id_first_short_connection(enum e_side node_side) const; bool validate_num_sides() const; bool validate_side(enum e_side side) const; @@ -232,40 +232,40 @@ class RRSwitchBlock { /* Object Device Routing Resource Switch Block * This includes: * 1. a collection of RRSwitch blocks, each of which can be used to instance Switch blocks in the top-level netlists - * 2. a collection of unique mirrors of RRSwitchBlocks, which can be used to output Verilog / SPICE modules - * 3. a colleciton of unique rotatable of RRSwitchBlocks, which can be used to output Verilog / SPICE modules - * The rotatable RRSwitchBlocks are more generic mirrors, which allow SwitchBlocks to be wired by rotating the pins, + * 2. a collection of unique mirrors of RRGSBs, which can be used to output Verilog / SPICE modules + * 3. a colleciton of unique rotatable of RRGSBs, which can be used to output Verilog / SPICE modules + * The rotatable RRGSBs are more generic mirrors, which allow SwitchBlocks to be wired by rotating the pins, * further reduce the number of Verilog/SPICE modules outputted. This will lead to rapid layout generation */ -class DeviceRRSwitchBlock { +class DeviceRRGSB { public: /* Contructors */ public: /* Accessors */ DeviceCoordinator get_switch_block_range() const; /* get the max coordinator of the switch block array */ - RRSwitchBlock get_switch_block(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */ - RRSwitchBlock get_switch_block(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */ + RRGSB get_switch_block(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */ + RRGSB get_switch_block(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */ size_t get_num_unique_module(enum e_side side, size_t seg_index) const; /* get the number of unique mirrors of switch blocks */ size_t get_num_unique_mirror() const; /* get the number of unique mirrors of switch blocks */ size_t get_num_rotatable_mirror() const; /* get the number of rotatable mirrors of switch blocks */ - RRSwitchBlock get_unique_side_module(size_t index, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */ - RRSwitchBlock get_unique_mirror(size_t index) const; /* Get a rr switch block which a unique mirror */ - RRSwitchBlock get_unique_mirror(DeviceCoordinator& coordinator) const; /* Get a rr switch block which a unique mirror */ - RRSwitchBlock get_rotatable_mirror(size_t index) const; /* Get a rr switch block which a unique mirror */ + RRGSB get_unique_side_module(size_t index, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */ + RRGSB get_unique_mirror(size_t index) const; /* Get a rr switch block which a unique mirror */ + RRGSB get_unique_mirror(DeviceCoordinator& coordinator) const; /* Get a rr switch block which a unique mirror */ + RRGSB get_rotatable_mirror(size_t index) const; /* Get a rr switch block which a unique mirror */ size_t get_max_num_sides() const; /* Get the maximum number of sides across the switch blocks */ size_t get_num_segments() const; /* Get the size of segment_ids */ size_t get_segment_id(size_t index) const; /* Get a segment id */ public: /* Mutators */ - void set_rr_switch_block_num_reserved_conf_bits(DeviceCoordinator& coordinator, size_t num_reserved_conf_bits); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ - void set_rr_switch_block_conf_bits_lsb(DeviceCoordinator& coordinator, size_t conf_bits_lsb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ - void set_rr_switch_block_conf_bits_msb(DeviceCoordinator& coordinator, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ + void set_sb_num_reserved_conf_bits(DeviceCoordinator& coordinator, size_t num_reserved_conf_bits); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ + void set_sb_conf_bits_lsb(DeviceCoordinator& coordinator, size_t conf_bits_lsb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ + void set_sb_conf_bits_msb(DeviceCoordinator& coordinator, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ void reserve(DeviceCoordinator& coordinator); /* Pre-allocate the rr_switch_block array that the device requires */ void reserve_unique_module_id(DeviceCoordinator& coordinator); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ void resize_upon_need(DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */ - void add_rr_switch_block(DeviceCoordinator& coordinator, RRSwitchBlock& rr_sb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ + void add_rr_switch_block(DeviceCoordinator& coordinator, RRGSB& rr_sb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ void build_unique_mirror(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ void build_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */ - void add_rotatable_mirror(DeviceCoordinator& coordinator, RRSwitchBlock& rr_sb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ - void add_unique_side_segment_module(DeviceCoordinator& coordinator, RRSwitchBlock& rr_sb, enum e_side side, size_t seg_id); - void add_unique_side_module(DeviceCoordinator& coordinator, RRSwitchBlock& rr_sb, enum e_side side); + void add_rotatable_mirror(DeviceCoordinator& coordinator, RRGSB& rr_sb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ + void add_unique_side_segment_module(DeviceCoordinator& coordinator, RRGSB& rr_sb, enum e_side side, size_t seg_id); + void add_unique_side_module(DeviceCoordinator& coordinator, RRGSB& rr_sb, enum e_side side); void build_segment_ids(); /* build a map of segment_ids */ void clear(); /* clean the content */ void clear_unique_module(); /* clean the content */ @@ -280,14 +280,14 @@ class DeviceRRSwitchBlock { bool validate_unique_module_index(size_t index, enum e_side side, size_t seg_index) const; /* Validate if the index in the range of unique_module vector */ bool validate_segment_index(size_t index) const; private: /* Internal Data */ - std::vector< std::vector > rr_switch_block_; + std::vector< std::vector > rr_gsb; std::vector< std::vector< std::vector< std::vector > > > rr_sb_unique_module_id_; /* A map from rr_switch_block to its unique_side_module [0..x][0..y][0..num_sides][num_seg-1]*/ std::vector< std::vector > > unique_module_; /* For each side of switch block, we identify a list of unique modules based on its connection. This is a matrix [0..num_sides-1][0..num_seg-1][0..num_module], num_sides will the max number of sides of all the rr_switch_blocks */ - std::vector< std::vector > rr_switch_block_mirror_id_; /* A map from rr_switch_block to its unique mirror */ + std::vector< std::vector > rr_gsbmirror_id_; /* A map from rr_switch_block to its unique mirror */ std::vector unique_mirror_; - std::vector< std::vector > rr_switch_block_rotatable_mirror_id_; /* A map from rr_switch_block to its unique mirror */ + std::vector< std::vector > rr_gsbrotatable_mirror_id_; /* A map from rr_switch_block to its unique mirror */ std::vector rotatable_mirror_; std::vector segment_ids_; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.cpp index 495259921..4a65a8e29 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.cpp @@ -10,7 +10,7 @@ #include "fpga_x2p_utils.h" -void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb) { +void write_rr_switch_block_to_xml(std::string fname_prefix, RRGSB& rr_sb) { /* Prepare file name */ std::string fname(fname_prefix); fname += rr_sb.gen_verilog_module_name(); @@ -116,20 +116,20 @@ void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb } /* Output each rr_switch_block to a XML file */ -void write_device_rr_switch_block_to_xml(char* sb_xml_dir, - DeviceRRSwitchBlock& LL_device_rr_switch_block) { +void write_device_rr_gsb_to_xml(char* sb_xml_dir, + DeviceRRGSB& LL_device_rr_gsb) { std::string fname_prefix(sb_xml_dir); /* Add slash if needed */ if ('/' != fname_prefix.back()) { fname_prefix += '/'; } - DeviceCoordinator sb_range = LL_device_rr_switch_block.get_switch_block_range(); + DeviceCoordinator sb_range = LL_device_rr_gsb.get_switch_block_range(); /* For each switch block, an XML file will be outputted */ for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - RRSwitchBlock rr_sb = LL_device_rr_switch_block.get_switch_block(ix, iy); + RRGSB rr_sb = LL_device_rr_gsb.get_switch_block(ix, iy); write_rr_switch_block_to_xml(fname_prefix, rr_sb); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.h index bcd0a01d9..49001e6ee 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.h @@ -1,8 +1,8 @@ #ifndef WRITE_RR_BLOCKS_H #define WRITE_RR_BLOCKS_H -void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb); +void write_rr_switch_block_to_xml(std::string fname_prefix, RRGSB& rr_sb); -void write_device_rr_switch_block_to_xml(char* sb_xml_dir, DeviceRRSwitchBlock& LL_device_rr_switch_block); +void write_device_rr_gsb_to_xml(char* sb_xml_dir, DeviceRRGSB& LL_device_rr_gsb); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c index d44c80ea8..4871c9b48 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c @@ -36,7 +36,7 @@ /* Generate bitstream for a multiplexer of a switch block */ static void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_sram_orgz_info* cur_sram_orgz_info, t_rr_node* cur_rr_node, int mux_size, @@ -211,7 +211,7 @@ void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp, static void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_sram_orgz_info* cur_sram_orgz_info, enum e_side chan_side, t_rr_node* cur_rr_node) { @@ -342,7 +342,7 @@ void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp, */ static void fpga_spice_generate_bitstream_routing_switch_box_subckt(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_sram_orgz_info* cur_sram_orgz_info) { /* Check */ /* Check the file handler*/ @@ -675,10 +675,10 @@ void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log /* Switch Boxes*/ vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Switch blocks...\n"); if (TRUE == compact_routing_hierarchy) { - DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range(); + DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range(); for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy); + RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy); fpga_spice_generate_bitstream_routing_switch_box_subckt(fp, rr_sb, cur_sram_orgz_info); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index ac004fee9..f87ee5602 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -749,7 +749,7 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, static void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - RRSwitchBlock& rr_sb) { + RRGSB& rr_sb) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -766,7 +766,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz /* If we have an mirror SB, we should the module name of the mirror !!! */ DeviceCoordinator coordinator = rr_sb.get_coordinator(); - RRSwitchBlock unique_mirror = device_rr_switch_block.get_unique_mirror(coordinator); + RRGSB unique_mirror = device_rr_gsb.get_unique_mirror(coordinator); fprintf(fp, "%s ", unique_mirror.gen_verilog_module_name()); fprintf(fp, "%s ", rr_sb.gen_verilog_instance_name()); fprintf(fp, "("); @@ -850,7 +850,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz static void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp) { - DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range(); + DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range(); /* Check the file handler*/ if (NULL == fp) { @@ -861,7 +861,7 @@ void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_i for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy); + RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy); dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, rr_sb); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c index 358b6b68c..31de5e895 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c @@ -245,7 +245,7 @@ void free_wire_L_llist(t_llist* rr_path_cnt) { */ static void verilog_generate_one_report_timing_within_sb(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_rr_node* src_rr_node, t_rr_node* des_rr_node) { /* Check the file handler */ @@ -371,7 +371,7 @@ void verilog_generate_one_report_timing_sb_to_cb(FILE* fp, */ static void verilog_generate_one_report_timing_sb_to_cb(FILE* fp, - RRSwitchBlock& src_sb, + RRGSB& src_sb, t_rr_node* src_rr_node, t_cb* des_cb_info, t_rr_node* des_rr_node) { @@ -413,9 +413,9 @@ void verilog_generate_one_report_timing_sb_to_cb(FILE* fp, */ static void verilog_generate_one_report_timing_sb_to_sb(FILE* fp, - RRSwitchBlock& src_sb, + RRGSB& src_sb, t_rr_node* src_rr_node, - RRSwitchBlock& des_sb, + RRGSB& des_sb, t_rr_node* des_rr_node) { /* Check the file handler */ if (NULL == fp) { @@ -597,9 +597,9 @@ void build_ending_rr_node_for_one_sb_wire(t_rr_node* wire_rr_node, */ static void verilog_generate_report_timing_one_sb_thru_segments(FILE* fp, - RRSwitchBlock src_sb, + RRGSB src_sb, t_rr_node* src_rr_node, - RRSwitchBlock des_sb, + RRGSB des_sb, t_rr_node* des_rr_node, char* rpt_name) { /* Check the file handler */ @@ -692,13 +692,13 @@ void verilog_generate_report_timing_one_sb_thru_segments(FILE* fp, */ static void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp, - RRSwitchBlock& src_sb, + RRGSB& src_sb, t_rr_node* src_rr_node, t_rr_node* des_rr_node, char* rpt_name) { t_cb* next_cb = NULL; DeviceCoordinator next_sb_coordinator; - RRSwitchBlock next_sb; + RRGSB next_sb; /* Check the file handler */ if (NULL == fp) { @@ -719,7 +719,7 @@ void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp, case CHANY: /* Get the coordinate of ending SB */ next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node); - next_sb = device_rr_switch_block.get_switch_block(next_sb_coordinator); + next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator); verilog_generate_one_report_timing_sb_to_sb(fp, src_sb, src_rr_node, next_sb, src_rr_node); break; @@ -801,7 +801,7 @@ void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp, static void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, t_syn_verilog_opts fpga_verilog_opts, - RRSwitchBlock& src_sb, + RRGSB& src_sb, t_rr_node* drive_rr_node, t_rr_node* src_rr_node, t_rr_node* des_rr_node, @@ -812,7 +812,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, t_cb* next_cb = NULL; char* rpt_name = NULL; DeviceCoordinator next_sb_coordinator; - RRSwitchBlock next_sb; + RRGSB next_sb; /* Check the file handler */ if (NULL == fp) { @@ -947,7 +947,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, case CHANY: /* Get the coordinate of ending CB */ next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node); - next_sb = device_rr_switch_block.get_switch_block(next_sb_coordinator); + next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator); end_sb_x = next_sb.get_x(); end_sb_y = next_sb.get_y(); break; @@ -966,7 +966,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, /* Follow the graph above, go through X channel */ for (int ix = src_sb.get_x(); ix < end_sb_x; ix++) { DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y); - RRSwitchBlock begin_sb = device_rr_switch_block.get_switch_block(begin_sb_coordinator); + RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator); /* If this is the ending point, we add a ending segment */ if (ix == end_sb_x - 1) { verilog_generate_report_timing_one_sb_ending_segments(fp, @@ -978,7 +978,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, } /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ DeviceCoordinator end_sb_coordinator(ix + 1, cur_sb_y); - RRSwitchBlock end_sb = device_rr_switch_block.get_switch_block(end_sb_coordinator); + RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator); verilog_generate_report_timing_one_sb_thru_segments(fp, begin_sb, src_rr_node, end_sb, src_rr_node, @@ -989,7 +989,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, /* Follow the graph above, go through Y channel */ for (int iy = src_sb.get_y(); iy < end_sb_y; iy++) { DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy); - RRSwitchBlock begin_sb = device_rr_switch_block.get_switch_block(begin_sb_coordinator); + RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator); /* If this is the ending point, we add a ending segment */ if (iy == end_sb_y - 1) { verilog_generate_report_timing_one_sb_ending_segments(fp, @@ -1000,7 +1000,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, } /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ DeviceCoordinator end_sb_coordinator(cur_sb_x, iy + 1); - RRSwitchBlock end_sb = device_rr_switch_block.get_switch_block(end_sb_coordinator); + RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator); verilog_generate_report_timing_one_sb_thru_segments(fp, begin_sb, src_rr_node, end_sb, src_rr_node, @@ -1011,7 +1011,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, /* Follow the graph above, go through X channel */ for (int ix = src_sb.get_x() - 1; ix > end_sb_x; ix--) { DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y); - RRSwitchBlock begin_sb = device_rr_switch_block.get_switch_block(begin_sb_coordinator); + RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator); /* If this is the ending point, we add a ending segment */ if (ix == end_sb_x + 1) { verilog_generate_report_timing_one_sb_ending_segments(fp, @@ -1022,7 +1022,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, } /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ DeviceCoordinator end_sb_coordinator(ix - 1, cur_sb_y); - RRSwitchBlock end_sb = device_rr_switch_block.get_switch_block(end_sb_coordinator); + RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator); verilog_generate_report_timing_one_sb_thru_segments(fp, begin_sb, src_rr_node, end_sb, src_rr_node, @@ -1033,7 +1033,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, /* Follow the graph above, go through Y channel */ for (int iy = src_sb.get_y() - 1; iy > end_sb_y; iy--) { DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy); - RRSwitchBlock begin_sb = device_rr_switch_block.get_switch_block(begin_sb_coordinator); + RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator); /* If this is the ending point, we add a ending segment */ if (iy == end_sb_y + 1) { verilog_generate_report_timing_one_sb_ending_segments(fp, @@ -1044,7 +1044,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, } /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ DeviceCoordinator end_sb_coordinator(cur_sb_x, iy - 1); - RRSwitchBlock end_sb = device_rr_switch_block.get_switch_block(end_sb_coordinator); + RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator); verilog_generate_report_timing_one_sb_thru_segments(fp, begin_sb, src_rr_node, end_sb, src_rr_node, @@ -1310,14 +1310,14 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, */ static void dump_verilog_sb_through_routing_pins(FILE* fp, - RRSwitchBlock& src_rr_sb, + RRGSB& src_rr_sb, t_rr_node* src_rr_node, t_rr_node* des_rr_node) { size_t cur_sb_x, cur_sb_y; size_t end_sb_x, end_sb_y; t_cb* next_cb; DeviceCoordinator next_sb_coordinator; - RRSwitchBlock next_sb; + RRGSB next_sb; /* Check the file handler */ if (NULL == fp) { @@ -1432,7 +1432,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp, case CHANY: /* Get the coordinate of ending CB */ next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node); - next_sb = device_rr_switch_block.get_switch_block(next_sb_coordinator); + next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator); end_sb_x = next_sb.get_x(); end_sb_y = next_sb.get_y(); break; @@ -1454,7 +1454,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp, fprintf(fp, " "); /* output instance name */ DeviceCoordinator inter_sb_coordinator(ix, cur_sb_y); - RRSwitchBlock inter_sb = device_rr_switch_block.get_switch_block(inter_sb_coordinator); + RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator); fprintf(fp, "%s/", inter_sb.gen_verilog_instance_name()); dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT); @@ -1473,7 +1473,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp, fprintf(fp, " "); /* output instance name */ DeviceCoordinator inter_sb_coordinator(cur_sb_x, iy); - RRSwitchBlock inter_sb = device_rr_switch_block.get_switch_block(inter_sb_coordinator); + RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator); fprintf(fp, "%s/", inter_sb.gen_verilog_instance_name()); dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT); @@ -1492,7 +1492,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp, fprintf(fp, " "); /* output instance name */ DeviceCoordinator inter_sb_coordinator(ix, cur_sb_y); - RRSwitchBlock inter_sb = device_rr_switch_block.get_switch_block(inter_sb_coordinator); + RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator); fprintf(fp, "%s/", inter_sb.gen_verilog_instance_name()); dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT); @@ -1511,7 +1511,7 @@ void dump_verilog_sb_through_routing_pins(FILE* fp, fprintf(fp, " "); /* output instance name */ DeviceCoordinator inter_sb_coordinator(cur_sb_x, iy); - RRSwitchBlock inter_sb = device_rr_switch_block.get_switch_block(inter_sb_coordinator); + RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator); fprintf(fp, "%s/", inter_sb.gen_verilog_instance_name()); dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT); @@ -1751,7 +1751,7 @@ static void verilog_generate_one_routing_wire_report_timing(FILE* fp, t_trpt_opts sdc_opts, int L_wire, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_rr_node* wire_rr_node, t_rr_node* LL_rr_node) { int path_cnt = 0; @@ -1784,7 +1784,7 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp, DeviceCoordinator next_sb_coordinator; /* Reciever could be IPIN or CHANX or CHANY */ int inode = wire_rr_node->edges[jedge]; - RRSwitchBlock next_sb; + RRGSB next_sb; t_cb* next_cb = NULL; /* Find the SB/CB block that it belongs to */ switch (LL_rr_node[inode].type) { @@ -1831,7 +1831,7 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp, case CHANY: /* Get the coordinate of ending SB */ next_sb_coordinator = get_chan_node_ending_sb_coordinator(wire_rr_node, &(LL_rr_node[inode])); - next_sb = device_rr_switch_block.get_switch_block(next_sb_coordinator); + next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator); /* This will not be the longest path unless the cb is close to the ending SB */ if ((TRUE == sdc_opts.longest_path_only) && ((next_sb.get_x() != (size_t)x_end) || (next_sb.get_y() != (size_t)y_end))) { @@ -2055,10 +2055,10 @@ void verilog_generate_routing_wires_report_timing(FILE* fp, } if (TRUE == sdc_opts.compact_routing_hierarchy) { - DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range(); + DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range(); for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy); + RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy); for (size_t side = 0; side < rr_sb.get_num_sides(); side++) { Side side_manager(side); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { @@ -2195,7 +2195,7 @@ void verilog_generate_sb_report_timing(t_trpt_opts sdc_opts, static void verilog_generate_one_routing_segmental_report_timing(FILE* fp, t_syn_verilog_opts fpga_verilog_opts, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_rr_node* wire_rr_node, t_rr_node* LL_rr_node, int* path_cnt) { @@ -2386,10 +2386,10 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts, "Generating TCL script to report timing for routing wires\n"); /* We start from a SB[x][y] */ - DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range(); + DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range(); for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy); + RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy); for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { Side side_manager(side); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index b717eb6ba..4364ed217 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -661,7 +661,7 @@ void dump_verilog_switch_box_chan_port(FILE* fp, static void dump_verilog_unique_switch_box_chan_port(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, enum e_side chan_side, t_rr_node* cur_rr_node, enum PORTS cur_rr_node_direction) { @@ -703,7 +703,7 @@ void dump_verilog_unique_switch_box_chan_port(FILE* fp, */ static void dump_verilog_unique_switch_box_short_interc(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, enum e_side chan_side, t_rr_node* cur_rr_node, int actual_fan_in, @@ -1134,7 +1134,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, static void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, enum e_side chan_side, t_rr_node* cur_rr_node, int mux_size, @@ -1410,7 +1410,7 @@ int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_in /* Count the number of configuration bits of a rr_node*/ static size_t count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - RRSwitchBlock& rr_sb, enum e_side chan_side, + RRGSB& rr_sb, enum e_side chan_side, t_rr_node* cur_rr_node) { size_t num_conf_bits = 0; int switch_idx = 0; @@ -1485,7 +1485,7 @@ int count_verilog_switch_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sra /* Count the number of reserved configuration bits of a rr_node*/ static size_t count_verilog_switch_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - RRSwitchBlock& rr_sb, enum e_side chan_side, + RRGSB& rr_sb, enum e_side chan_side, t_rr_node* cur_rr_node) { size_t num_reserved_conf_bits = 0; int switch_idx = 0; @@ -1578,7 +1578,7 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, static void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, enum e_side chan_side, t_rr_node* cur_rr_node) { int num_drive_rr_nodes = 0; @@ -1660,7 +1660,7 @@ int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_ /* Count the number of configuration bits of a Switch Box */ static size_t count_verilog_switch_box_side_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - RRSwitchBlock& rr_sb, enum e_side side, size_t seg_id) { + RRGSB& rr_sb, enum e_side side, size_t seg_id) { size_t num_reserved_conf_bits = 0; size_t temp_num_reserved_conf_bits = 0; Side side_manager(side); @@ -1695,7 +1695,7 @@ size_t count_verilog_switch_box_side_reserved_conf_bits(t_sram_orgz_info* cur_sr /* Count the number of configuration bits of a Switch Box */ static size_t count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - RRSwitchBlock& rr_sb) { + RRGSB& rr_sb) { size_t num_reserved_conf_bits = 0; size_t temp_num_reserved_conf_bits = 0; @@ -1744,7 +1744,7 @@ int count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, /* Count the number of configuration bits of a Switch Box */ static size_t count_verilog_switch_box_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, enum e_side side, size_t seg_id) { size_t num_conf_bits = 0; Side side_manager(side); @@ -1775,7 +1775,7 @@ size_t count_verilog_switch_box_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_i /* Count the number of configuration bits of a Switch Box */ static size_t count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - RRSwitchBlock& rr_sb) { + RRGSB& rr_sb) { size_t num_conf_bits = 0; for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { @@ -1792,7 +1792,7 @@ size_t count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, static void update_routing_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - RRSwitchBlock& rr_sb) { + RRGSB& rr_sb) { int cur_num_bl, cur_num_wl; get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_num_bl, &cur_num_wl); @@ -1807,9 +1807,9 @@ void update_routing_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, /* Estimate the sram_verilog_model->cnt */ int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - device_rr_switch_block.set_rr_switch_block_num_reserved_conf_bits(sb_coordinator, num_reserved_conf_bits); - device_rr_switch_block.set_rr_switch_block_conf_bits_lsb(sb_coordinator, cur_num_sram); - device_rr_switch_block.set_rr_switch_block_conf_bits_msb(sb_coordinator, cur_num_sram + num_conf_bits - 1); + device_rr_gsb.set_sb_num_reserved_conf_bits(sb_coordinator, num_reserved_conf_bits); + device_rr_gsb.set_sb_conf_bits_lsb(sb_coordinator, cur_num_sram); + device_rr_gsb.set_sb_conf_bits_msb(sb_coordinator, cur_num_sram + num_conf_bits - 1); /* Update the counter */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_conf_bits); @@ -1824,7 +1824,7 @@ void update_routing_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, */ static void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, enum e_side sb_side, size_t seg_id, boolean dump_port_type) { @@ -1946,7 +1946,7 @@ static void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, size_t module_id, size_t seg_id, - RRSwitchBlock& rr_sb, enum e_side side) { + RRGSB& rr_sb, enum e_side side) { FILE* fp = NULL; char* fname = NULL; Side side_manager(side); @@ -2092,7 +2092,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr static void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - RRSwitchBlock& rr_sb) { + RRGSB& rr_sb) { FILE* fp = NULL; char* fname = NULL; @@ -2333,7 +2333,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or static void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - RRSwitchBlock& rr_sb) { + RRGSB& rr_sb) { FILE* fp = NULL; char* fname = NULL; @@ -3453,30 +3453,30 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, t_sram_orgz_info* stamped_sram_orgz_info = snapshot_sram_orgz_info(cur_sram_orgz_info); /* Output unique side modules */ - for (size_t side = 0; side < device_rr_switch_block.get_max_num_sides(); ++side) { + for (size_t side = 0; side < device_rr_gsb.get_max_num_sides(); ++side) { Side side_manager(side); - for (size_t iseg = 0; iseg < device_rr_switch_block.get_num_segments(); ++iseg) { - for (size_t isb = 0; isb < device_rr_switch_block.get_num_unique_module(side_manager.get_side(), iseg); ++isb) { - RRSwitchBlock unique_mirror = device_rr_switch_block.get_unique_side_module(isb, side_manager.get_side(), iseg); - size_t seg_id = device_rr_switch_block.get_segment_id(iseg); + for (size_t iseg = 0; iseg < device_rr_gsb.get_num_segments(); ++iseg) { + for (size_t isb = 0; isb < device_rr_gsb.get_num_unique_module(side_manager.get_side(), iseg); ++isb) { + RRGSB unique_mirror = device_rr_gsb.get_unique_side_module(isb, side_manager.get_side(), iseg); + size_t seg_id = device_rr_gsb.get_segment_id(iseg); dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side()); } } } /* Output unique modules */ - for (size_t isb = 0; isb < device_rr_switch_block.get_num_unique_mirror(); ++isb) { - RRSwitchBlock unique_mirror = device_rr_switch_block.get_unique_mirror(isb); + for (size_t isb = 0; isb < device_rr_gsb.get_num_unique_mirror(); ++isb) { + RRGSB unique_mirror = device_rr_gsb.get_unique_mirror(isb); dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror); } /* Restore sram_orgz_info to the base */ copy_sram_orgz_info (cur_sram_orgz_info, stamped_sram_orgz_info); - DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range(); + DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range(); for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy); + RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy); update_routing_switch_box_conf_bits(cur_sram_orgz_info, rr_sb); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index 4bcbb1921..98e27e964 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -1011,11 +1011,11 @@ void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp) { exit(1); } - DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range(); + DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range(); for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy); + RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy); /* Print comments */ fprintf(fp, "########################################################\n"); @@ -1167,11 +1167,11 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp) { exit(1); } - DeviceCoordinator sb_range = device_rr_switch_block.get_switch_block_range(); + DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range(); /* We start from a SB[x][y] */ for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(ix, iy); + RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy); /* Print comments */ fprintf(fp, "##################################################\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c index caecf6ebe..7e02d08da 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c @@ -60,7 +60,7 @@ void dump_verilog_sdc_file_header(FILE* fp, } void dump_verilog_one_sb_chan_pin(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_rr_node* cur_rr_node, enum PORTS port_type) { int track_idx; @@ -135,7 +135,7 @@ void dump_verilog_one_sb_chan_pin(FILE* fp, /* Output the pin name of a routing wire in a SB */ void dump_verilog_one_sb_routing_pin(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_rr_node* cur_rr_node) { int side; @@ -398,7 +398,7 @@ DeviceCoordinator get_chan_node_ending_sb_coordinator(t_rr_node* src_rr_node, } DeviceCoordinator sb_coordinator(next_sb_x, next_sb_y); - RRSwitchBlock rr_sb = device_rr_switch_block.get_switch_block(sb_coordinator); + RRGSB rr_sb = device_rr_gsb.get_switch_block(sb_coordinator); /* Double check if src_rr_node is in the list */ enum e_side side; int index; @@ -552,7 +552,7 @@ t_sb* get_chan_rr_node_ending_sb(t_rr_node* src_rr_node, /* Restore the disabled timing for the sb wire */ void restore_disable_timing_one_sb_output(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_rr_node* wire_rr_node) { /* Check the file handler */ if (NULL == fp) { @@ -604,7 +604,7 @@ void restore_disable_timing_one_sb_output(FILE* fp, /* Restore the disabled timing for the sb wire */ void set_disable_timing_one_sb_output(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_rr_node* wire_rr_node) { /* Check the file handler */ if (NULL == fp) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h index cab307677..e9169a73a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h @@ -9,7 +9,7 @@ void dump_verilog_sdc_file_header(FILE* fp, char* usage); void dump_verilog_one_sb_chan_pin(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_rr_node* cur_rr_node, enum PORTS port_type); @@ -19,7 +19,7 @@ void dump_verilog_one_sb_chan_pin(FILE* fp, enum PORTS port_type); void dump_verilog_one_sb_routing_pin(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_rr_node* cur_rr_node); void dump_verilog_one_sb_routing_pin(FILE* fp, @@ -36,7 +36,7 @@ t_sb* get_chan_rr_node_ending_sb(t_rr_node* src_rr_node, t_rr_node* end_rr_node); void restore_disable_timing_one_sb_output(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_rr_node* wire_rr_node); void restore_disable_timing_one_sb_output(FILE* fp, @@ -44,7 +44,7 @@ void restore_disable_timing_one_sb_output(FILE* fp, t_rr_node* wire_rr_node); void set_disable_timing_one_sb_output(FILE* fp, - RRSwitchBlock& rr_sb, + RRGSB& rr_sb, t_rr_node* wire_rr_node); void set_disable_timing_one_sb_output(FILE* fp, diff --git a/vpr7_x2p/vpr/go_fpga_verilog.sh b/vpr7_x2p/vpr/go_fpga_verilog.sh index 861bf5b10..cb2cb23dc 100755 --- a/vpr7_x2p/vpr/go_fpga_verilog.sh +++ b/vpr7_x2p/vpr/go_fpga_verilog.sh @@ -39,8 +39,8 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname\_compact # Run VPR #valgrind -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl +echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl" -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname\_compact --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl +echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname\_compact --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl"