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fixed a bug in wired LUT

This commit is contained in:
tangxifan 2018-12-06 16:50:30 -07:00
parent 7795d4e7fd
commit b3c1018e28
2 changed files with 7 additions and 6 deletions
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6
fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf
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@ -1,11 +1,11 @@
# Standard Configuration Example
[dir_path]
script_base = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/scripts/
benchmark_dir = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/benchmarks/RelChip_verilog_bench/
benchmark_dir = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/benchmarks/FPGA_SPICE_bench/
yosys_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../yosys/yosys
odin2_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
cirkit_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/not_used_atm/cirkit
abc_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../abc/abc
abc_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../yosys/yosys-abc
abc_mccl_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../abc_with_bb_support/abc
abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../abc_with_bb_support/abc
mpack1_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/not_used_atm/mpack1
@ -16,7 +16,7 @@ rpt_dir = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/results
ace_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../ace2/ace
[flow_conf]
flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
vpr_arch = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf

7
vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c
View File

@ -5894,14 +5894,15 @@ int get_pb_graph_node_wired_lut_logical_block_index(t_pb_graph_node* cur_pb_grap
for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) {
for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) {
temp_rr_node_index = cur_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster;
if (OPEN != op_pb_rr_graph[temp_rr_node_index].vpack_net_num) {
if (lut_output_vpack_net_num == op_pb_rr_graph[temp_rr_node_index].vpack_net_num) {
num_used_lut_input_pins++;
lut_output_vpack_net_num = op_pb_rr_graph[temp_rr_node_index].vpack_net_num;
}
}
}
/* Make sure we only have 1 used input pin */
assert (1 == num_used_lut_input_pins);
if (1 != num_used_lut_input_pins) {
assert (1 == num_used_lut_input_pins);
}
/* vpr_printf(TIO_MESSAGE_INFO, "Wired LUT output vpack_net_num is %d\n", lut_output_vpack_net_num); */