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OpenFPGA
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adapt arch xml and act for demo

This commit is contained in:
tangxifan 2018-12-13 22:46:40 -07:00
parent 3d9e913e4e
commit ee6b1d6cd6
5 changed files with 38 additions and 37 deletions
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2
vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_tsmc40nm_TT.xml
View File

@ -164,7 +164,7 @@
</delay>
</measure>
<stimulate>
<clock op_freq="auto" sim_slack="0.2" prog_freq="2.5e6">
<clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6">
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>

50
vpr7_x2p/vpr/Circuits/fifo_1bit.act
View File

@ -33,27 +33,27 @@ int_reg[28] 0.000000 0.000000
int_reg[29] 0.000000 0.000000
int_reg[30] 0.000000 0.000000
data_out 0.000000 0.000000
n64 0.021400 0.103732
n69 0.016400 0.104289
n74 0.013600 0.104355
n79 0.011800 0.104449
n84 0.010200 0.104579
n89 0.008400 0.104751
n94 0.006800 0.104964
n99 0.005200 0.105218
n104 0.003600 0.105473
n109 0.002400 0.105561
n114 0.001400 0.105648
n119 0.001000 0.105609
n124 0.000800 0.105610
n129 0.000600 0.105652
n134 0.000400 0.105695
n139 0.000200 0.105737
n144 0.000000 0.105779
n149 0.000000 0.105738
n154 0.000000 0.105738
n159 0.000000 0.105738
n164 0.000000 0.105738
n64 0.021400 0.003732
n69 0.016400 0.004289
n74 0.013600 0.004355
n79 0.011800 0.004449
n84 0.010200 0.004579
n89 0.008400 0.004751
n94 0.006800 0.004964
n99 0.005200 0.005218
n104 0.003600 0.005473
n109 0.002400 0.005561
n114 0.001400 0.005648
n119 0.001000 0.005609
n124 0.000800 0.005610
n129 0.000600 0.005652
n134 0.000400 0.005695
n139 0.000200 0.005737
n144 0.000000 0.005779
n149 0.000000 0.005738
n154 0.000000 0.005738
n159 0.000000 0.005738
n164 0.000000 0.005738
n9 0.257400 0.049974
n14 0.202800 0.087932
n19 0.160800 0.092067
@ -61,7 +61,7 @@ n24 0.130400 0.094679
n29 0.106200 0.096468
n34 0.085800 0.097926
n39 0.070200 0.099152
n44 0.055800 0.100744
n49 0.043600 0.102005
n54 0.033400 0.103037
n59 0.026000 0.103481
n44 0.055800 0.000744
n49 0.043600 0.002005
n54 0.033400 0.003037
n59 0.026000 0.003481

17
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_api.c
View File

@ -284,14 +284,15 @@ void vpr_dump_syn_verilog(t_vpr_setup vpr_setup,
/* Output Modelsim Autodeck scripts */
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_modelsim_autodeck) {
dump_verilog_modelsim_autodeck(sram_verilog_orgz_info, *(Arch.spice), num_clocks,
verilog_dir_formatted, chomped_circuit_name,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.modelsim_ini_path,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.include_timing,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.init_sim,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_tb,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_auto_tb,
tb_preconf);
dump_verilog_modelsim_autodeck(sram_verilog_orgz_info, *(Arch.spice),
Arch.spice->spice_params.meas_params.sim_num_clock_cycle,
verilog_dir_formatted, chomped_circuit_name,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.modelsim_ini_path,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.include_timing,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.init_sim,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_tb,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_auto_tb,
tb_preconf);
}
/* dump verilog testbench only for input blif */

2
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_global.c
View File

@ -25,7 +25,7 @@ char* modelsim_top_script_name_postfix = "_runsim.tcl";
char* modelsim_testbench_module_postfix = "_top_tb";
char* modelsim_auto_testbench_module_postfix = "_top_auto_tb";
char* modelsim_auto_preconf_testbench_module_postfix = "_top_auto_preconf_tb";
char* modelsim_simulation_time_unit = "ms";
char* modelsim_simulation_time_unit = "ns";
char* verilog_top_postfix = "_top.v";
char* bitstream_verilog_file_postfix = ".bitstream";

4
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_modelsim_autodeck.c
View File

@ -518,7 +518,7 @@ void dump_verilog_modelsim_top_script(char* modelsim_top_script_filename,
fprintf(fp, "\n");
fprintf(fp, "#in ms\n");
fprintf(fp, "set simtime %.4g\n", sim_time);
fprintf(fp, "set simtime %.18g\n", sim_time);
fprintf(fp, "set unit %s\n",
sim_time_unit);
fprintf(fp, "\n");
@ -587,7 +587,7 @@ void dump_verilog_modelsim_top_auto_script(char* modelsim_top_auto_script_filena
fprintf(fp, "\n");
fprintf(fp, "#in ms\n");
fprintf(fp, "set simtime %.4g\n", sim_time);
fprintf(fp, "set simtime %.18g\n", sim_time);
fprintf(fp, "set unit %s\n",
sim_time_unit);
fprintf(fp, "\n");