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Correction of the SDC to remove global clocks

This commit is contained in:
Baudouin Chauviere 2019-05-30 15:04:21 -06:00
parent ba05a08ef0
commit 1932d00309
2 changed files with 6 additions and 1 deletions
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2
vpr7_x2p/vpr/SRC/ctags_vpr_src.sh
View File

@ -1,2 +1,2 @@
rm tags
ctags -R shell_main.c main.c ./* ../../libarchfpga/include/*.[ch] ../../libarchfpga/fpga_spice_include/*.[ch] ../../libarchfpga/*.[ch] ../../pcre/SRC/*.[ch]
ctags -R shell_main.c main.c ./* ../../libarchfpga/include/*.[ch] ../../libarchfpga/fpga_spice_include/*.[ch] ../../libarchfpga/*.[ch] ../../pcre/SRC/*.[ch] ../../libarchfpga/SRC/include/*.[ch]

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -1590,6 +1590,11 @@ void verilog_generate_sdc_disable_one_unused_block(FILE* fp,
if (FALSE == is_rr_node_to_be_disable_for_analysis(&(cur_phy_pb->rr_graph->rr_node[inode]))) {
continue;
}
/* If pin is global port, don't dump */
if (PB_PIN_CLOCK == cur_phy_pb->rr_graph->rr_node[inode].pb_graph_pin->type) {
continue;
}
/* Get the pb_graph_pin */
assert (NULL != cur_phy_pb->rr_graph->rr_node[inode].pb_graph_pin);
/* Disable the timing of this node */