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Path correction in tech debugging + correction of yosys rewrite file in fpga_flow

This commit is contained in:
AurelienUoU 2019-05-30 09:52:19 -06:00
parent 0e820d38ea
commit ba05a08ef0
3 changed files with 4 additions and 4 deletions
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4
fpga_flow/benchmarks/Verilog/MCNC/apex2/apex2.v
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@ -2,12 +2,12 @@
module apex2 (
i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_,
i_11_, i_12_, i_13_, i_14_, i_15_, i_16_, i_17_, i_18_, i_19_, i_20_,
i_11_, i_12_, i_13_, i_14_, i_16_, i_17_, i_18_, i_19_, i_20_,
i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, i_30_,
i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_,
o_0_, o_1_, o_2_ );
input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_,
i_10_, i_11_, i_12_, i_13_, i_14_, i_15_, i_16_, i_17_, i_18_, i_19_,
i_10_, i_11_, i_12_, i_13_, i_14_, i_16_, i_17_, i_18_, i_19_,
i_20_, i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_,
i_30_, i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_;
output o_0_, o_1_, o_2_;

2
fpga_flow/scripts/fpga_flow.pl
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@ -1890,7 +1890,7 @@ sub run_yosys_vpr_flow($ $ $ $ $)
$vpr_reroute_log = "$prefix"."vpr_reroute.log";
# Need to add a regenation of the verilog from the optimized blif -> write verilog from blif + correct the name of the verilog for the testbench
$verilog_benchmark = &run_rewrite_verilog($ace_new_blif, $rpt_dir, $benchmark, $benchmark, $yosys_log);
$verilog_benchmark = &run_rewrite_verilog($corrected_ace_blif, $rpt_dir, $benchmark, $benchmark, $yosys_log);
&run_vpr_in_flow($tag, $benchmark, $benchmark_file, $corrected_ace_blif, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results);

2
vpr7_x2p/vpr/.regression_verilog.sh
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@ -37,7 +37,7 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname
# Run VPR
#valgrind
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_sdc_pnr --fpga_verilog_print_report_timing_tcl --power --tech_properties ../../fpga_flow/tech/PTM_45nm/45nm.xml #--fpga_verilog_print_sdc_analysis
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml #--fpga_verilog_print_sdc_analysis --fpga_verilog_print_sdc_pnr