From 1932d00309afbf8a67a726063afce0f24ca6cef3 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 30 May 2019 15:04:21 -0600 Subject: [PATCH] Correction of the SDC to remove global clocks --- vpr7_x2p/vpr/SRC/ctags_vpr_src.sh | 2 +- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh index c12803ba1..030dca84f 100755 --- a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh +++ b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh @@ -1,2 +1,2 @@ rm tags -ctags -R shell_main.c main.c ./* ../../libarchfpga/include/*.[ch] ../../libarchfpga/fpga_spice_include/*.[ch] ../../libarchfpga/*.[ch] ../../pcre/SRC/*.[ch] +ctags -R shell_main.c main.c ./* ../../libarchfpga/include/*.[ch] ../../libarchfpga/fpga_spice_include/*.[ch] ../../libarchfpga/*.[ch] ../../pcre/SRC/*.[ch] ../../libarchfpga/SRC/include/*.[ch] diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index 5b36b0b37..d21c62704 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -1590,6 +1590,11 @@ void verilog_generate_sdc_disable_one_unused_block(FILE* fp, if (FALSE == is_rr_node_to_be_disable_for_analysis(&(cur_phy_pb->rr_graph->rr_node[inode]))) { continue; } + /* If pin is global port, don't dump */ + if (PB_PIN_CLOCK == cur_phy_pb->rr_graph->rr_node[inode].pb_graph_pin->type) { + continue; + } + /* Get the pb_graph_pin */ assert (NULL != cur_phy_pb->rr_graph->rr_node[inode].pb_graph_pin); /* Disable the timing of this node */