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fixed a bug for rram based fpga when using explicit verilog port mapping

This commit is contained in:
giacomin 2019-05-20 16:44:47 -06:00
parent cd4dc8b2e8
commit 8b520349e7
1 changed files with 4 additions and 4 deletions
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8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
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@ -873,12 +873,12 @@ void dump_verilog_rram_mux_one_basis_module_structural(FILE* fp,
*/
/* LEFT part */
for (i = 0; i < num_input_basis_subckt - 1; i++) {
fprintf(fp, "%s %s_%d (in[%d], wl[%d], bl[%d], out);\n",
fprintf(fp, "%s %s_%d (.A(in[%d]), .WL(wl[%d]), .BLB(bl[%d]), .Z(out));\n",
progTE_module_name, progTE_module_name, i,
i, i, i);
}
/* RIGHT part */
fprintf(fp, "%s %s_%d (out, wl[%d], bl[%d]);\n",
fprintf(fp, "%s %s_%d (.INOUT(out), .WL(wl[%d]), .BLB(bl[%d]));\n",
progBE_module_name, progBE_module_name, i,
i, i);
@ -2058,7 +2058,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp,
fprintf(fp, ".%s(",
buf_input_port[0]->lib_name);
}
fprintf(fp, "%s[%d], ", input_port[0]->prefix, i); /* input port */
fprintf(fp, "%s[%d]", input_port[0]->prefix, i); /* input port */
if ( TRUE == spice_model.input_buffer->spice_model->dump_explicit_port_map) {
fprintf(fp, ")");
}
@ -2069,7 +2069,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp,
fprintf(fp, ".%s(",
buf_output_port[0]->lib_name);
}
fprintf(fp, "mux2_l%d_in[%d]);", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/
fprintf(fp, "mux2_l%d_in[%d]", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/
if ( TRUE == spice_model.input_buffer->spice_model->dump_explicit_port_map) {
fprintf(fp, ")");
}