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fix bugs in fpga_flow.pl

This commit is contained in:
tangxifan 2019-07-10 21:12:00 -06:00
parent a90316e9f4
commit 31749fe62b
2 changed files with 20 additions and 20 deletions
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4
fpga_flow/scripts/fpga_flow.pl
View File

@ -1318,7 +1318,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
my ($chan_width_opt) = ("");
if (($fix_chan_width > 0)||($fix_chan_width == 0)) {
$chan_width_opt = "-route_chan_width $fix_chan_width";
$chan_width_opt = "--route_chan_width $fix_chan_width";
}
if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) {
$chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width";
@ -1569,7 +1569,7 @@ sub run_mpack2_vpr($ $ $ $ $ $ $)
if (0 != $min_chan_width%2) {
$min_chan_width += 1;
}
$chan_width_opt = "-route_chan_width $min_chan_width";
$chan_width_opt = "--route_chan_width $min_chan_width";
}
chdir $vpr_dir;

36
vpr7_x2p/vpr/SRC/base/vpr_api.c
View File

@ -365,16 +365,16 @@ void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) {
alloc_and_load_grid(num_instances_type);
freeGrid();
/* Xifan TANG: We need consider the length of carry-chain CLBs into account! */
num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros);
/* find length of longest carry-chain logic blocks */
max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros);
/* Free all the allocated structs */
free_placement_macros_structs();
for (imacro = 0; imacro < num_pl_macros; imacro ++) {
free(pl_macros[imacro].members);
}
free(pl_macros);
/* Xifan TANG: We need consider the length of carry-chain CLBs into account! */
num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros);
/* find length of longest carry-chain logic blocks */
max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros);
/* Free all the allocated structs */
free_placement_macros_structs();
for (imacro = 0; imacro < num_pl_macros; imacro ++) {
free(pl_macros[imacro].members);
}
free(pl_macros);
/* Test if netlist fits in grid */
fit = TRUE;
@ -384,14 +384,14 @@ void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) {
break;
}
}
/* If the length of macros is longer than ny - 2, fitting should fail.
* Note: carry-chain logic blocks are placed only vertically in FPGA.
*/
if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) {
fit = FALSE;
vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d)!\n",
max_len_chain_blocks, ny);
}
/* If the length of macros is longer than ny - 2, fitting should fail.
* Note: carry-chain logic blocks are placed only vertically in FPGA.
*/
if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) {
fit = FALSE;
vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d)!\n",
max_len_chain_blocks, ny);
}
/* get next value */
if (!fit) {