fix bugs in fpga_flow.pl
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parent
a90316e9f4
commit
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@ -1318,7 +1318,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
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my ($chan_width_opt) = ("");
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if (($fix_chan_width > 0)||($fix_chan_width == 0)) {
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$chan_width_opt = "-route_chan_width $fix_chan_width";
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$chan_width_opt = "--route_chan_width $fix_chan_width";
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}
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if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) {
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$chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width";
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@ -1569,7 +1569,7 @@ sub run_mpack2_vpr($ $ $ $ $ $ $)
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if (0 != $min_chan_width%2) {
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$min_chan_width += 1;
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}
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$chan_width_opt = "-route_chan_width $min_chan_width";
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$chan_width_opt = "--route_chan_width $min_chan_width";
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}
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chdir $vpr_dir;
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@ -365,16 +365,16 @@ void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) {
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alloc_and_load_grid(num_instances_type);
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freeGrid();
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/* Xifan TANG: We need consider the length of carry-chain CLBs into account! */
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num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros);
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/* find length of longest carry-chain logic blocks */
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max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros);
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/* Free all the allocated structs */
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free_placement_macros_structs();
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for (imacro = 0; imacro < num_pl_macros; imacro ++) {
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free(pl_macros[imacro].members);
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}
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free(pl_macros);
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/* Xifan TANG: We need consider the length of carry-chain CLBs into account! */
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num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros);
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/* find length of longest carry-chain logic blocks */
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max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros);
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/* Free all the allocated structs */
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free_placement_macros_structs();
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for (imacro = 0; imacro < num_pl_macros; imacro ++) {
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free(pl_macros[imacro].members);
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}
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free(pl_macros);
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/* Test if netlist fits in grid */
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fit = TRUE;
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@ -384,14 +384,14 @@ void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) {
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break;
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}
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}
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/* If the length of macros is longer than ny - 2, fitting should fail.
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* Note: carry-chain logic blocks are placed only vertically in FPGA.
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*/
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if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) {
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fit = FALSE;
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vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d)!\n",
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max_len_chain_blocks, ny);
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}
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/* If the length of macros is longer than ny - 2, fitting should fail.
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* Note: carry-chain logic blocks are placed only vertically in FPGA.
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*/
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if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) {
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fit = FALSE;
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vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d)!\n",
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max_len_chain_blocks, ny);
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}
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/* get next value */
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if (!fit) {
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