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Fix bug

This commit is contained in:
Baudouin Chauviere 2019-06-05 11:40:04 -06:00
parent fcc10d8acf
commit d24488092d
6 changed files with 19 additions and 9 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c
View File

@ -585,7 +585,7 @@ int get_rr_node_index_in_cb_info(t_rr_node* cur_rr_node,
/* Determine the coordinate of a chan_rr_node in a SB_info
* Return chan_type & chan_rr_node_x & chan_rr_node_y
*/
void get_chan_rr_node_coorindate_in_sb_info(t_sb cur_sb_info,
void get_chan_rr_node_coordinate_in_sb_info(t_sb cur_sb_info,
int chan_rr_node_side,
t_rr_type* chan_type,
int* chan_rr_node_x, int* chan_rr_node_y) {

2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h
View File

@ -41,7 +41,7 @@ void get_rr_node_side_and_index_in_sb_info(t_rr_node* cur_rr_node,
OUTP int* cur_rr_node_side,
OUTP int* cur_rr_node_index);
void get_chan_rr_node_coorindate_in_sb_info(t_sb cur_sb_info,
void get_chan_rr_node_coordinate_in_sb_info(t_sb cur_sb_info,
int chan_rr_node_side,
t_rr_type* chan_type,
int* chan_rr_node_x, int* chan_rr_node_y);

2
vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c
View File

@ -274,7 +274,7 @@ void fprint_switch_box_chan_port(FILE* fp,
/* Make sure this node is included in this sb_info */
assert((-1 != index)&&(-1 != chan_side));
get_chan_rr_node_coorindate_in_sb_info(cur_sb_info, chan_side,
get_chan_rr_node_coordinate_in_sb_info(cur_sb_info, chan_side,
&chan_rr_node_type, &chan_rr_node_x, &chan_rr_node_y);
assert(cur_rr_node->type == chan_rr_node_type);

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -645,7 +645,7 @@ void dump_verilog_switch_box_chan_port(FILE* fp,
/* Make sure this node is included in this sb_info */
assert((-1 != index)&&(-1 != chan_side));
get_chan_rr_node_coorindate_in_sb_info((*cur_sb_info), chan_side,
get_chan_rr_node_coordinate_in_sb_info((*cur_sb_info), chan_side,
&chan_rr_node_type, &chan_rr_node_x, &chan_rr_node_y);
assert(cur_rr_node->type == chan_rr_node_type);

18
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -772,7 +772,7 @@ void verilog_generate_sdc_disable_one_unused_chan(FILE* fp,
fprintf(fp,
"##################################################\n");
fprintf(fp,
"### Disable Timing for an %s[%d][%d] ###\n",
"### Disable Timing for an flag 1 %s[%d][%d] ###\n",
convert_chan_type_to_string(rr_chan.get_type()),
x, y);
fprintf(fp,
@ -833,7 +833,7 @@ void verilog_generate_sdc_disable_one_unused_chan(FILE* fp,
fprintf(fp,
"##################################################\n");
fprintf(fp,
"### Disable Timing for an %s[%d][%d] ###\n",
"### Disable Timing for an flag 2 %s[%d][%d] ###\n",
convert_chan_type_to_string(chan_type),
x, y);
fprintf(fp,
@ -1252,6 +1252,9 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp,
if (FALSE == is_rr_node_to_be_disable_for_analysis(cur_sb_info->chan_rr_node[side][itrack])) {
continue;
}
if (0 == cur_sb_info->chan_rr_node[side][itrack]->fan_in) {
continue;
}
fprintf(fp, "set_disable_timing ");
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(cur_sb_info));
@ -1266,6 +1269,9 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp,
if (FALSE == is_rr_node_to_be_disable_for_analysis(cur_sb_info->opin_rr_node[side][inode])) {
continue;
}
if (0 == cur_sb_info->opin_rr_node[side][inode]->fan_in) {
continue;
}
fprintf(fp, "set_disable_timing ");
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(cur_sb_info));
@ -1299,7 +1305,7 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp,
fprintf(fp,
"##################################################\n");
fprintf(fp,
"### Disable Timing for an %s[%d][%d] ###\n",
"### Disable Timing for an unused %s[%d][%d] ###\n",
convert_cb_type_to_string(cur_cb_info->type),
cur_cb_info->x, cur_cb_info->y);
fprintf(fp,
@ -1320,6 +1326,9 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp,
if (FALSE == is_rr_node_to_be_disable_for_analysis(cur_cb_info->ipin_rr_node[side][inode])) {
continue;
}
if (0 == cur_cb_info->ipin_rr_node[side][inode]->fan_in) {
continue;
}
fprintf(fp, "set_disable_timing ");
fprintf(fp, "%s/",
gen_verilog_one_cb_instance_name(cur_cb_info));
@ -1583,7 +1592,8 @@ void verilog_generate_sdc_disable_one_unused_block(FILE* fp,
for (inode = 0; inode < cur_phy_pb->rr_graph->num_rr_nodes; inode++) {
/* Focus on the SOURCE and SINK rr_nodes */
if ((SOURCE != cur_phy_pb->rr_graph->rr_node[inode].type)
&& (SINK != cur_phy_pb->rr_graph->rr_node[inode].type)) {
&& (SINK != cur_phy_pb->rr_graph->rr_node[inode].type)
&& (NULL == cur_phy_pb->rr_graph->rr_node[inode].pb_graph_pin)) {
continue;
}
/* Identify if the rr_node is usused */

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c
View File

@ -120,7 +120,7 @@ void dump_verilog_one_sb_chan_pin(FILE* fp,
get_rr_node_side_and_index_in_sb_info(cur_rr_node,
*cur_sb_info,
port_type, &side, &track_idx);
get_chan_rr_node_coorindate_in_sb_info(*cur_sb_info, side,
get_chan_rr_node_coordinate_in_sb_info(*cur_sb_info, side,
&(chan_rr_type),
&x_start, &y_start);
assert (chan_rr_type == cur_rr_node->type);