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add options to specify output directory of SB XML

This commit is contained in:
tangxifan 2019-05-28 15:19:10 -06:00
parent 6b51b42ee7
commit ca363da30c
12 changed files with 66 additions and 13 deletions
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1
vpr7_x2p/vpr/SRC/base/OptionTokens.c
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@ -62,6 +62,7 @@ struct s_TokenPair OptionBaseTokenList[] = {
{ "fpga_x2p_signal_density_weight", OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT }, /* The weight of signal density */
{ "fpga_x2p_sim_window_size", OT_FPGA_X2P_SIM_WINDOW_SIZE }, /* Window size in determining number of clock cycles in simulation */
{ "fpga_x2p_compact_routing_hierarchy", OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY }, /* use a compact routing hierarchy in SPICE/Verilog generation */
{ "fpga_x2p_output_sb_xml", OT_FPGA_X2P_OUTPUT_SB_XML }, /* use a compact routing hierarchy in SPICE/Verilog generation */
/* Xifan TANG: FPGA SPICE Support */
{ "fpga_spice", OT_FPGA_SPICE },/* Xifan TANG: SPICE Model Support, turn on the functionality*/
{ "fpga_spice_dir", OT_FPGA_SPICE_DIR },/* Xifan TANG: SPICE Model Support, directory of spice netlists*/

1
vpr7_x2p/vpr/SRC/base/OptionTokens.h
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@ -79,6 +79,7 @@ enum e_OptionBaseToken {
OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT, /* The weight of signal density in determining number of clock cycles in simulation */
OT_FPGA_X2P_SIM_WINDOW_SIZE, /* Window size in determining number of clock cycles in simulation */
OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY, /* use a compact routing hierarchy in SPICE/Verilog generation */
OT_FPGA_X2P_OUTPUT_SB_XML, /* output switch blocks to XML files */
/* Xifan TANG: FPGA SPICE Support */
OT_FPGA_SPICE, /* Xifan TANG: FPGA SPICE Model Support */
OT_FPGA_SPICE_DIR, /* Xifan TANG: FPGA SPICE Model Support */

3
vpr7_x2p/vpr/SRC/base/ReadOptions.c
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@ -484,6 +484,9 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
case OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY:
/* use a compact routing hierarchy in SPICE/Verilog generation */
return Args;
case OT_FPGA_X2P_OUTPUT_SB_XML:
/* Read the file prefix to output SB XML files */
return ReadString(Args, &Options->sb_xml_dir);
/* Xifan TANG: FPGA SPICE Model Options*/
case OT_FPGA_SPICE:
return Args;

1
vpr7_x2p/vpr/SRC/base/ReadOptions.h
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@ -94,6 +94,7 @@ struct s_options {
/* Xifan TANG: signal weight in FPGA_SPICE simulation */
float fpga_spice_signal_density_weight;
float fpga_spice_sim_window_size;
char* sb_xml_dir;
/* Xifan TANG: SPICE Support*/
char* spice_dir;

8
vpr7_x2p/vpr/SRC/base/SetupVPR.c
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@ -1241,6 +1241,14 @@ static void SetupFpgaSpiceOpts(t_options Options,
fpga_spice_opts->compact_routing_hierarchy = TRUE;
}
/* Check if user wants to use a compact routing hierarchy */
fpga_spice_opts->output_sb_xml = FALSE;
fpga_spice_opts->sb_xml_dir = NULL;
if (Options.Count[OT_FPGA_X2P_OUTPUT_SB_XML]) {
fpga_spice_opts->output_sb_xml = TRUE;
fpga_spice_opts->sb_xml_dir = Options.sb_xml_dir;
}
/* Decide if we need to do FPGA-SPICE */
fpga_spice_opts->do_fpga_spice = FALSE;
if (( TRUE == fpga_spice_opts->SpiceOpts.do_spice)

1
vpr7_x2p/vpr/SRC/base/vpr_api.c
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@ -171,6 +171,7 @@ void vpr_print_usage(void) {
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_signal_density_weight <float>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_sim_window_size <float>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_compact_routing_hierarchy\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_output_sb_xml <directory_path_output_switch_block_XML>\n");
vpr_printf(TIO_MESSAGE_INFO, "SPICE Support Options:\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_dir <directory_path_output_spice_netlists>\n");

3
vpr7_x2p/vpr/SRC/base/vpr_types.h
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@ -1284,6 +1284,9 @@ struct s_fpga_spice_opts {
/* Signal Density */
float signal_density_weight;
float sim_window_size;
/* SB XML file prefix */
boolean output_sb_xml;
char* sb_xml_dir;
};
/* Power estimation options */

5
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c
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@ -1400,7 +1400,10 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup,
/* Assign Gobal variable: build the Routing Resource Channels */
device_rr_chan = build_device_rr_chan(num_rr_nodes, rr_node, rr_node_indices, Arch->num_segments, rr_indexed_data);
device_rr_switch_block = build_device_rr_switch_blocks(num_rr_nodes, rr_node, rr_node_indices, Arch->num_segments, rr_indexed_data);
device_rr_switch_block = build_device_rr_switch_blocks(vpr_setup.FPGA_SPICE_Opts.output_sb_xml,
vpr_setup.FPGA_SPICE_Opts.sb_xml_dir,
num_rr_nodes, rr_node, rr_node_indices,
Arch->num_segments, rr_indexed_data);
/* Rotatable will be done in the next step
identify_rotatable_switch_blocks();

30
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
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@ -1197,7 +1197,8 @@ RRSwitchBlock rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
* Each switch block in the FPGA fabric will be an instance of these modules.
* We maintain a map from each instance to each module
*/
DeviceRRSwitchBlock build_device_rr_switch_blocks(int LL_num_rr_nodes, t_rr_node* LL_rr_node,
DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* sb_xml_dir,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices, int num_segments,
t_rr_indexed_data* LL_rr_indexed_data) {
/* Create an object */
@ -1231,22 +1232,45 @@ DeviceRRSwitchBlock build_device_rr_switch_blocks(int LL_num_rr_nodes, t_rr_node
"Detect %d independent switch blocks from %d switch blocks.\n",
LL_device_rr_switch_block.get_num_unique_mirror(), (nx + 1) * (ny + 1) );
/* Create directory if needed */
if (TRUE == output_sb_xml) {
create_dir_path(sb_xml_dir);
}
for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) {
RRSwitchBlock rr_sb = LL_device_rr_switch_block.get_switch_block(ix, iy);
RRSwitchBlock rotated_rr_sb = rotate_rr_switch_block_for_mirror(sb_range, rr_sb);
DeviceCoordinator sb_coordinator = rr_sb.get_coordinator();
LL_device_rr_switch_block.add_rotatable_mirror(sb_coordinator, rotated_rr_sb);
if (TRUE == output_sb_xml) {
std::string fname_prefix(sb_xml_dir);
/* Add slash if needed */
if ('/' != fname_prefix.back()) {
fname_prefix += "/";
}
fname_prefix += "rotated_";
write_rr_switch_block_to_xml(fname_prefix, rotated_rr_sb);
}
}
}
/* Skip rotating mirror searching */
vpr_printf(TIO_MESSAGE_INFO,
"Detect %d rotatable unique switch blocks from %d switch blocks.\n",
LL_device_rr_switch_block.get_num_rotatable_mirror(), (nx + 1) * (ny + 1) );
write_device_rr_switch_block_to_xml(LL_device_rr_switch_block);
if (TRUE == output_sb_xml) {
write_device_rr_switch_block_to_xml(sb_xml_dir, LL_device_rr_switch_block);
/* Skip rotating mirror searching */
vpr_printf(TIO_MESSAGE_INFO,
"Output XML description of Switch Blocks to %s.\n",
sb_xml_dir);
}
return LL_device_rr_switch_block;
}

3
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h
View File

@ -14,7 +14,8 @@ DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node,
* Each switch block in the FPGA fabric will be an instance of these modules.
* We maintain a map from each instance to each module
*/
DeviceRRSwitchBlock build_device_rr_switch_blocks(int LL_num_rr_nodes, t_rr_node* LL_rr_node,
DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* sb_xml_dir,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices, int num_segments,
t_rr_indexed_data* LL_rr_indexed_data);

19
vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.cpp
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@ -11,14 +11,15 @@
#include "fpga_x2p_utils.h"
void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb) {
/* Create a file handler*/
std::fstream fp;
std::string fname = fname_prefix;
/* Prepare file name */
std::string fname(fname_prefix);
fname += rr_sb.gen_verilog_instance_name();
fname += ".xml";
printf("Output SB XML: %s\n", fname.c_str());
vpr_printf(TIO_MESSAGE_INFO, "Output SB XML: %s\n", fname.c_str());
/* Create a file handler*/
std::fstream fp;
/* Open a file */
fp.open(fname, std::fstream::out | std::fstream::trunc);
@ -94,8 +95,14 @@ void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb
}
/* Output each rr_switch_block to a XML file */
void write_device_rr_switch_block_to_xml(DeviceRRSwitchBlock& LL_device_rr_switch_block) {
std::string fname_prefix("/var/tmp/xtang/sb_xml/");
void write_device_rr_switch_block_to_xml(char* sb_xml_dir,
DeviceRRSwitchBlock& LL_device_rr_switch_block) {
std::string fname_prefix(sb_xml_dir);
/* Add slash if needed */
if ('/' != fname_prefix.back()) {
fname_prefix += '/';
}
DeviceCoordinator sb_range = LL_device_rr_switch_block.get_switch_block_range();
/* For each switch block, an XML file will be outputted */

4
vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.h
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@ -1,8 +1,8 @@
#ifndef WRITE_RR_BLOCKS_H
#define WRITE_RR_BLOCKS_H
void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb) {
void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb);
void write_device_rr_switch_block_to_xml(DeviceRRSwitchBlock& LL_device_rr_switch_block);
void write_device_rr_switch_block_to_xml(char* sb_xml_dir, DeviceRRSwitchBlock& LL_device_rr_switch_block);
#endif