add options to specify output directory of SB XML
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6b51b42ee7
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@ -62,6 +62,7 @@ struct s_TokenPair OptionBaseTokenList[] = {
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{ "fpga_x2p_signal_density_weight", OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT }, /* The weight of signal density */
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{ "fpga_x2p_sim_window_size", OT_FPGA_X2P_SIM_WINDOW_SIZE }, /* Window size in determining number of clock cycles in simulation */
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{ "fpga_x2p_compact_routing_hierarchy", OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY }, /* use a compact routing hierarchy in SPICE/Verilog generation */
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{ "fpga_x2p_output_sb_xml", OT_FPGA_X2P_OUTPUT_SB_XML }, /* use a compact routing hierarchy in SPICE/Verilog generation */
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/* Xifan TANG: FPGA SPICE Support */
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{ "fpga_spice", OT_FPGA_SPICE },/* Xifan TANG: SPICE Model Support, turn on the functionality*/
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{ "fpga_spice_dir", OT_FPGA_SPICE_DIR },/* Xifan TANG: SPICE Model Support, directory of spice netlists*/
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@ -79,6 +79,7 @@ enum e_OptionBaseToken {
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OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT, /* The weight of signal density in determining number of clock cycles in simulation */
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OT_FPGA_X2P_SIM_WINDOW_SIZE, /* Window size in determining number of clock cycles in simulation */
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OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY, /* use a compact routing hierarchy in SPICE/Verilog generation */
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OT_FPGA_X2P_OUTPUT_SB_XML, /* output switch blocks to XML files */
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/* Xifan TANG: FPGA SPICE Support */
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OT_FPGA_SPICE, /* Xifan TANG: FPGA SPICE Model Support */
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OT_FPGA_SPICE_DIR, /* Xifan TANG: FPGA SPICE Model Support */
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@ -484,6 +484,9 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
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case OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY:
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/* use a compact routing hierarchy in SPICE/Verilog generation */
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return Args;
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case OT_FPGA_X2P_OUTPUT_SB_XML:
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/* Read the file prefix to output SB XML files */
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return ReadString(Args, &Options->sb_xml_dir);
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/* Xifan TANG: FPGA SPICE Model Options*/
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case OT_FPGA_SPICE:
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return Args;
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@ -94,6 +94,7 @@ struct s_options {
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/* Xifan TANG: signal weight in FPGA_SPICE simulation */
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float fpga_spice_signal_density_weight;
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float fpga_spice_sim_window_size;
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char* sb_xml_dir;
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/* Xifan TANG: SPICE Support*/
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char* spice_dir;
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@ -1241,6 +1241,14 @@ static void SetupFpgaSpiceOpts(t_options Options,
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fpga_spice_opts->compact_routing_hierarchy = TRUE;
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}
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/* Check if user wants to use a compact routing hierarchy */
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fpga_spice_opts->output_sb_xml = FALSE;
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fpga_spice_opts->sb_xml_dir = NULL;
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if (Options.Count[OT_FPGA_X2P_OUTPUT_SB_XML]) {
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fpga_spice_opts->output_sb_xml = TRUE;
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fpga_spice_opts->sb_xml_dir = Options.sb_xml_dir;
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}
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/* Decide if we need to do FPGA-SPICE */
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fpga_spice_opts->do_fpga_spice = FALSE;
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if (( TRUE == fpga_spice_opts->SpiceOpts.do_spice)
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@ -171,6 +171,7 @@ void vpr_print_usage(void) {
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vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_signal_density_weight <float>\n");
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vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_sim_window_size <float>\n");
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vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_compact_routing_hierarchy\n");
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vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_output_sb_xml <directory_path_output_switch_block_XML>\n");
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vpr_printf(TIO_MESSAGE_INFO, "SPICE Support Options:\n");
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vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice\n");
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vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_dir <directory_path_output_spice_netlists>\n");
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@ -1284,6 +1284,9 @@ struct s_fpga_spice_opts {
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/* Signal Density */
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float signal_density_weight;
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float sim_window_size;
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/* SB XML file prefix */
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boolean output_sb_xml;
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char* sb_xml_dir;
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};
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/* Power estimation options */
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@ -1400,7 +1400,10 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup,
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/* Assign Gobal variable: build the Routing Resource Channels */
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device_rr_chan = build_device_rr_chan(num_rr_nodes, rr_node, rr_node_indices, Arch->num_segments, rr_indexed_data);
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device_rr_switch_block = build_device_rr_switch_blocks(num_rr_nodes, rr_node, rr_node_indices, Arch->num_segments, rr_indexed_data);
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device_rr_switch_block = build_device_rr_switch_blocks(vpr_setup.FPGA_SPICE_Opts.output_sb_xml,
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vpr_setup.FPGA_SPICE_Opts.sb_xml_dir,
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num_rr_nodes, rr_node, rr_node_indices,
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Arch->num_segments, rr_indexed_data);
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/* Rotatable will be done in the next step
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identify_rotatable_switch_blocks();
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@ -1197,7 +1197,8 @@ RRSwitchBlock rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
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* Each switch block in the FPGA fabric will be an instance of these modules.
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* We maintain a map from each instance to each module
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*/
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DeviceRRSwitchBlock build_device_rr_switch_blocks(int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* sb_xml_dir,
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int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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t_ivec*** LL_rr_node_indices, int num_segments,
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t_rr_indexed_data* LL_rr_indexed_data) {
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/* Create an object */
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@ -1231,22 +1232,45 @@ DeviceRRSwitchBlock build_device_rr_switch_blocks(int LL_num_rr_nodes, t_rr_node
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"Detect %d independent switch blocks from %d switch blocks.\n",
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LL_device_rr_switch_block.get_num_unique_mirror(), (nx + 1) * (ny + 1) );
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/* Create directory if needed */
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if (TRUE == output_sb_xml) {
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create_dir_path(sb_xml_dir);
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}
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for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) {
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for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) {
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RRSwitchBlock rr_sb = LL_device_rr_switch_block.get_switch_block(ix, iy);
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RRSwitchBlock rotated_rr_sb = rotate_rr_switch_block_for_mirror(sb_range, rr_sb);
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DeviceCoordinator sb_coordinator = rr_sb.get_coordinator();
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LL_device_rr_switch_block.add_rotatable_mirror(sb_coordinator, rotated_rr_sb);
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if (TRUE == output_sb_xml) {
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std::string fname_prefix(sb_xml_dir);
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/* Add slash if needed */
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if ('/' != fname_prefix.back()) {
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fname_prefix += "/";
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}
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fname_prefix += "rotated_";
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write_rr_switch_block_to_xml(fname_prefix, rotated_rr_sb);
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}
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}
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}
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/* Skip rotating mirror searching */
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vpr_printf(TIO_MESSAGE_INFO,
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"Detect %d rotatable unique switch blocks from %d switch blocks.\n",
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LL_device_rr_switch_block.get_num_rotatable_mirror(), (nx + 1) * (ny + 1) );
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write_device_rr_switch_block_to_xml(LL_device_rr_switch_block);
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if (TRUE == output_sb_xml) {
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write_device_rr_switch_block_to_xml(sb_xml_dir, LL_device_rr_switch_block);
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/* Skip rotating mirror searching */
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vpr_printf(TIO_MESSAGE_INFO,
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"Output XML description of Switch Blocks to %s.\n",
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sb_xml_dir);
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}
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return LL_device_rr_switch_block;
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}
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@ -14,7 +14,8 @@ DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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* Each switch block in the FPGA fabric will be an instance of these modules.
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* We maintain a map from each instance to each module
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*/
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DeviceRRSwitchBlock build_device_rr_switch_blocks(int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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DeviceRRSwitchBlock build_device_rr_switch_blocks(boolean output_sb_xml, char* sb_xml_dir,
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int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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t_ivec*** LL_rr_node_indices, int num_segments,
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t_rr_indexed_data* LL_rr_indexed_data);
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@ -11,14 +11,15 @@
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#include "fpga_x2p_utils.h"
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void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb) {
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/* Create a file handler*/
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std::fstream fp;
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std::string fname = fname_prefix;
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/* Prepare file name */
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std::string fname(fname_prefix);
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fname += rr_sb.gen_verilog_instance_name();
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fname += ".xml";
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printf("Output SB XML: %s\n", fname.c_str());
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vpr_printf(TIO_MESSAGE_INFO, "Output SB XML: %s\n", fname.c_str());
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/* Create a file handler*/
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std::fstream fp;
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/* Open a file */
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fp.open(fname, std::fstream::out | std::fstream::trunc);
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@ -94,8 +95,14 @@ void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb
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}
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/* Output each rr_switch_block to a XML file */
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void write_device_rr_switch_block_to_xml(DeviceRRSwitchBlock& LL_device_rr_switch_block) {
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std::string fname_prefix("/var/tmp/xtang/sb_xml/");
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void write_device_rr_switch_block_to_xml(char* sb_xml_dir,
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DeviceRRSwitchBlock& LL_device_rr_switch_block) {
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std::string fname_prefix(sb_xml_dir);
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/* Add slash if needed */
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if ('/' != fname_prefix.back()) {
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fname_prefix += '/';
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}
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DeviceCoordinator sb_range = LL_device_rr_switch_block.get_switch_block_range();
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/* For each switch block, an XML file will be outputted */
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@ -1,8 +1,8 @@
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#ifndef WRITE_RR_BLOCKS_H
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#define WRITE_RR_BLOCKS_H
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void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb) {
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void write_rr_switch_block_to_xml(std::string fname_prefix, RRSwitchBlock& rr_sb);
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void write_device_rr_switch_block_to_xml(DeviceRRSwitchBlock& LL_device_rr_switch_block);
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void write_device_rr_switch_block_to_xml(char* sb_xml_dir, DeviceRRSwitchBlock& LL_device_rr_switch_block);
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#endif
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