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bug fixed for the tileable RR graph generator for heterogeneous blocks

This commit is contained in:
tangxifan 2019-07-11 21:02:09 -06:00
parent 75ff2e904e
commit cffdebd912
2 changed files with 67 additions and 44 deletions
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107
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp
View File

@ -244,7 +244,7 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator
rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y();
rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1;
rr_graph->rr_node[*cur_node_id].ptc_num = opin_list[pin];
rr_graph->rr_node[*cur_node_id].capacity = 1;
rr_graph->rr_node[*cur_node_id].occ = 0;
@ -253,6 +253,15 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator
/* Switch info */
rr_graph->rr_node[*cur_node_id].driver_switch = delayless_switch;
/* fill fast look-up table */
/* If height > 1, we will update fast lookup to twice:
* 1. for the x, y + height. This enable fast fast look-up for node collection in rr_gsb
* 2. for the x, y. This enables fast lookup for SOURCE and SINK nodes drive/driven by the node
*/
load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
rr_graph->rr_node[*cur_node_id].type,
rr_graph->rr_node[*cur_node_id].xlow,
rr_graph->rr_node[*cur_node_id].ylow + height,
rr_graph->rr_node[*cur_node_id].ptc_num);
load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
rr_graph->rr_node[*cur_node_id].type,
rr_graph->rr_node[*cur_node_id].xlow,
@ -269,7 +278,7 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator
rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y();
rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1;
rr_graph->rr_node[*cur_node_id].ptc_num = ipin_list[pin];
rr_graph->rr_node[*cur_node_id].capacity = 1;
rr_graph->rr_node[*cur_node_id].occ = 0;
@ -278,6 +287,15 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator
/* Switch info */
rr_graph->rr_node[*cur_node_id].driver_switch = wire_to_ipin_switch;
/* fill fast look-up table */
/* If height > 1, we will update fast lookup to twice:
* 1. for the x, y + height. This enable fast fast look-up for node collection in rr_gsb
* 2. for the x, y. This enables fast lookup for SOURCE and SINK nodes drive/driven by the node
*/
load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
rr_graph->rr_node[*cur_node_id].type,
rr_graph->rr_node[*cur_node_id].xlow,
rr_graph->rr_node[*cur_node_id].ylow + height,
rr_graph->rr_node[*cur_node_id].ptc_num);
load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
rr_graph->rr_node[*cur_node_id].type,
rr_graph->rr_node[*cur_node_id].xlow,
@ -289,46 +307,44 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator
} /* End of side enumeration */
} /* End of height enumeration */
/* Walk through the height of each grid,
/* No need to Walk through the height of each grid,
* get pins and configure the rr_nodes */
for (int height = 0; height < cur_grid.type->height; ++height) {
/* Set a SOURCE or a SINK rr_node for each class */
for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) {
/* Set a SINK rr_node for the OPIN */
if ( DRIVER == cur_grid.type->class_inf[iclass].type) {
rr_graph->rr_node[*cur_node_id].type = SOURCE;
}
if ( RECEIVER == cur_grid.type->class_inf[iclass].type) {
rr_graph->rr_node[*cur_node_id].type = SINK;
}
rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y();
rr_graph->rr_node[*cur_node_id].ptc_num = iclass;
/* FIXME: need to confirm if the capacity should be the number of pins in this class*/
rr_graph->rr_node[*cur_node_id].capacity = cur_grid.type->class_inf[iclass].num_pins;
rr_graph->rr_node[*cur_node_id].occ = 0;
/* cost index is a FIXED value for SOURCE and SINK */
if (SOURCE == rr_graph->rr_node[*cur_node_id].type) {
rr_graph->rr_node[*cur_node_id].cost_index = SOURCE_COST_INDEX;
}
if (SINK == rr_graph->rr_node[*cur_node_id].type) {
rr_graph->rr_node[*cur_node_id].cost_index = SINK_COST_INDEX;
}
/* Switch info */
rr_graph->rr_node[*cur_node_id].driver_switch = delayless_switch;
/* TODO: should we set pb_graph_pin here? */
/* fill fast look-up table */
load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
rr_graph->rr_node[*cur_node_id].type,
rr_graph->rr_node[*cur_node_id].xlow,
rr_graph->rr_node[*cur_node_id].ylow,
rr_graph->rr_node[*cur_node_id].ptc_num);
/* Update node counter */
(*cur_node_id)++;
} /* End of height enumeration */
} /* End of pin_class enumeration */
/* Set a SOURCE or a SINK rr_node for each class */
for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) {
/* Set a SINK rr_node for the OPIN */
if ( DRIVER == cur_grid.type->class_inf[iclass].type) {
rr_graph->rr_node[*cur_node_id].type = SOURCE;
}
if ( RECEIVER == cur_grid.type->class_inf[iclass].type) {
rr_graph->rr_node[*cur_node_id].type = SINK;
}
rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1;
rr_graph->rr_node[*cur_node_id].ptc_num = iclass;
/* FIXME: need to confirm if the capacity should be the number of pins in this class*/
rr_graph->rr_node[*cur_node_id].capacity = cur_grid.type->class_inf[iclass].num_pins;
rr_graph->rr_node[*cur_node_id].occ = 0;
/* cost index is a FIXED value for SOURCE and SINK */
if (SOURCE == rr_graph->rr_node[*cur_node_id].type) {
rr_graph->rr_node[*cur_node_id].cost_index = SOURCE_COST_INDEX;
}
if (SINK == rr_graph->rr_node[*cur_node_id].type) {
rr_graph->rr_node[*cur_node_id].cost_index = SINK_COST_INDEX;
}
/* Switch info */
rr_graph->rr_node[*cur_node_id].driver_switch = delayless_switch;
/* TODO: should we set pb_graph_pin here? */
/* fill fast look-up table */
load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
rr_graph->rr_node[*cur_node_id].type,
rr_graph->rr_node[*cur_node_id].xlow,
rr_graph->rr_node[*cur_node_id].ylow,
rr_graph->rr_node[*cur_node_id].ptc_num);
/* Update node counter */
(*cur_node_id)++;
} /* End of height enumeration */
return;
}
@ -640,7 +656,7 @@ void load_rr_nodes_basic_info(t_rr_graph* rr_graph,
|| (OPIN == rr_graph->rr_node[inode].type)
|| (IPIN == rr_graph->rr_node[inode].type));
assert (rr_graph->rr_node[inode].xlow == rr_graph->rr_node[inode].xhigh);
assert (rr_graph->rr_node[inode].ylow == rr_graph->rr_node[inode].yhigh);
assert (rr_graph->rr_node[inode].ylow + grids[rr_graph->rr_node[inode].xlow][rr_graph->rr_node[inode].ylow].type->height - 1 == rr_graph->rr_node[inode].yhigh);
}
}
@ -993,6 +1009,13 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types,
***********************************************************************/
alloc_rr_graph_fast_lookup(device_size, &rr_graph);
/* FIXME: DEBUG CODES TO BE REMOVED
vpr_printf(TIO_MESSAGE_INFO, "estimated %lu SOURCE NODE.\n", num_rr_nodes_per_type[SOURCE]);
vpr_printf(TIO_MESSAGE_INFO, "estimated %lu SINK NODE.\n", num_rr_nodes_per_type[SINK]);
vpr_printf(TIO_MESSAGE_INFO, "estimated %lu OPIN NODE.\n", num_rr_nodes_per_type[OPIN]);
vpr_printf(TIO_MESSAGE_INFO, "estimated %lu IPIN NODE.\n", num_rr_nodes_per_type[IPIN]);
*/
load_rr_nodes_basic_info(&rr_graph, device_size, grids, device_chan_width, segment_infs,
wire_to_ipin_switch, delayless_switch);

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -373,7 +373,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
fprintf(fp, ".%s(",
pb_type_port->spice_model_port->lib_name);
}
if (1 < pb_type_port_num_pins) {
if (1 < pb_type_port->num_pins) {
fprintf(fp, "{");
}
for (int ipin = 0; ipin < pb_type_port->num_pins; ++ipin) {
@ -383,7 +383,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin));
}
if (1 < pb_type_port_num_pins) {
if (1 < pb_type_port->num_pins) {
fprintf(fp, "}");
}
if (TRUE == dump_explicit_port_map) {