Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb

Conflicts:
	vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
This commit is contained in:
tangxifan 2019-06-13 16:32:39 -06:00
commit 5f61cd8876
3 changed files with 144 additions and 11 deletions

View File

@ -2,6 +2,9 @@
# Regression test version 1.0
# Set variables
my_pwd=$PWD
fpga_flow_scripts=${my_pwd}/fpga_flow/scripts
vpr_path=${my_pwd}/vpr7_x2p/vpr
benchmark="test_modes"
include_netlists="_include_netlists.v"
compiled_file="compiled_$benchmark"
@ -9,16 +12,16 @@ tb_formal_postfix="_top_formal_verification_random_tb"
verilog_output_dirname="${benchmark}_Verilog"
log_file="${benchmark}_sim.log"
cd fpga_flow/scripts
perl rewrite_path_in_file.pl -i ../arch/template/k6_N10_sram_chain_HC_template.xml
perl rewrite_path_in_file.pl -i ../../vpr7_x2p/vpr/regression_verilog.sh
perl rewrite_path_in_file.pl -i ../../vpr7_x2p/vpr/VerilogNetlists/ff.v
cd $fpga_flow_scripts
cd -
perl rewrite_path_in_file.pl -i $vpr_path/regression_verilog.sh
perl rewrite_path_in_file.pl -i $vpr_path/VerilogNetlists/ff.v
cd $my_pwd
# Move to vpr folder
cd vpr7_x2p/vpr
cd $vpr_path
# Remove former log file
rm -f $log_file
@ -34,14 +37,14 @@ if ["$result" = ""]; then
result=`grep "Failed" $log_file`
if ["$result" = ""]; then
echo "Unexpected error, Verification didn't run"
cd -
cd $my_pwd
exit 1
else
echo "Verification failed"
cd -
cd $my_pwd
exit 2
fi
else
echo "Verification succeed"
cd -
cd $my_pwd
fi

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@ -0,0 +1,122 @@
#!usr/bin/perl -w
use strict;
use Cwd;
#use Shell;
use FileHandle;
#Use the time
use Time::gmtime;
my $arch_file;
my $new_arch_file;
my $overwrite = "TRUE";
my $keyword = "OPENFPGAPATHKEYWORD";
my $folder_top = "OpenFPGA";
sub print_usage()
{
print "Usage:\n";
print " perl <script_name.pl> [-options]\n";
print " Options:(Mandatory!)\n";
print " -i <input_architecture_file_path>\n";
print " Options:(Optional)\n";
print " -o <output_architecture_file_path>\n";
print "\n";
return;
}
sub opts_read()
{
if ($#ARGV == -1){
print "Error: Not enough input argument!\n";
&print_usage();
exit(1);
} else {
for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++){
if ("-i" eq $ARGV[$iargv]){
$arch_file = $ARGV[$iargv+1];
$iargv++;
} elsif ("-o" eq $ARGV[$iargv]){
$new_arch_file = $ARGV[$iargv+1];
$overwrite = "FALSE";
$iargv++;
} else {
die "WRONG ARGUMENT";
}
}
}
return;
}
sub rewriting_required_check($)
{
my ($arch) = @_;
open(F, $arch);
my @lines=<F>;
close F;
my $grep_result = grep ($keyword, @lines);
if($grep_result >= 1){
print "Rewrite needed\n";
return 1;
} else {
print "Rewrite NOT needed\n";
return 0;
}
}
sub save_original($)
{
my ($template) = @_;
my $renamed_template = "$template".".bak";
rename($template, $renamed_template);
return $renamed_template;
}
sub findPath(){
my $path;
my $dir = cwd;
my @folders = split("/", $dir);
for(my $count = 0; $count < ($#folders -1); $count++){
print "path fragment = $folders[$count]\n";
if($folders[$count] eq ""){
} else {
$path = "$path"."/"."$folders[$count]";
if($folders[$count] eq $folder_top){
print "$path\n";
return $path;
}
}
}
die "ERROR: Script launched from the outside of the $folder_top folder!\n";
}
sub rewrite_file($ $)
{
my ($arch, $template) = @_;
my $myPath = &findPath();
open(IN, '<'.$template);
open(OUT, '>'.$arch);
while(<IN>){
$_ =~ s/$keyword/$myPath/g;
print OUT $_;
}
return;
}
sub main()
{
&opts_read();
my $rewrite_needed = &rewriting_required_check($arch_file);
if($rewrite_needed == 1){
if($overwrite eq "true"){
my $template_file = &save_original($arch_file);
&rewrite_file($arch_file, $template_file);
} else {
&rewrite_file($new_arch_file, $arch_file);
}
}
return;
}
&main();
exit(1);

View File

@ -9,11 +9,13 @@ verilog_output_dirname="${benchmark}_Verilog"
verilog_output_dirpath="$PWD"
tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
# VPR critical inputs
arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml"
blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
vpr_route_chan_width="200"
fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
# Step A: Make sure a clean start
# Recompile if needed
@ -22,7 +24,13 @@ vpr_route_chan_width="200"
# Remove previous designs
rm -rf $verilog_output_dirpath/$verilog_output_dirname
mkdir ${OpenFPGA_path}/fpga_flow/arch/generated
cd $fpga_flow_scripts
perl arch_rewrite.pl -i $template_arch_xml_file -o $arch_xml_file
cd -
# Run VPR
#valgrind
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis #--fpga_x2p_compact_routing_hierarchy
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy