Error correction in memory generation for pb_types without modes

2019-06-13 15:34:25 -06:00 · 2019-06-13 15:34:25 -06:00 · 15b4cc9ecb
parent bf13c1f731
commit 15b4cc9ecb
1 changed files with 2 additions and 0 deletions
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
@ -418,8 +418,10 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
  temp_iopad_lsb = 0;

  /* Local wires for memory configurations */
+  if (0 < temp_conf_bits_msb) { 
  dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, 
                                              0, temp_conf_bits_msb - 1); 
+  }


  /* Quote all the sub blocks*/