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Add possibility to choose default value for initialization

This commit is contained in:
Aur??Lien ALACCHI 2018-12-06 15:34:14 -07:00
parent b6bb419e1d
commit eebdf7cb10
1 changed files with 3 additions and 2 deletions
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5
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_submodules.c
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@ -101,8 +101,9 @@ void dump_verilog_submodule_init_sim(FILE* fp,
fprintf(fp, "initial begin\n");
for (iport = 0; iport < num_input_port; iport++) {
fprintf(fp, " $signal_force(\"%s\", \"0\", 0, 1, , 1);\n",
input_port[iport]->prefix);
fprintf(fp, " $signal_force(\"%s\", %d, 0, 1, , 1);\n",
input_port[iport]->prefix,
input_port[iport]->default_val);
}
fprintf(fp, "end\n");