Add possibility to choose default value for initialization
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@ -101,8 +101,9 @@ void dump_verilog_submodule_init_sim(FILE* fp,
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fprintf(fp, "initial begin\n");
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for (iport = 0; iport < num_input_port; iport++) {
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fprintf(fp, " $signal_force(\"%s\", \"0\", 0, 1, , 1);\n",
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input_port[iport]->prefix);
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fprintf(fp, " $signal_force(\"%s\", %d, 0, 1, , 1);\n",
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input_port[iport]->prefix,
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input_port[iport]->default_val);
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}
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fprintf(fp, "end\n");
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