add rr_chan obj
This commit is contained in:
tangxifan
parent
9c05a4fb0a
commit
3313eac23b
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@ -31,7 +31,7 @@ find_package(Readline REQUIRED)
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#Collect the source files
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file(GLOB_RECURSE EXEC_SOURCES SRC/main.c)
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file(GLOB_RECURSE EXEC_SOURCES_SHELL SRC/shell_main.c)
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file(GLOB_RECURSE LIB_SOURCES SRC/*/*.c SRC/*/*/*.c)
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file(GLOB_RECURSE LIB_SOURCES SRC/*/*.c SRC/*/*/*.c SRC/*/*.cpp SRC/*/*/*.cpp)
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file(GLOB_RECURSE LIB_HEADERS SRC/*/*.h SRC/*/*/*.h)
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files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
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@ -0,0 +1,270 @@
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#include <cassert>
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#include "rr_chan.h"
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/* Member Functions of Class RRChan */
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/* accessors */
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t_rr_type RRChan::get_type() const {
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return type_;
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}
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/* get the number of tracks in this channel */
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size_t RRChan::get_chan_width() const {
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return nodes_.size();
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}
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/* get the track_id of a node */
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int RRChan::get_node_track_id(t_rr_node* node) const {
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/* if the given node is NULL, we return an invalid id */
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if (NULL == node) {
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return -1; /* FIXME: use a strong id!!! */
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}
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/* check each member and return if we find a match in content */
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for (size_t inode = 0; inode < nodes_.size(); ++inode) {
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if (node == nodes_[inode]) {
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return inode;
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}
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}
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return -1;
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}
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/* get the rr_node with the track_id */
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t_rr_node* RRChan::get_node(size_t track_num) const {
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if ( false == valid_node_id(track_num) ) {
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return NULL;
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}
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return nodes_[track_num];
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}
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/* get the segment id of a node */
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int RRChan::get_node_segment(t_rr_node* node) const {
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int node_id = get_node_track_id(node);
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if ( false == valid_node_id(node_id)) {
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return -1;
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}
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return get_node_segment(node_id);
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}
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/* get the segment id of a node */
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int RRChan::get_node_segment(size_t track_num) const {
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if ( false == valid_node_id(track_num)) {
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return -1;
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}
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return node_segments_[track_num];
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}
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/* evaluate if two RRChan is mirror to each other */
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bool RRChan::is_mirror(RRChan& cand) const {
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/* If any following element does not match, it is not mirror */
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/* 1. type */
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if (this->get_type() != cand.get_type()) {
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return false;
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}
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/* 2. track_width */
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if (this->get_chan_width() != cand.get_chan_width()) {
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return false;
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}
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/* 3. for each node */
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for (size_t inode = 0; inode < this->get_chan_width(); ++inode) {
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/* 3.1 check node type */
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if (this->get_node(inode)->type != cand.get_node(inode)->type) {
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return false;
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}
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/* 3.2 check node directionality */
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if (this->get_node(inode)->direction != cand.get_node(inode)->direction) {
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return false;
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}
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/* 3.3 check node segment */
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if (this->get_node_segment(inode) != cand.get_node_segment(inode)) {
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return false;
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}
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}
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return true;
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}
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/* Mutators */
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/* modify type */
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void RRChan::set_type(t_rr_type type) {
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assert(valid_type(type));
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type_ = type;
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return;
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}
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/* add a node to the array */
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void RRChan::add_node(t_rr_node* node, size_t node_segment) {
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/* resize the array if needed, node is placed in the sequence of node->ptc_num */
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if (size_t(node->ptc_num) > (nodes_.size() + 1)) {
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nodes_.resize(node->ptc_num + 1); /* resize to the maximum */
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node_segments_.resize(node->ptc_num + 1); /* resize to the maximum */
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}
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/* fill the dedicated element in the vector */
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nodes_[node->ptc_num] = node;
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node_segments_[node->ptc_num] = node_segment;
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return;
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}
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/* Clear content */
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void RRChan::clear() {
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nodes_.clear();
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node_segments_.clear();
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return;
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}
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/* Internal functions */
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/* for type, only valid type is CHANX and CHANY */
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bool RRChan::valid_type(t_rr_type type) const {
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if ((CHANX == type) && (CHANY == type)) {
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return true;
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}
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return false;
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}
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/* check if the node id is valid */
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bool RRChan::valid_node_id(size_t node_id) const {
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if ( (size_t(-1) < node_id) && (node_id < nodes_.size()) ) {
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return true;
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}
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return false;
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}
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/* Member Functions of Class DeviceRRChan */
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/* accessors */
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RRChan DeviceRRChan::get_module(t_rr_type chan_type, size_t module_id) const {
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assert(valid_module_id(chan_type, module_id));
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if (CHANX == chan_type) {
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return chanx_modules_[module_id];
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} else if (CHANY == chan_type) {
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return chany_modules_[module_id];
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}
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}
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void DeviceRRChan::init_module_ids(size_t device_width, size_t device_height) {
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init_chan_module_ids(CHANX, device_width, device_height);
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init_chan_module_ids(CHANY, device_width, device_height);
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return;
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}
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void DeviceRRChan::init_chan_module_ids(t_rr_type chan_type, size_t device_width, size_t device_height) {
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assert(valid_chan_type(chan_type));
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if (CHANX == chan_type) {
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chanx_module_ids_.resize(device_width);
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for (size_t x = 0; x < chanx_module_ids_.size(); ++x) {
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chanx_module_ids_[x].resize(device_height);
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}
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} else if (CHANY == chan_type) {
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chany_module_ids_.resize(device_width);
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for (size_t x = 0; x < chany_module_ids_.size(); ++x) {
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chany_module_ids_[x].resize(device_height);
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}
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}
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return;
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}
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void DeviceRRChan::add_one_chan_module(t_rr_type chan_type, size_t x, size_t y, RRChan rr_chan) {
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assert(valid_coordinator(chan_type, x, y));
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if (CHANX == chan_type) {
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/* Find if the module is unique */
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for (size_t i = 0; i < chanx_modules_.size(); ++i) {
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if ( true == chanx_modules_[i].is_mirror(rr_chan)) {
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/* Find a mirror in the list, assign ids and return */
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chanx_module_ids_[x][y] = i;
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return;
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}
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}
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/* Reach here, it means this is a unique module */
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/* add to the module list */
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chanx_modules_.push_back(rr_chan);
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chanx_module_ids_[x][y] = chanx_modules_.size() - 1;
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} else if (CHANY == chan_type) {
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/* Find if the module is unique */
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for (size_t i = 0; i < chany_modules_.size(); ++i) {
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if ( true == chany_modules_[i].is_mirror(rr_chan)) {
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/* Find a mirror in the list, assign ids and return */
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chany_module_ids_[x][y] = i;
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return;
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}
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}
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/* Reach here, it means this is a unique module */
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/* add to the module list */
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chany_modules_.push_back(rr_chan);
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chany_module_ids_[x][y] = chany_modules_.size() - 1;
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}
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return;
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}
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void DeviceRRChan::clear() {
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clear_chan(CHANX);
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clear_chan(CHANY);
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}
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void DeviceRRChan::clear_chan(t_rr_type chan_type) {
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assert(valid_chan_type(chan_type));
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if (CHANX == chan_type) {
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chanx_modules_.clear();
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} else if (CHANY == chan_type) {
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chany_modules_.clear();
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}
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return;
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}
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/* for type, only valid type is CHANX and CHANY */
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bool DeviceRRChan::valid_chan_type(t_rr_type chan_type) const {
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if ((CHANX == chan_type) && (CHANY == chan_type)) {
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return true;
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}
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return false;
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}
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/* check if the coordinator is in range */
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bool DeviceRRChan::valid_coordinator(t_rr_type chan_type, size_t x, size_t y) const {
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assert(valid_chan_type(chan_type));
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if (CHANX == chan_type) {
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if (!( (size_t(-1) < x) && (x < chanx_module_ids_.size()) )) {
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return false;
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}
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if (!( (size_t(-1) < y) && (y < chanx_module_ids_[x].size()) )) {
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return false;
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}
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} else if (CHANY == chan_type) {
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if (!( (size_t(-1) < x) && (x < chany_module_ids_.size()) )) {
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return false;
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}
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if (!( (size_t(-1) < y) && (y < chany_module_ids_[x].size()) )) {
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return false;
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}
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}
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return true;
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}
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/* check if the node id is valid */
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bool DeviceRRChan::valid_module_id(t_rr_type chan_type, size_t module_id) const {
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assert(valid_chan_type(chan_type));
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if (CHANX == chan_type) {
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if ( (size_t(-1) < module_id) && (module_id < chanx_modules_.size()) ) {
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return true;
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}
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} else if (CHANY == chan_type) {
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if ( (size_t(-1) < module_id) && (module_id < chany_modules_.size()) ) {
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return true;
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}
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}
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return false;
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}
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@ -0,0 +1,74 @@
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/* IMPORTANT:
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* The following preprocessing flags are added to
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* avoid compilation error when this headers are included in more than 1 times
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*/
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#ifndef RR_CHAN_H
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#define RR_CHAN_H
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/*
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* Notes in include header files in a head file
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* Only include the neccessary header files
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* that is required by the data types in the function/class declarations!
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*/
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/* Header files should be included in a sequence */
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/* Standard header files required go first */
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#include <vector>
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#include "vpr_types.h"
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/* RRChan coordinator class */
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/* Object of a channel in a routing resource graph */
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class RRChan {
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public: /* Accessors */
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t_rr_type get_type() const;
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size_t get_chan_width() const; /* get the number of tracks in this channel */
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int get_node_track_id(t_rr_node* node) const; /* get the track_id of a node */
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t_rr_node* get_node(size_t track_num) const; /* get the rr_node with the track_id */
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int get_node_segment(t_rr_node* node) const;
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int get_node_segment(size_t track_num) const;
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bool is_mirror(RRChan& cand) const; /* evaluate if two RR_chan is mirror to each other */
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public: /* Mutators */
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void set_type(t_rr_type type); /* modify type */
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void add_node(t_rr_node* node, size_t node_segment); /* add a node to the array */
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void clear(); /* clear the content */
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private: /* internal functions */
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bool valid_type(t_rr_type type) const;
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bool valid_node_id(size_t node_id) const;
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private: /* Internal Data */
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t_rr_type type_; /* channel type: CHANX or CHANY */
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std::vector<t_rr_node*> nodes_; /* rr nodes of each track in the channel */
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std::vector<size_t> node_segments_; /* segment of each track */
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};
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/* Object including all the RR channels in a device,
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* 1. the RR channels will be in an 2D array
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* 2. Unique Module Name for each channel
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* 3. Instance name for each channel
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* 4. Detailed internal structure of each channel
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* Considering RR channels may share the same structure
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* To be memory efficient, we build a list of unique structures
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* and link each RR channel to
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*/
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class DeviceRRChan {
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public: /* Accessors */
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RRChan get_module(t_rr_type chan_type, size_t module_id) const;
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public: /* Mutators */
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void init_module_ids(size_t device_height, size_t device_width);
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void add_one_chan_module(t_rr_type chan_type, size_t x, size_t y, RRChan rr_chan); /* Add a new unique module of RRChan*/
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void clear();
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private: /* internal functions */
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void clear_chan(t_rr_type chan_type);
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void init_chan_module_ids(t_rr_type chan_type, size_t device_width, size_t device_height);
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bool valid_chan_type(t_rr_type chan_type) const;
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bool valid_coordinator(t_rr_type chan_type, size_t x, size_t y) const;
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bool valid_module_id(t_rr_type chan_type, size_t module_id) const;
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private: /* Internal Data */
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std::vector< std::vector<size_t> > chanx_module_ids_; /* Module id in modules_ for each X-direction rr_channel */
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std::vector< std::vector<size_t> > chany_module_ids_; /* Module id in modules_ for each Y-direction rr_channel */
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std::vector<RRChan> chanx_modules_; /* Detailed internal structure of each unique module */
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std::vector<RRChan> chany_modules_; /* Detailed internal structure of each unique module */
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};
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#endif
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@ -281,7 +281,7 @@ void vpr_fpga_spice(t_vpr_setup vpr_setup,
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spice_print_headers(include_dir_path, vpr_crit_path_delay, num_clocks, *(Arch.spice));
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/* Generate sub circuits: Inverter, Buffer, Transmission Gate, LUT, DFF, SRAM, MUX*/
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generate_spice_subckts(subckt_dir_path, &Arch ,&vpr_setup.RoutingArch);
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generate_spice_subckts(subckt_dir_path, &Arch ,&vpr_setup.RoutingArch, vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
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/* Print MUX testbench if needed */
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if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_pb_mux_testbench) {
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@ -632,7 +632,8 @@ void fprint_switch_box_interc(FILE* fp,
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void fprint_routing_switch_box_subckt(char* subckt_dir,
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t_sb cur_sb_info,
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int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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t_ivec*** LL_rr_node_indices) {
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t_ivec*** LL_rr_node_indices,
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boolean compact_routing_hierarchy) {
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int itrack, inode, side, ix, iy, x, y;
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FILE* fp = NULL;
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char* fname = NULL;
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@ -998,7 +999,9 @@ void fprint_connection_box_interc(FILE* fp,
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void fprint_routing_connection_box_subckt(char* subckt_dir,
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t_cb cur_cb_info,
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int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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t_ivec*** LL_rr_node_indices) {
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t_ivec*** LL_rr_node_indices,
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boolean compact_routing_hierarchy) {
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int itrack, inode, side, x, y;
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int side_cnt = 0;
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FILE* fp = NULL;
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@ -1170,7 +1173,8 @@ void generate_spice_routing_resources(char* subckt_dir,
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t_arch arch,
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t_det_routing_arch* routing_arch,
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int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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t_ivec*** LL_rr_node_indices) {
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t_ivec*** LL_rr_node_indices,
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boolean compact_routing_hierarchy) {
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int ix, iy;
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assert(UNI_DIRECTIONAL == routing_arch->directionality);
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@ -1218,7 +1222,8 @@ void generate_spice_routing_resources(char* subckt_dir,
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for (iy = 0; iy < (ny + 1); iy++) {
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update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models);
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fprint_routing_switch_box_subckt(subckt_dir, sb_info[ix][iy],
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LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices);
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LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices,
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compact_routing_hierarchy);
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update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models);
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}
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}
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@ -1233,7 +1238,8 @@ void generate_spice_routing_resources(char* subckt_dir,
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if ((TRUE == is_cb_exist(CHANX, ix, iy))
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&&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) {
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fprint_routing_connection_box_subckt(subckt_dir, cbx_info[ix][iy],
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LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices);
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LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices,
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compact_routing_hierarchy);
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}
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update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models);
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}
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@ -1246,7 +1252,8 @@ void generate_spice_routing_resources(char* subckt_dir,
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if ((TRUE == is_cb_exist(CHANY, ix, iy))
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&&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) {
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fprint_routing_connection_box_subckt(subckt_dir, cby_info[ix][iy],
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LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices);
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LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices,
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compact_routing_hierarchy);
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}
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||||
update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models);
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||||
}
|
||||
|
|
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|||
|
|
@ -43,7 +43,8 @@ void fprint_switch_box_interc(FILE* fp,
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|||
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||||
void fprint_routing_switch_box_subckt(FILE* fp, t_sb cur_sb_info,
|
||||
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
|
||||
t_ivec*** LL_rr_node_indices);
|
||||
t_ivec*** LL_rr_node_indices,
|
||||
boolean compact_routing_hierarchy);
|
||||
|
||||
void fprint_connection_box_short_interc(FILE* fp,
|
||||
t_cb cur_cb_info,
|
||||
|
|
@ -59,11 +60,13 @@ void fprint_connection_box_interc(FILE* fp,
|
|||
|
||||
void fprint_routing_connection_box_subckt(FILE* fp, t_cb cur_cb_info,
|
||||
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
|
||||
t_ivec*** LL_rr_node_indices);
|
||||
t_ivec*** LL_rr_node_indices,
|
||||
boolean compact_routing_hierarchy);
|
||||
|
||||
void generate_spice_routing_resources(char* subckt_dir,
|
||||
t_arch arch,
|
||||
t_det_routing_arch* routing_arch,
|
||||
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
|
||||
t_ivec*** LL_rr_node_indices);
|
||||
t_ivec*** LL_rr_node_indices,
|
||||
boolean compact_routing_hierarchy);
|
||||
|
||||
|
|
|
|||
|
|
@ -706,7 +706,8 @@ void generate_spice_wires(char* subckt_dir,
|
|||
*/
|
||||
void generate_spice_subckts(char* subckt_dir,
|
||||
t_arch* arch,
|
||||
t_det_routing_arch* routing_arch) {
|
||||
t_det_routing_arch* routing_arch,
|
||||
boolean compact_routing_hierarchy) {
|
||||
/* 1.Generate NMOS, PMOS and transmission gate */
|
||||
vpr_printf(TIO_MESSAGE_INFO,"Writing SPICE NMOS and PMOS...\n");
|
||||
generate_spice_nmos_pmos(subckt_dir, arch->spice->tech_lib);
|
||||
|
|
@ -736,7 +737,8 @@ void generate_spice_subckts(char* subckt_dir,
|
|||
/* 6. Generate Routing architecture*/
|
||||
vpr_printf(TIO_MESSAGE_INFO, "Writing Routing Resources....\n");
|
||||
generate_spice_routing_resources(subckt_dir, (*arch), routing_arch,
|
||||
num_rr_nodes, rr_node, rr_node_indices);
|
||||
num_rr_nodes, rr_node, rr_node_indices,
|
||||
compact_routing_hierarchy);
|
||||
|
||||
/* 7. Generate Logic Blocks */
|
||||
vpr_printf(TIO_MESSAGE_INFO,"Writing Logic Blocks...\n");
|
||||
|
|
|
|||
|
|
@ -10,4 +10,5 @@ void generate_spice_subckt_tapbuf(FILE* fp,
|
|||
|
||||
void generate_spice_subckts(char* subckt_dir,
|
||||
t_arch* arch,
|
||||
t_det_routing_arch* routing_arch);
|
||||
t_det_routing_arch* routing_arch,
|
||||
boolean compact_routing_hierarchy);
|
||||
|
|
|
|||
Loading…
Reference in New Issue