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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb

This commit is contained in:
AurelienUoU 2019-05-10 14:09:23 -06:00
parent ff9b84d800 be4643b8a6
commit 9c05a4fb0a
21 changed files with 1224 additions and 1765 deletions
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1
vpr7_x2p/vpr/SRC/base/OptionTokens.c
View File

@ -61,6 +61,7 @@ struct s_TokenPair OptionBaseTokenList[] = {
{ "fpga_x2p_rename_illegal_port", OT_FPGA_X2P_RENAME_ILLEGAL_PORT }, /* Xifan TANG: rename illegal port names */
{ "fpga_x2p_signal_density_weight", OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT }, /* The weight of signal density */
{ "fpga_x2p_sim_window_size", OT_FPGA_X2P_SIM_WINDOW_SIZE }, /* Window size in determining number of clock cycles in simulation */
{ "fpga_x2p_compact_routing_hierarchy", OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY }, /* use a compact routing hierarchy in SPICE/Verilog generation */
/* Xifan TANG: FPGA SPICE Support */
{ "fpga_spice", OT_FPGA_SPICE },/* Xifan TANG: SPICE Model Support, turn on the functionality*/
{ "fpga_spice_dir", OT_FPGA_SPICE_DIR },/* Xifan TANG: SPICE Model Support, directory of spice netlists*/

1
vpr7_x2p/vpr/SRC/base/OptionTokens.h
View File

@ -78,6 +78,7 @@ enum e_OptionBaseToken {
OT_FPGA_X2P_RENAME_ILLEGAL_PORT,
OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT, /* The weight of signal density in determining number of clock cycles in simulation */
OT_FPGA_X2P_SIM_WINDOW_SIZE, /* Window size in determining number of clock cycles in simulation */
OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY, /* use a compact routing hierarchy in SPICE/Verilog generation */
/* Xifan TANG: FPGA SPICE Support */
OT_FPGA_SPICE, /* Xifan TANG: FPGA SPICE Model Support */
OT_FPGA_SPICE_DIR, /* Xifan TANG: FPGA SPICE Model Support */

3
vpr7_x2p/vpr/SRC/base/ReadOptions.c
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@ -481,6 +481,9 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
return ReadFloat(Args, &Options->fpga_spice_signal_density_weight);
case OT_FPGA_X2P_SIM_WINDOW_SIZE:
return ReadFloat(Args, &Options->fpga_spice_sim_window_size);
case OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY:
/* use a compact routing hierarchy in SPICE/Verilog generation */
return Args;
/* Xifan TANG: FPGA SPICE Model Options*/
case OT_FPGA_SPICE:
return Args;

6
vpr7_x2p/vpr/SRC/base/SetupVPR.c
View File

@ -1235,6 +1235,12 @@ static void SetupFpgaSpiceOpts(t_options Options,
fpga_spice_opts->sim_window_size = Options.fpga_spice_sim_window_size;
}
/* Check if user wants to use a compact routing hierarchy */
fpga_spice_opts->compact_routing_hierarchy = FALSE;
if (Options.Count[OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY]) {
fpga_spice_opts->compact_routing_hierarchy = TRUE;
}
/* Decide if we need to do FPGA-SPICE */
fpga_spice_opts->do_fpga_spice = FALSE;
if (( TRUE == fpga_spice_opts->SpiceOpts.do_spice)

1
vpr7_x2p/vpr/SRC/base/vpr_api.c
View File

@ -170,6 +170,7 @@ void vpr_print_usage(void) {
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_rename_illegal_port\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_signal_density_weight <float>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_sim_window_size <float>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_compact_routing_hierarchy\n");
vpr_printf(TIO_MESSAGE_INFO, "SPICE Support Options:\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_dir <directory_path_output_spice_netlists>\n");

26
vpr7_x2p/vpr/SRC/base/vpr_types.h
View File

@ -1153,6 +1153,18 @@ struct s_sb {
int num_reserved_conf_bits; /* number of reserved configuration bits */
int conf_bits_lsb; /* LSB of configuration bits */
int conf_bits_msb; /* MSB of configuration bits */
/* For identical SBs */
t_sb* mirror; /* an exact mirror of this switch block, with same connection & switches */
/* an rotatable mirror of this switch block,
* the two switch blocks will be same in terms of connection & switches
* by applying an offset to the connection & switches
*/
t_sb* rotatable;
/* Offset to be applied for each side of nodes */
int* offset_ipin; /* [0, ..., num_sides-1]*/
int* offset_opin; /* [0, ..., num_sides-1]*/
int* offset_chan; /* [0, ..., num_sides-1]*/
};
/* Information for each conneciton block */
@ -1188,6 +1200,18 @@ struct s_cb {
int num_reserved_conf_bits; /* number of reserved configuration bits */
int conf_bits_lsb; /* LSB of configuration bits */
int conf_bits_msb; /* MSB of configuration bits */
/* For identical SBs */
t_cb* mirror; /* an exact mirror of this connection block, with same connection & switches */
/* an rotatable mirror of this connection block,
* the two connection blocks will be same in terms of connection & switches
* by applying an offset to the connection & switches
*/
t_cb* rotatable;
/* Offset to be applied for each side of nodes */
int* offset_ipin; /* [0, ..., num_sides-1]*/
int* offset_opin; /* [0, ..., num_sides-1]*/
int* offset_chan; /* [0, ..., num_sides-1]*/
};
/* Xifan TANG: SPICE Support*/
@ -1255,6 +1279,8 @@ struct s_fpga_spice_opts {
t_syn_verilog_opts SynVerilogOpts; /* Xifan TANG: Synthesizable verilog dumping*/
t_bitstream_gen_opts BitstreamGenOpts; /* Xifan Bitsteam Generator */
boolean compact_routing_hierarchy; /* use compact routing hierarchy */
/* Signal Density */
float signal_density_weight;
float sim_window_size;

20
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c
View File

@ -206,6 +206,12 @@ void init_one_sb_info(t_sb* cur_sb) {
cur_sb->conf_bits_lsb = 0;
cur_sb->conf_bits_msb = 0;
cur_sb->mirror = NULL;
cur_sb->rotatable = NULL;
cur_sb->offset_ipin = NULL;
cur_sb->offset_opin = NULL;
cur_sb->offset_chan = NULL;
return;
}
@ -237,6 +243,10 @@ void free_one_sb_info(t_sb* cur_sb) {
my_free(cur_sb->opin_rr_node);
my_free(cur_sb->opin_rr_node_grid_side);
my_free(cur_sb->offset_ipin);
my_free(cur_sb->offset_opin);
my_free(cur_sb->offset_chan);
return;
}
@ -299,6 +309,12 @@ void init_one_cb_info(t_cb* cur_cb) {
cur_cb->conf_bits_lsb = 0;
cur_cb->conf_bits_msb = 0;
cur_cb->mirror = NULL;
cur_cb->rotatable = NULL;
cur_cb->offset_ipin = NULL;
cur_cb->offset_opin = NULL;
cur_cb->offset_chan = NULL;
return;
}
@ -330,6 +346,10 @@ void free_one_cb_info(t_cb* cur_cb) {
my_free(cur_cb->opin_rr_node);
my_free(cur_cb->opin_rr_node_grid_side);
my_free(cur_cb->offset_ipin);
my_free(cur_cb->offset_opin);
my_free(cur_cb->offset_chan);
return;
}

709
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c Normal file
View File

@ -0,0 +1,709 @@
/***********************************/
/* SPICE Modeling for VPR */
/* Xifan TANG, EPFL/LSI */
/***********************************/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#include <assert.h>
#include <sys/stat.h>
#include <unistd.h>
/* Include vpr structs*/
#include "util.h"
#include "physical_types.h"
#include "vpr_types.h"
#include "globals.h"
#include "rr_graph_util.h"
#include "rr_graph.h"
#include "rr_graph2.h"
#include "vpr_utils.h"
#include "path_delay.h"
#include "stats.h"
#include "route_common.h"
/* Include spice support headers*/
#include "read_xml_spice_util.h"
#include "linkedlist.h"
#include "fpga_x2p_types.h"
#include "fpga_x2p_globals.h"
#include "fpga_x2p_utils.h"
#include "fpga_x2p_backannotate_utils.h"
#include "fpga_x2p_identify_routing.h"
/***** subroutines declaration *****/
void assign_switch_block_mirror(t_sb* src, t_sb* des);
void assign_connection_block_mirror(t_cb* src, t_cb* des);
boolean is_two_sb_rr_nodes_mirror(t_sb* src_sb, t_sb* des_sb, int side,
t_rr_node* src_rr_node, t_rr_node* des_rr_node);
boolean is_two_cb_rr_nodes_mirror(t_cb* src_cb, t_cb* des_cb,
t_rr_node* src_rr_node, t_rr_node* des_rr_node);
boolean is_two_switch_blocks_mirror(t_sb* src, t_sb* des);
boolean is_two_connection_blocks_mirror(t_cb* src, t_cb* des);
void assign_mirror_switch_blocks();
void assign_mirror_connection_blocks();
boolean validate_one_switch_block_mirror(t_sb* cur_sb);
boolean validate_one_connection_block_mirror(t_cb* cur_cb);
void update_one_switch_block_mirror(t_sb* cur_sb);
void update_one_connection_block_mirror(t_cb* cur_cb);
boolean validate_mirror_switch_blocks();
boolean validate_mirror_connection_blocks();
void update_mirror_switch_blocks();
void update_mirror_connection_blocks();
void print_mirror_switch_block_stats();
void print_mirror_connection_block_stats();
/***** subroutines *****/
void assign_switch_block_mirror(t_sb* src, t_sb* des) {
assert ( (NULL != src) && (NULL != des) );
/* check if the mirror of the first SB is assigned */
if (NULL != src->mirror) {
/* Assign mirror of the first SB to the second SB */
/* traceback to the upstream */
t_sb* temp = src->mirror;
while (NULL != temp->mirror) {
/* go to the next */
temp = temp->mirror;
}
/* We reach the upstream, ensure its mirror is empty */
assert(NULL == temp->mirror);
des->mirror = temp;
} else {
/* Assign the first SB as the mirror to the second SB */
des->mirror = src;
}
return;
}
void assign_connection_block_mirror(t_cb* src, t_cb* des) {
assert ( (NULL != src) && (NULL != des) );
/* check if the mirror of the first SB is assigned */
if (NULL != src->mirror) {
/* Assign mirror of the first SB to the second SB */
/* traceback to the upstream */
t_cb* temp = src->mirror;
while (NULL != temp->mirror) {
/* go to the next */
temp = temp->mirror;
}
/* We reach the upstream, ensure its mirror is empty */
assert(NULL == temp->mirror);
des->mirror = temp;
} else {
/* Assign the first SB as the mirror to the second SB */
des->mirror = src;
}
return;
}
/* check if two rr_nodes have a similar set of drive_rr_nodes
* for each drive_rr_node:
* 1. CHANX or CHANY: should have the same side and index
* 2. OPIN or IPIN: should have the same side and index
* 3. each drive_rr_switch should be the same
*/
boolean is_two_sb_rr_nodes_mirror(t_sb* src_sb, t_sb* des_sb, int side,
t_rr_node* src_rr_node, t_rr_node* des_rr_node) {
/* Ensure rr_nodes are either the output of short-connection or multiplexer */
if ( check_drive_rr_node_imply_short(*src_sb, src_rr_node, side)
!= check_drive_rr_node_imply_short(*des_sb, des_rr_node, side)) {
return FALSE;
}
/* Find the driving rr_node in this sb */
if (TRUE == check_drive_rr_node_imply_short(*src_sb, src_rr_node, side)) {
/* Ensure we have the same track id for the driving nodes */
if ( is_rr_node_exist_opposite_side_in_sb_info(*src_sb, src_rr_node, side)
!= is_rr_node_exist_opposite_side_in_sb_info(*des_sb, des_rr_node, side)) {
return FALSE;
}
} else { /* check driving rr_nodes */
if ( src_rr_node->num_drive_rr_nodes != des_rr_node->num_drive_rr_nodes ) {
return FALSE;
}
for (int inode = 0; inode < src_rr_node->num_drive_rr_nodes; ++inode) {
/* node type should be the same */
if ( src_rr_node->drive_rr_nodes[inode]->type
!= des_rr_node->drive_rr_nodes[inode]->type) {
return FALSE;
}
/* switch type should be the same */
if ( src_rr_node->drive_switches[inode]
!= des_rr_node->drive_switches[inode]) {
return FALSE;
}
int src_node_id, des_node_id;
int src_node_side, des_node_side;
get_rr_node_side_and_index_in_sb_info(src_rr_node->drive_rr_nodes[inode], *src_sb, OUT_PORT, &src_node_side, &src_node_id);
get_rr_node_side_and_index_in_sb_info(des_rr_node->drive_rr_nodes[inode], *des_sb, OUT_PORT, &des_node_side, &des_node_id);
if (src_node_id != des_node_id) {
return FALSE;
}
if (src_node_side != des_node_side) {
return FALSE;
}
}
}
return TRUE;
}
/* check if two rr_nodes have a similar set of drive_rr_nodes
* for each drive_rr_node:
* 1. CHANX or CHANY: should have the same side and index
* 2. OPIN or IPIN: should have the same side and index
* 3. each drive_rr_switch should be the same
*/
boolean is_two_cb_rr_nodes_mirror(t_cb* src_cb, t_cb* des_cb,
t_rr_node* src_rr_node, t_rr_node* des_rr_node) {
/* check driving rr_nodes */
if ( src_rr_node->num_drive_rr_nodes != des_rr_node->num_drive_rr_nodes ) {
return FALSE;
}
for (int inode = 0; inode < src_rr_node->num_drive_rr_nodes; ++inode) {
/* node type should be the same */
if ( src_rr_node->drive_rr_nodes[inode]->type
!= des_rr_node->drive_rr_nodes[inode]->type) {
return FALSE;
}
/* switch type should be the same */
if ( src_rr_node->drive_switches[inode]
!= des_rr_node->drive_switches[inode]) {
return FALSE;
}
int src_node_id, des_node_id;
int src_node_side, des_node_side;
get_rr_node_side_and_index_in_cb_info(src_rr_node->drive_rr_nodes[inode], *src_cb, OUT_PORT, &src_node_side, &src_node_id);
get_rr_node_side_and_index_in_cb_info(des_rr_node->drive_rr_nodes[inode], *des_cb, OUT_PORT, &des_node_side, &des_node_id);
if (src_node_id != des_node_id) {
return FALSE;
}
if (src_node_side != des_node_side) {
return FALSE;
}
}
return TRUE;
}
/* Idenify mirror Switch blocks
* Check each two switch blocks:
* 1. Number of channel/opin/ipin rr_nodes are same
* For channel rr_nodes
* 2. check if their track_ids (ptc_num) are same
* 3. Check if the switches (ids) are same
* For opin/ipin rr_nodes,
* 4. check if their parent type_descriptors same,
* 5. check if pin class id and pin id are same
* If all above are satisfied, the two switch blocks are mirrors!
*/
boolean is_two_switch_blocks_mirror(t_sb* src, t_sb* des) {
/* check the numbers of sides */
if (src->num_sides != des->num_sides) {
return FALSE;
}
/* check the numbers/directionality of channel rr_nodes */
for (int side = 0; side < src->num_sides; ++side) {
/* Ensure we have the same channel width on this side */
if (src->chan_width[side] != des->chan_width[side]) {
return FALSE;
}
for (int itrack = 0; itrack < src->chan_width[side]; ++itrack) {
/* Check the directionality of each node */
if (src->chan_rr_node_direction[side][itrack] != des->chan_rr_node_direction[side][itrack]) {
return FALSE;
}
/* Check the track_id of each node */
if (src->chan_rr_node[side][itrack]->ptc_num != des->chan_rr_node[side][itrack]->ptc_num) {
return FALSE;
}
/* For OUT_PORT rr_node, we need to check fan-in */
if (OUT_PORT != src->chan_rr_node_direction[side][itrack]) {
continue; /* skip IN_PORT */
}
if (FALSE == is_two_sb_rr_nodes_mirror(src, des, side,
src->chan_rr_node[side][itrack],
des->chan_rr_node[side][itrack])) {
return FALSE;
}
}
}
/* check the numbers of opin_rr_nodes */
for (int side = 0; side < src->num_sides; ++side) {
if (src->num_ipin_rr_nodes[side] != des->num_ipin_rr_nodes[side]) {
return FALSE;
}
}
/* Make sure the number of conf bits are the same */
if ( (src->conf_bits_msb - src->conf_bits_lsb)
!= (des->conf_bits_msb - des->conf_bits_lsb)) {
return FALSE;
}
return TRUE;
}
/* Walk through all the switch blocks,
* Make one-to-one comparison,
* If we have a pair, update the 1st SB to be the base and label the 2nd as a mirror
* If the 1st SB is already a mirror to another, we will trace back to the upstream base and update the 2nd SB
*/
void assign_mirror_switch_blocks() {
/* Walkthrough each column, and find mirrors */
for (int ix = 0; ix < (nx + 1); ++ix) {
for (int iy = 0; iy < (ny + 1); ++iy) {
for (int jy = iy; jy < (ny + 1); ++jy) {
/* bypass the same one */
if (iy == jy) {
continue;
}
/* Do one-to-one comparison */
if (FALSE == is_two_switch_blocks_mirror(&(sb_info[ix][iy]), &(sb_info[ix][jy]))) {
/* Nothing to do if the two switch blocks are not equivalent */
continue;
}
/* configure the mirror of the second switch block */
assign_switch_block_mirror(&(sb_info[ix][iy]), &(sb_info[ix][jy]));
}
}
}
/* Now mirror switch blocks in each column has been annotated */
/* Walkthrough each row, and find mirrors */
for (int iy = 0; iy < (ny + 1); ++iy) {
for (int ix = 0; ix < (nx + 1); ++ix) {
for (int jx = ix; jx < (nx + 1); ++jx) {
/* bypass the same one */
if (ix == jx) {
continue;
}
/* Do one-to-one comparison */
if (FALSE == is_two_switch_blocks_mirror(&(sb_info[ix][iy]), &(sb_info[jx][iy]))) {
/* Nothing to do if the two switch blocks are not equivalent */
continue;
}
/* configure the mirror of the second switch block */
assign_switch_block_mirror(&(sb_info[ix][iy]), &(sb_info[jx][iy]));
}
}
}
return;
}
/* Validate the mirror of a switch block is the upstream
* with NULL mirror
*/
boolean validate_one_switch_block_mirror(t_sb* cur_sb) {
if (NULL == cur_sb->mirror) {
/* This is the upstream */
return TRUE;
}
/* If the upstream has a mirror, there is a bug */
if (NULL != cur_sb->mirror->mirror) {
return FALSE;
}
return TRUE;
}
/* Validate the mirror of a switch block is the upstream
* with NULL mirror
*/
boolean validate_one_connection_block_mirror(t_cb* cur_cb) {
if (NULL == cur_cb->mirror) {
/* This is the upstream */
return TRUE;
}
/* If the upstream has a mirror, there is a bug */
if (NULL != cur_cb->mirror->mirror) {
return FALSE;
}
return TRUE;
}
/* update the mirror of each switch block */
void update_one_switch_block_mirror(t_sb* cur_sb) {
if (NULL == cur_sb->mirror) {
/* This is the upstream */
return;
}
/* Assign mirror of the first SB to the second SB */
/* traceback to the upstream */
t_sb* temp = cur_sb->mirror;
while (NULL != temp->mirror) {
/* go to the next */
temp = temp->mirror;
}
/* We reach the upstream, ensure its mirror is empty */
assert(NULL == temp->mirror);
cur_sb->mirror = temp;
return;
}
/* update the mirror of each switch block */
void update_one_connection_block_mirror(t_cb* cur_cb) {
if (NULL == cur_cb->mirror) {
/* This is the upstream */
return;
}
/* Assign mirror of the first SB to the second SB */
/* traceback to the upstream */
t_cb* temp = cur_cb->mirror;
while (NULL != temp->mirror) {
/* go to the next */
temp = temp->mirror;
}
/* We reach the upstream, ensure its mirror is empty */
assert(NULL == temp->mirror);
cur_cb->mirror = temp;
return;
}
/* Validate the mirror of each switch block is the upstream */
boolean validate_mirror_switch_blocks() {
boolean ret = TRUE;
/* Walkthrough each column, and find mirrors */
for (int ix = 0; ix < (nx + 1); ++ix) {
for (int iy = 0; iy < (ny + 1); ++iy) {
if (FALSE == validate_one_switch_block_mirror(&(sb_info[ix][iy]))) {
ret = FALSE;
}
}
}
return ret;
}
/* Validate the mirror of each connection block is the upstream */
boolean validate_mirror_connection_blocks() {
boolean ret = TRUE;
/* X - channels [1...nx][0..ny]*/
for (int iy = 0; iy < (ny + 1); iy++) {
for (int ix = 1; ix < (nx + 1); ix++) {
if (FALSE == validate_one_connection_block_mirror(&(cbx_info[ix][iy]))) {
ret = FALSE;
}
}
}
/* Y - channels [1...ny][0..nx]*/
for (int ix = 0; ix < (nx + 1); ix++) {
for (int iy = 1; iy < (ny + 1); iy++) {
if (FALSE == validate_one_connection_block_mirror(&(cby_info[ix][iy]))) {
ret = FALSE;
}
}
}
return ret;
}
/* Validate the mirror of each switch block is the upstream */
void update_mirror_switch_blocks() {
/* Walkthrough each column, and find mirrors */
for (int ix = 0; ix < (nx + 1); ++ix) {
for (int iy = 0; iy < (ny + 1); ++iy) {
update_one_switch_block_mirror(&(sb_info[ix][iy]));
}
}
return;
}
/* Validate the mirror of each connection block is the upstream */
void update_mirror_connection_blocks() {
/* X - channels [1...nx][0..ny]*/
for (int iy = 0; iy < (ny + 1); iy++) {
for (int ix = 1; ix < (nx + 1); ix++) {
update_one_connection_block_mirror(&(cbx_info[ix][iy]));
}
}
/* Y - channels [1...ny][0..nx]*/
for (int ix = 0; ix < (nx + 1); ix++) {
for (int iy = 1; iy < (ny + 1); iy++) {
update_one_connection_block_mirror(&(cby_info[ix][iy]));
}
}
return;
}
void print_mirror_switch_block_stats() {
int num_mirror_sb = 0;
/* Walkthrough each column, and find mirrors */
for (int ix = 0; ix < (nx + 1); ++ix) {
for (int iy = 0; iy < (ny + 1); ++iy) {
if (NULL == sb_info[ix][iy].mirror) {
num_mirror_sb++;
}
}
}
/* Print stats */
vpr_printf(TIO_MESSAGE_INFO,
"Detect %d independent switch blocks from %d switch blocks.\n",
num_mirror_sb, (nx + 1) * (ny + 1) );
return;
}
void print_mirror_connection_block_stats() {
int num_mirror_cbx = 0;
int num_mirror_cby = 0;
/* X - channels [1...nx][0..ny]*/
for (int iy = 0; iy < (ny + 1); iy++) {
for (int ix = 1; ix < (nx + 1); ix++) {
if (NULL == cbx_info[ix][iy].mirror) {
num_mirror_cbx++;
}
}
}
/* Y - channels [1...ny][0..nx]*/
for (int ix = 0; ix < (nx + 1); ix++) {
for (int iy = 1; iy < (ny + 1); iy++) {
if (NULL == cby_info[ix][iy].mirror) {
num_mirror_cby++;
}
}
}
/* Print stats */
vpr_printf(TIO_MESSAGE_INFO,
"Detect %d independent connection blocks from %d X-channel connection blocks.\n",
num_mirror_cbx, (nx + 0) * (ny + 1) );
vpr_printf(TIO_MESSAGE_INFO,
"Detect %d independent connection blocks from %d Y-channel connection blocks.\n",
num_mirror_cby, (nx + 1) * (ny + 0) );
return;
}
void identify_mirror_switch_blocks() {
/* Assign the mirror of each switch block */
assign_mirror_switch_blocks();
/* Ensure all the mirror are the upstream */
update_mirror_switch_blocks();
/* Validate the mirror of switch blocks, everyone should be the upstream */
assert(TRUE == validate_mirror_switch_blocks());
/* print the stats */
print_mirror_switch_block_stats();
return;
}
/* Idenify mirror connection blocks
* Check each two connection blocks:
* 1. Number of channel/opin/ipin rr_nodes are same
* For channel rr_nodes
* 2. check if their track_ids (ptc_num) are same
* 3. Check if the switches (ids) are same
* For opin/ipin rr_nodes,
* 4. check if their parent type_descriptors same,
* 5. check if pin class id and pin id are same
* If all above are satisfied, the two switch blocks are mirrors!
*/
boolean is_two_connection_blocks_mirror(t_cb* src, t_cb* des) {
/* check the numbers of sides */
if (src->num_sides != des->num_sides) {
return FALSE;
}
/* check the numbers/directionality of channel rr_nodes */
for (int side = 0; side < src->num_sides; ++side) {
/* Ensure we have the same channel width on this side */
if (src->chan_width[side] != des->chan_width[side]) {
return FALSE;
}
for (int itrack = 0; itrack < src->chan_width[side]; ++itrack) {
/* Check the directionality of each node */
if (src->chan_rr_node_direction[side][itrack] != des->chan_rr_node_direction[side][itrack]) {
return FALSE;
}
/* Check the track_id of each node */
if (src->chan_rr_node[side][itrack]->ptc_num != des->chan_rr_node[side][itrack]->ptc_num) {
return FALSE;
}
}
}
/* check the equivalence of ipins */
for (int side = 0; side < src->num_sides; ++side) {
/* Ensure we have the same number of IPINs on this side */
if (src->num_ipin_rr_nodes[side] != des->num_ipin_rr_nodes[side]) {
return FALSE;
}
for (int inode = 0; inode < src->num_ipin_rr_nodes[side]; ++inode) {
if (FALSE == is_two_cb_rr_nodes_mirror(src, des,
src->ipin_rr_node[side][inode],
des->ipin_rr_node[side][inode])) {
return FALSE;
}
}
}
/* Make sure the number of conf bits are the same */
if ( (src->conf_bits_msb - src->conf_bits_lsb)
!= (des->conf_bits_msb - des->conf_bits_lsb)) {
return FALSE;
}
return TRUE;
}
void assign_mirror_connection_blocks() {
/* X - channels [1...nx][0..ny]*/
for (int iy = 0; iy < (ny + 1); iy++) {
for (int ix = 1; ix < (nx + 1); ix++) {
for (int jx = ix; jx < (nx + 1); jx++) {
/* bypass the same one */
if (ix == jx) {
continue;
}
/* Do one-to-one comparison */
if (FALSE == is_two_connection_blocks_mirror(&(cbx_info[ix][iy]), &(cbx_info[jx][iy]))) {
/* Nothing to do if the two switch blocks are not equivalent */
continue;
}
/* configure the mirror of the second switch block */
assign_connection_block_mirror(&(cbx_info[ix][iy]), &(cbx_info[jx][iy]));
}
}
}
for (int ix = 1; ix < (nx + 1); ix++) {
for (int iy = 0; iy < (ny + 1); iy++) {
for (int jy = iy; jy < (ny + 1); jy++) {
/* bypass the same one */
if (iy == jy) {
continue;
}
/* Do one-to-one comparison */
if (FALSE == is_two_connection_blocks_mirror(&(cbx_info[ix][iy]), &(cbx_info[ix][jy]))) {
/* Nothing to do if the two switch blocks are not equivalent */
continue;
}
/* configure the mirror of the second switch block */
assign_connection_block_mirror(&(cbx_info[ix][iy]), &(cbx_info[ix][jy]));
}
}
}
/* Y - channels [1...ny][0..nx]*/
for (int ix = 0; ix < (nx + 1); ix++) {
for (int iy = 1; iy < (ny + 1); iy++) {
for (int jy = iy; jy < (ny + 1); jy++) {
/* bypass the same one */
if (iy == jy) {
continue;
}
/* Do one-to-one comparison */
if (FALSE == is_two_connection_blocks_mirror(&(cby_info[ix][iy]), &(cby_info[ix][jy]))) {
/* Nothing to do if the two switch blocks are not equivalent */
continue;
}
/* configure the mirror of the second switch block */
assign_connection_block_mirror(&(cby_info[ix][iy]), &(cby_info[ix][jy]));
}
}
}
for (int iy = 1; iy < (ny + 1); iy++) {
for (int ix = 0; ix < (nx + 1); ix++) {
for (int jx = ix; jx < (nx + 1); jx++) {
/* bypass the same one */
if (ix == jx) {
continue;
}
/* Do one-to-one comparison */
if (FALSE == is_two_connection_blocks_mirror(&(cby_info[ix][iy]), &(cby_info[jx][iy]))) {
/* Nothing to do if the two switch blocks are not equivalent */
continue;
}
/* configure the mirror of the second switch block */
assign_connection_block_mirror(&(cby_info[ix][iy]), &(cby_info[jx][iy]));
}
}
}
return;
}
/* Idenify mirror Connection blocks */
void identify_mirror_connection_blocks() {
/* Assign the mirror of each switch block */
assign_mirror_connection_blocks();
/* Ensure all the mirror are the upstream */
update_mirror_connection_blocks();
/* Validate the mirror of switch blocks, everyone should be the upstream */
assert(TRUE == validate_mirror_connection_blocks());
/* print the stats */
print_mirror_connection_block_stats();
return;
}
/* Rotatable will be done in the next step
void identify_rotatable_switch_blocks();
void identify_rotatable_connection_blocks();
*/

13
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.h Normal file
View File

@ -0,0 +1,13 @@
/* Avoid repeated header inclusion */
#ifndef FPGA_X2P_IDENTIFY_ROUTING
#define FPGA_X2P_IDENTIFY_ROUTING
void identify_mirror_switch_blocks();
void identify_mirror_connection_blocks();
/* Rotatable will be done in the next step
identify_rotatable_switch_blocks();
identify_rotatable_connection_blocks();
*/
#endif

4
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h
View File

@ -113,8 +113,6 @@ t_pb* get_child_pb_for_phy_pb_graph_node(t_pb* cur_pb, int ipb, int jpb);
t_phy_pb* get_phy_child_pb_for_phy_pb_graph_node(t_phy_pb* cur_phy_pb, int ipb, int jpb);
enum e_interconnect find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin) ;
t_spice_model* find_pb_graph_pin_in_edges_interc_model(t_pb_graph_pin pb_graph_pin) ;
void find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin,
@ -210,8 +208,6 @@ t_phy_pb* rec_get_phy_pb_by_name(t_phy_pb* cur_phy_pb,
int get_pb_graph_node_wired_lut_logical_block_index(t_pb_graph_node* cur_pb_graph_node,
t_rr_node* op_pb_rr_graph);
void rec_reset_pb_graph_node_rr_node_index_physical_pb(t_pb_graph_node* cur_pb_graph_node);
void sync_wired_lut_to_one_phy_pb(t_pb_graph_node* cur_pb_graph_node,
t_phy_pb* cur_phy_pb,
t_rr_node* op_pb_rr_graph);

14
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c
View File

@ -31,6 +31,7 @@
#include "fpga_x2p_backannotate_utils.h"
#include "fpga_x2p_pbtypes_utils.h"
#include "verilog_api.h"
#include "fpga_x2p_identify_routing.h"
#include "fpga_x2p_setup.h"
/***** Subroutines Declarations *****/
@ -1302,7 +1303,7 @@ void fpga_x2p_free(t_arch* Arch) {
/* Top-level function of FPGA-SPICE setup */
void fpga_x2p_setup(t_vpr_setup vpr_setup,
t_arch* Arch) {
t_arch* Arch) {
int num_rename_violation = 0;
int num_clocks = 0;
float vpr_crit_path_delay = 0.;
@ -1386,6 +1387,17 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup,
vpr_setup.FPGA_SPICE_Opts.read_act_file,
vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_parasitic_net_estimation);
/* Try to use mirror SBs/CBs if enabled by user */
if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) {
/* Idenify mirror and rotatable Switch blocks and Connection blocks */
identify_mirror_switch_blocks();
identify_mirror_connection_blocks();
/* Rotatable will be done in the next step
identify_rotatable_switch_blocks();
identify_rotatable_connection_blocks();
*/
}
/* Not should be done when read_act_file is disabled */
if (FALSE == vpr_setup.FPGA_SPICE_Opts.read_act_file) {
return;

12
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h
View File

@ -1,3 +1,6 @@
#ifndef FPGA_X2P_UTILS_H
#define FPGA_X2P_UTILS_H
void my_free(void* ptr);
char* my_gettime();
@ -66,15 +69,8 @@ char* chomp_spice_node_prefix(char* spice_node_prefix);
char* format_spice_node_prefix(char* spice_node_prefix);
char* format_spice_node_prefix(char* spice_node_prefix);
t_block* search_mapped_block(int x, int y, int z);
char** fpga_spice_strtok(char* str,
char* delims,
int* len);
@ -409,3 +405,5 @@ void get_fpga_x2p_global_op_clock_ports(t_llist* head,
void get_fpga_x2p_global_all_clock_ports(t_llist* head,
int* num_clock_ports,
t_spice_model_port*** clock_port);
#endif

1
vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.c
View File

@ -31,6 +31,7 @@ boolean shell_setup_fpga_x2p_setup(t_shell_env* env, t_opt_info* opts) {
env->vpr_setup.FPGA_SPICE_Opts.rename_illegal_port = is_opt_set(opts, "rename_illegal_port", FALSE);
env->vpr_setup.FPGA_SPICE_Opts.signal_density_weight = get_opt_float_val(opts, "signal_density_weight", 1.);
env->vpr_setup.FPGA_SPICE_Opts.sim_window_size = get_opt_float_val(opts, "sim_window_size", 0.5);
env->vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy = is_opt_set(opts, "compact_routing_hierarchy", FALSE);
return TRUE;
}

1
vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.h
View File

@ -6,6 +6,7 @@ t_opt_info fpga_x2p_setup_opts[] = {
{"rename_illegal_port", "-rip,--rename_illegal_port", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Rename illegal ports that violates Verilog syntax"},
{"signal_density_weight", "-sdw,--signal_density_weight", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, "Specify the signal density weight when doing the average number"},
{"sim_window_size", "-sws,--sim_window_size", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, "Specify the size of window when doing simulation"},
{"compact_routing_hierarchy", "-crh,--compact_routing_hierarchy", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify if use a compact routing hierarchy in SPIC/Verilog generation"},
{HELP_OPT_TAG, HELP_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"},
{LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"}
};

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
View File

@ -253,7 +253,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
/* Dump routing resources: switch blocks, connection blocks and channel tracks */
dump_verilog_routing_resources(sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, &vpr_setup.RoutingArch,
num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
/* Dump logic blocks
* Branches to go:
@ -274,6 +274,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
num_rr_nodes, rr_node, rr_node_indices,
num_clocks,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts,
vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy,
*(Arch.spice));
/* Dump SDC constraints */

319
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -35,6 +35,7 @@
#include "verilog_utils.h"
#include "verilog_primitives.h"
#include "verilog_pbtypes.h"
#include "verilog_routing.h"
#include "verilog_top_netlist_utils.h"
/* ONLY for compact Verilog netlists:
@ -739,6 +740,311 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
return;
}
/* Call the defined switch box sub-circuit
* TODO: This function is also copied from
* spice_routing.c : dump_verilog_routing_switch_box_subckt
*/
static
void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_sb cur_sb_info) {
int ix, iy, side, itrack, x, y, inode;
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
__FILE__, __LINE__);
exit(1);
}
/* Check */
assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1))));
assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1))));
x = cur_sb_info.x;
y = cur_sb_info.y;
/* Comment lines */
fprintf(fp, "//----- BEGIN call module Switch blocks [%d][%d] -----\n",
cur_sb_info.x, cur_sb_info.y);
/* Print module*/
/* If we have an mirror SB, we should the module name of the mirror !!! */
if (NULL != cur_sb_info.mirror) {
fprintf(fp, "%s ", gen_verilog_one_sb_module_name(cur_sb_info.mirror));
} else {
fprintf(fp, "%s ", gen_verilog_one_sb_module_name(&cur_sb_info));
}
fprintf(fp, "%s ", gen_verilog_one_sb_instance_name(&cur_sb_info));
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
fprintf(fp, ",\n");
}
for (side = 0; side < cur_sb_info.num_sides; side++) {
determine_sb_port_coordinator(cur_sb_info, side, &ix, &iy);
fprintf(fp, "//----- %s side channel ports-----\n", convert_side_index_to_string(side));
for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) {
fprintf(fp, "%s,\n",
gen_verilog_routing_channel_one_pin_name(cur_sb_info.chan_rr_node[side][itrack],
ix, iy, itrack,
cur_sb_info.chan_rr_node_direction[side][itrack]));
}
fprintf(fp, "//----- %s side inputs: CLB output pins -----\n", convert_side_index_to_string(side));
/* Dump OPINs of adjacent CLBs */
for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[side]; inode++) {
dump_verilog_grid_side_pin_with_given_index(fp, IPIN,
cur_sb_info.opin_rr_node[side][inode]->ptc_num,
cur_sb_info.opin_rr_node_grid_side[side][inode],
cur_sb_info.opin_rr_node[side][inode]->xlow,
cur_sb_info.opin_rr_node[side][inode]->ylow,
FALSE); /* Do not specify the direction of port */
fprintf(fp, ", ");
}
fprintf(fp, "\n");
}
/* Configuration ports */
/* output of each configuration bit */
/* Reserved sram ports */
if (0 < (cur_sb_info.num_reserved_conf_bits)) {
dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
0, cur_sb_info.num_reserved_conf_bits - 1,
VERILOG_PORT_CONKT);
fprintf(fp, ",\n");
}
/* Normal sram ports */
if (0 < (cur_sb_info.conf_bits_msb - cur_sb_info.conf_bits_lsb)) {
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
cur_sb_info.conf_bits_lsb,
cur_sb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
}
/* Dump ports only visible during formal verification*/
if (0 < (cur_sb_info.conf_bits_msb - 1 - cur_sb_info.conf_bits_lsb)) {
fprintf(fp, "\n");
fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
fprintf(fp, ",\n");
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sb_info.conf_bits_lsb,
cur_sb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
fprintf(fp, ");\n");
/* Comment lines */
fprintf(fp, "//----- END call module Switch blocks [%d][%d] -----\n\n", x, y);
/* Free */
return;
}
void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
int ix, iy;
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
__FILE__, __LINE__);
exit(1);
}
for (ix = 0; ix < (nx + 1); ix++) {
for (iy = 0; iy < (ny + 1); iy++) {
dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, sb_info[ix][iy]);
}
}
return;
}
/* Call the defined sub-circuit of connection box
* TODO: actually most of this function is copied from
* spice_routing.c : dump_verilog_conneciton_box_interc
* Should be more clever to use the original function
*/
static
void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb cur_cb_info) {
int itrack, inode, side, x, y;
int side_cnt = 0;
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
__FILE__, __LINE__);
exit(1);
}
/* Check */
assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1))));
assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1))));
x = cur_cb_info.x;
y = cur_cb_info.y;
/* Comment lines */
fprintf(fp,
"//----- BEGIN Call Connection Box for %s direction [%d][%d] module -----\n",
convert_chan_type_to_string(cur_cb_info.type),
x, y);
/* Print module */
/* If we have an mirror SB, we should the module name of the mirror !!! */
if (NULL != cur_cb_info.mirror) {
fprintf(fp, "%s ", gen_verilog_one_cb_module_name(cur_cb_info.mirror));
} else {
fprintf(fp, "%s ", gen_verilog_one_cb_module_name(&cur_cb_info));
}
fprintf(fp, "%s ", gen_verilog_one_cb_instance_name(&cur_cb_info));
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
fprintf(fp, ",\n");
}
/* Print the ports of channels*/
/* connect to the mid point of a track*/
side_cnt = 0;
for (side = 0; side < cur_cb_info.num_sides; side++) {
/* Bypass side with zero channel width */
if (0 == cur_cb_info.chan_width[side]) {
continue;
}
assert (0 < cur_cb_info.chan_width[side]);
side_cnt++;
fprintf(fp, "//----- %s side inputs: channel track middle outputs -----\n", convert_side_index_to_string(side));
for (itrack = 0; itrack < cur_cb_info.chan_width[side]; itrack++) {
fprintf(fp, "%s, ",
gen_verilog_routing_channel_one_midout_name(&cur_cb_info, itrack));
fprintf(fp, "\n");
}
}
/*check side_cnt */
assert(1 == side_cnt);
side_cnt = 0;
/* Print the ports of grids*/
for (side = 0; side < cur_cb_info.num_sides; side++) {
/* Bypass side with zero IPINs*/
if (0 == cur_cb_info.num_ipin_rr_nodes[side]) {
continue;
}
side_cnt++;
assert(0 < cur_cb_info.num_ipin_rr_nodes[side]);
assert(NULL != cur_cb_info.ipin_rr_node[side]);
fprintf(fp, "//----- %s side outputs: CLB input pins -----\n", convert_side_index_to_string(side));
for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) {
/* Print each INPUT Pins of a grid */
dump_verilog_grid_side_pin_with_given_index(fp, OPIN,
cur_cb_info.ipin_rr_node[side][inode]->ptc_num,
cur_cb_info.ipin_rr_node_grid_side[side][inode],
cur_cb_info.ipin_rr_node[side][inode]->xlow,
cur_cb_info.ipin_rr_node[side][inode]->ylow,
FALSE); /* Do not specify direction of port */
fprintf(fp, ", \n");
}
}
/* Make sure only 2 sides of IPINs are printed */
assert((1 == side_cnt)||(2 == side_cnt));
/* Configuration ports */
/* Reserved sram ports */
if (0 < (cur_cb_info.num_reserved_conf_bits)) {
dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
0, cur_cb_info.num_reserved_conf_bits - 1,
VERILOG_PORT_CONKT);
fprintf(fp, ",\n");
}
/* Normal sram ports */
if (0 < (cur_cb_info.conf_bits_msb - cur_cb_info.conf_bits_lsb)) {
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
cur_cb_info.conf_bits_lsb, cur_cb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
}
/* Dump ports only visible during formal verification*/
if (0 < (cur_cb_info.conf_bits_msb - 1 - cur_cb_info.conf_bits_lsb)) {
fprintf(fp, "\n");
fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
fprintf(fp, ",\n");
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_cb_info.conf_bits_lsb,
cur_cb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
fprintf(fp, ");\n");
/* Comment lines */
switch(cur_cb_info.type) {
case CHANX:
fprintf(fp, "//----- END call Connection Box-X direction [%d][%d] module -----\n\n", x, y);
break;
case CHANY:
fprintf(fp, "//----- END call Connection Box-Y direction [%d][%d] module -----\n\n", x, y);
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__);
exit(1);
}
/* Check */
assert((1 == side_cnt)||(2 == side_cnt));
return;
}
/* Call the sub-circuits for connection boxes */
void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
int ix, iy;
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
__FILE__, __LINE__);
exit(1);
}
/* X - channels [1...nx][0..ny]*/
for (iy = 0; iy < (ny + 1); iy++) {
for (ix = 1; ix < (nx + 1); ix++) {
if ((TRUE == is_cb_exist(CHANX, ix, iy))
&&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cbx_info[ix][iy]);
}
}
}
/* Y - channels [1...ny][0..nx]*/
for (ix = 0; ix < (nx + 1); ix++) {
for (iy = 1; iy < (ny + 1); iy++) {
if ((TRUE == is_cb_exist(CHANY, ix, iy))
&&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cby_info[ix][iy]);
}
}
}
return;
}
/** Print Top-level SPICE netlist in a compact way
* Instance unique submodules (I/O, CLB, Heterogeneous block) for the full grids
*/
@ -754,6 +1060,7 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
t_ivec*** LL_rr_node_indices,
int num_clock,
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy,
t_spice verilog) {
FILE* fp = NULL;
char* formatted_dir_path = NULL;
@ -809,10 +1116,18 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices);
/* Quote Routing structures: Switch Boxes */
dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp);
if (TRUE == compact_routing_hierarchy ) {
dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp);
} else {
dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp);
}
/* Quote Routing structures: Connection Boxes */
dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp);
if (TRUE == compact_routing_hierarchy ) {
dump_compact_verilog_defined_connection_boxes(cur_sram_orgz_info, fp);
} else {
dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp);
}
/* Quote defined Logic blocks subckts (Grids) */
dump_compact_verilog_defined_grids(cur_sram_orgz_info, fp);

1
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h
View File

@ -24,5 +24,6 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
t_ivec*** LL_rr_node_indices,
int num_clock,
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy,
t_spice verilog);

70
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -1107,7 +1107,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
t_sb* cur_sb_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_syn_verilog_opts fpga_verilog_opts) {
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy) {
int itrack, inode, side, ix, iy, x, y;
int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt;
FILE* fp = NULL;
@ -1131,6 +1132,20 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
cur_sb_info->num_reserved_conf_bits = num_reserved_conf_bits;
cur_sb_info->conf_bits_lsb = cur_num_sram;
cur_sb_info->conf_bits_msb = cur_num_sram + num_conf_bits;
/* Handle mirror switch blocks:
* For mirrors, no need to output a file
* Just update the counter
*/
if ( (TRUE == compact_routing_hierarchy)
&& (NULL != cur_sb_info->mirror) ) {
/* Again ensure the conf_bits should match !!! */
/* Count the number of configuration bits of the mirror */
int mirror_num_conf_bits = count_verilog_switch_box_conf_bits(cur_sram_orgz_info, cur_sb_info->mirror);
assert( mirror_num_conf_bits == num_conf_bits );
/* return directly */
return;
}
/* Create file handler */
fp = verilog_create_one_subckt_file(subckt_dir, "Switch Block ", sb_verilog_file_name_prefix, cur_sb_info->x, cur_sb_info->y, &fname);
@ -1755,7 +1770,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
t_cb* cur_cb_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_syn_verilog_opts fpga_verilog_opts) {
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy) {
int itrack, inode, side, x, y;
int side_cnt = 0;
FILE* fp = NULL;
@ -1768,7 +1784,34 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
x= cur_cb_info->x;
y= cur_cb_info->y;
/* Count the number of configuration bits */
/* Count the number of configuration bits to be consumed by this Switch block */
num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, cur_cb_info);
/* Count the number of reserved configuration bits to be consumed by this Switch block */
num_reserved_conf_bits = count_verilog_connection_box_reserved_conf_bits(cur_sram_orgz_info, cur_cb_info);
/* Estimate the sram_verilog_model->cnt */
cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
esti_sram_cnt = cur_num_sram + num_conf_bits;
/* Record index */
cur_cb_info->num_reserved_conf_bits = num_reserved_conf_bits;
cur_cb_info->conf_bits_lsb = cur_num_sram;
cur_cb_info->conf_bits_msb = cur_num_sram + num_conf_bits;
/* Handle mirror switch blocks:
* For mirrors, no need to output a file
* Just update the counter
*/
if ( (TRUE == compact_routing_hierarchy)
&& (NULL != cur_cb_info->mirror) ) {
/* Again ensure the conf_bits should match !!! */
/* Count the number of configuration bits of the mirror */
int mirror_num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, cur_cb_info->mirror);
assert( mirror_num_conf_bits == num_conf_bits );
/* return directly */
return;
}
/* Print the definition of subckt*/
/* Identify the type of connection box */
switch(cur_cb_info->type) {
@ -1850,18 +1893,6 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
/* Make sure only 2 sides of IPINs are printed */
assert((1 == side_cnt)||(2 == side_cnt));
/* Count the number of configuration bits */
/* Count the number of configuration bits to be consumed by this Switch block */
num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, cur_cb_info);
/* Count the number of reserved configuration bits to be consumed by this Switch block */
num_reserved_conf_bits = count_verilog_connection_box_reserved_conf_bits(cur_sram_orgz_info, cur_cb_info);
/* Estimate the sram_verilog_model->cnt */
cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
esti_sram_cnt = cur_num_sram + num_conf_bits;
/* Record index */
cur_cb_info->num_reserved_conf_bits = num_reserved_conf_bits;
cur_cb_info->conf_bits_lsb = cur_num_sram;
cur_cb_info->conf_bits_msb = cur_num_sram + num_conf_bits;
/* Put down configuration port */
/* output of each configuration bit */
@ -1956,7 +1987,8 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
t_syn_verilog_opts fpga_verilog_opts) {
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy) {
int ix, iy;
assert(UNI_DIRECTIONAL == routing_arch->directionality);
@ -2005,7 +2037,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models);
dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(sb_info[ix][iy]),
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices,
fpga_verilog_opts);
fpga_verilog_opts, compact_routing_hierarchy);
update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models);
}
}
@ -2020,7 +2052,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
&&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) {
dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cbx_info[ix][iy]),
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices,
fpga_verilog_opts);
fpga_verilog_opts, compact_routing_hierarchy);
}
update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models);
}
@ -2034,7 +2066,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
&&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) {
dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cby_info[ix][iy]),
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices,
fpga_verilog_opts);
fpga_verilog_opts, compact_routing_hierarchy);
}
update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models);
}

9
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h
View File

@ -67,7 +67,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
t_sb* cur_sb_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_syn_verilog_opts fpga_verilog_opts);
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy);
void dump_verilog_connection_box_short_interc(t_sram_orgz_info* cur_sram_orgz_info,
@ -111,7 +112,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
t_cb* cur_cb_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_syn_verilog_opts fpga_verilog_opts);
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy);
void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
@ -122,5 +124,6 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
t_syn_verilog_opts fpga_verilog_opts);
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy);

1773
vpr7_x2p/vpr/SRC/tags
View File

File diff suppressed because it is too large Load Diff

2
vpr7_x2p/vpr/go_fpga_verilog.sh
View File

@ -37,7 +37,7 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname
# Run VPR
#valgrind
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis #--fpga_verilog_print_report_timing_tcl
echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl "