From a3c3f2b8920e5066099d69803fad897ea936d38f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 8 May 2019 20:49:21 -0600 Subject: [PATCH 1/4] developing compact routing hierarchy --- vpr7_x2p/vpr/SRC/base/OptionTokens.c | 1 + vpr7_x2p/vpr/SRC/base/OptionTokens.h | 1 + vpr7_x2p/vpr/SRC/base/ReadOptions.c | 3 + vpr7_x2p/vpr/SRC/base/SetupVPR.c | 6 + vpr7_x2p/vpr/SRC/base/vpr_api.c | 1 + vpr7_x2p/vpr/SRC/base/vpr_types.h | 26 +++ .../base/fpga_x2p_backannotate_utils.c | 20 ++ .../fpga_x2p/base/fpga_x2p_identify_routing.c | 200 ++++++++++++++++++ .../fpga_x2p/base/fpga_x2p_identify_routing.h | 13 ++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c | 14 +- .../SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.c | 1 + .../SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.h | 1 + 12 files changed, 286 insertions(+), 1 deletion(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.h diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.c b/vpr7_x2p/vpr/SRC/base/OptionTokens.c index d96645aac..18b502e01 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.c +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.c @@ -61,6 +61,7 @@ struct s_TokenPair OptionBaseTokenList[] = { { "fpga_x2p_rename_illegal_port", OT_FPGA_X2P_RENAME_ILLEGAL_PORT }, /* Xifan TANG: rename illegal port names */ { "fpga_x2p_signal_density_weight", OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT }, /* The weight of signal density */ { "fpga_x2p_sim_window_size", OT_FPGA_X2P_SIM_WINDOW_SIZE }, /* Window size in determining number of clock cycles in simulation */ + { "fpga_x2p_compact_routing_hierarchy", OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY }, /* use a compact routing hierarchy in SPICE/Verilog generation */ /* Xifan TANG: FPGA SPICE Support */ { "fpga_spice", OT_FPGA_SPICE },/* Xifan TANG: SPICE Model Support, turn on the functionality*/ { "fpga_spice_dir", OT_FPGA_SPICE_DIR },/* Xifan TANG: SPICE Model Support, directory of spice netlists*/ diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.h b/vpr7_x2p/vpr/SRC/base/OptionTokens.h index af7392806..b188cb08e 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.h +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.h @@ -78,6 +78,7 @@ enum e_OptionBaseToken { OT_FPGA_X2P_RENAME_ILLEGAL_PORT, OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT, /* The weight of signal density in determining number of clock cycles in simulation */ OT_FPGA_X2P_SIM_WINDOW_SIZE, /* Window size in determining number of clock cycles in simulation */ + OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY, /* use a compact routing hierarchy in SPICE/Verilog generation */ /* Xifan TANG: FPGA SPICE Support */ OT_FPGA_SPICE, /* Xifan TANG: FPGA SPICE Model Support */ OT_FPGA_SPICE_DIR, /* Xifan TANG: FPGA SPICE Model Support */ diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c index 6d3697e69..c6d1a4186 100644 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c +++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.c @@ -481,6 +481,9 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) { return ReadFloat(Args, &Options->fpga_spice_signal_density_weight); case OT_FPGA_X2P_SIM_WINDOW_SIZE: return ReadFloat(Args, &Options->fpga_spice_sim_window_size); + case OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY: + /* use a compact routing hierarchy in SPICE/Verilog generation */ + return Args; /* Xifan TANG: FPGA SPICE Model Options*/ case OT_FPGA_SPICE: return Args; diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 304ec022a..e8038bc30 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -1235,6 +1235,12 @@ static void SetupFpgaSpiceOpts(t_options Options, fpga_spice_opts->sim_window_size = Options.fpga_spice_sim_window_size; } + /* Check if user wants to use a compact routing hierarchy */ + fpga_spice_opts->compact_routing_hierarchy = FALSE; + if (Options.Count[OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY]) { + fpga_spice_opts->compact_routing_hierarchy = TRUE; + } + /* Decide if we need to do FPGA-SPICE */ fpga_spice_opts->do_fpga_spice = FALSE; if (( TRUE == fpga_spice_opts->SpiceOpts.do_spice) diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index 24fa4ed77..9fecb247e 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -170,6 +170,7 @@ void vpr_print_usage(void) { vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_rename_illegal_port\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_signal_density_weight \n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_sim_window_size \n"); + vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_compact_routing_hierarchy\n"); vpr_printf(TIO_MESSAGE_INFO, "SPICE Support Options:\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_dir \n"); diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index aeea025db..08daffb98 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -1153,6 +1153,18 @@ struct s_sb { int num_reserved_conf_bits; /* number of reserved configuration bits */ int conf_bits_lsb; /* LSB of configuration bits */ int conf_bits_msb; /* MSB of configuration bits */ + + /* For identical SBs */ + t_sb* mirror; /* an exact mirror of this switch block, with same connection & switches */ + /* an rotatable mirror of this switch block, + * the two switch blocks will be same in terms of connection & switches + * by applying an offset to the connection & switches + */ + t_sb* rotatable; + /* Offset to be applied for each side of nodes */ + int* offset_ipin; /* [0, ..., num_sides-1]*/ + int* offset_opin; /* [0, ..., num_sides-1]*/ + int* offset_chan; /* [0, ..., num_sides-1]*/ }; /* Information for each conneciton block */ @@ -1188,6 +1200,18 @@ struct s_cb { int num_reserved_conf_bits; /* number of reserved configuration bits */ int conf_bits_lsb; /* LSB of configuration bits */ int conf_bits_msb; /* MSB of configuration bits */ + + /* For identical SBs */ + t_cb* mirror; /* an exact mirror of this connection block, with same connection & switches */ + /* an rotatable mirror of this connection block, + * the two connection blocks will be same in terms of connection & switches + * by applying an offset to the connection & switches + */ + t_cb* rotatable; + /* Offset to be applied for each side of nodes */ + int* offset_ipin; /* [0, ..., num_sides-1]*/ + int* offset_opin; /* [0, ..., num_sides-1]*/ + int* offset_chan; /* [0, ..., num_sides-1]*/ }; /* Xifan TANG: SPICE Support*/ @@ -1255,6 +1279,8 @@ struct s_fpga_spice_opts { t_syn_verilog_opts SynVerilogOpts; /* Xifan TANG: Synthesizable verilog dumping*/ t_bitstream_gen_opts BitstreamGenOpts; /* Xifan Bitsteam Generator */ + boolean compact_routing_hierarchy; /* use compact routing hierarchy */ + /* Signal Density */ float signal_density_weight; float sim_window_size; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c index 438ba3746..eb66b22d9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c @@ -206,6 +206,12 @@ void init_one_sb_info(t_sb* cur_sb) { cur_sb->conf_bits_lsb = 0; cur_sb->conf_bits_msb = 0; + cur_sb->mirror = NULL; + cur_sb->rotatable = NULL; + cur_sb->offset_ipin = NULL; + cur_sb->offset_opin = NULL; + cur_sb->offset_chan = NULL; + return; } @@ -237,6 +243,10 @@ void free_one_sb_info(t_sb* cur_sb) { my_free(cur_sb->opin_rr_node); my_free(cur_sb->opin_rr_node_grid_side); + my_free(cur_sb->offset_ipin); + my_free(cur_sb->offset_opin); + my_free(cur_sb->offset_chan); + return; } @@ -299,6 +309,12 @@ void init_one_cb_info(t_cb* cur_cb) { cur_cb->conf_bits_lsb = 0; cur_cb->conf_bits_msb = 0; + cur_cb->mirror = NULL; + cur_cb->rotatable = NULL; + cur_cb->offset_ipin = NULL; + cur_cb->offset_opin = NULL; + cur_cb->offset_chan = NULL; + return; } @@ -330,6 +346,10 @@ void free_one_cb_info(t_cb* cur_cb) { my_free(cur_cb->opin_rr_node); my_free(cur_cb->opin_rr_node_grid_side); + my_free(cur_cb->offset_ipin); + my_free(cur_cb->offset_opin); + my_free(cur_cb->offset_chan); + return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c new file mode 100644 index 000000000..b9fa237a8 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c @@ -0,0 +1,200 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" +#include "route_common.h" + +/* Include spice support headers*/ +#include "read_xml_spice_util.h" +#include "linkedlist.h" +#include "fpga_x2p_types.h" +#include "fpga_x2p_globals.h" +#include "fpga_x2p_utils.h" + + +void assign_switch_block_mirror(t_sb* src, t_sb* des) { + assert ( (NULL != src) && (NULL != des) ); + /* check if the mirror of the first SB is assigned */ + if (NULL != src->mirror) { + /* Assign mirror of the first SB to the second SB */ + /* traceback to the upstream */ + t_sb* temp = src->mirror; + while (NULL != temp->mirror) { + /* go to the next */ + temp = temp->mirror; + } + /* We reach the upstream, ensure its mirror is empty */ + assert(NULL == temp->mirror); + des->mirror = temp; + } else { + /* Assign the first SB as the mirror to the second SB */ + des->mirror = src; + } + + return; +} + +/* Idenify mirror Switch blocks + * Check each two switch blocks: + * 1. Number of channel/opin/ipin rr_nodes are same + * For channel rr_nodes + * 2. check if their track_ids (ptc_num) are same + * 3. Check if the switches (ids) are same + * For opin/ipin rr_nodes, + * 4. check if their parent type_descriptors same, + * 5. check if pin class id and pin id are same + * If all above are satisfied, the two switch blocks are mirrors! + */ +boolean is_two_switch_blocks_mirror(t_sb* src, t_sb* des) { + return FALSE; +} + +/* Walk through all the switch blocks, + * Make one-to-one comparison, + * If we have a pair, update the 1st SB to be the base and label the 2nd as a mirror + * If the 1st SB is already a mirror to another, we will trace back to the upstream base and update the 2nd SB + */ +void assign_mirror_switch_blocks() { + + /* Walkthrough each column, and find mirrors */ + for (int ix = 0; ix < (nx + 1); ++ix) { + for (int iy = 0; iy < (ny + 1); ++iy) { + for (int jy = iy; jy < (ny + 1); ++jy) { + /* Do one-to-one comparison */ + if (FALSE == is_two_switch_blocks_mirror(&(sb_info[ix][iy]), &(sb_info[ix][jy]))) { + /* Nothing to do if the two switch blocks are not equivalent */ + continue; + } + /* configure the mirror of the second switch block */ + assign_switch_block_mirror(&(sb_info[ix][iy]), &(sb_info[ix][jy])); + } + } + } + /* Now mirror switch blocks in each column has been annotated */ + + /* Walkthrough each row, and find mirrors */ + for (int iy = 0; iy < (ny + 1); ++iy) { + for (int ix = 0; ix < (nx + 1); ++ix) { + for (int jx = ix; jx < (nx + 1); ++jx) { + /* Do one-to-one comparison */ + if (FALSE == is_two_switch_blocks_mirror(&(sb_info[ix][iy]), &(sb_info[jx][iy]))) { + /* Nothing to do if the two switch blocks are not equivalent */ + continue; + } + /* configure the mirror of the second switch block */ + assign_switch_block_mirror(&(sb_info[ix][iy]), &(sb_info[jx][iy])); + } + } + } + + return; +} + +/* Validate the mirror of a switch block is the upstream + * with NULL mirror + */ +boolean validate_one_switch_block_mirror(t_sb* cur_sb) { + if (NULL == cur_sb->mirror) { + /* This is the upstream */ + return TRUE; + } + if (NULL == cur_sb->mirror->mirror) { + return FALSE; + } + return TRUE; +} + +/* update the mirror of each switch block */ +void update_one_switch_block_mirror(t_sb* cur_sb) { + + if (NULL == cur_sb->mirror) { + /* This is the upstream */ + return; + } + + /* Assign mirror of the first SB to the second SB */ + /* traceback to the upstream */ + t_sb* temp = cur_sb->mirror; + while (NULL != temp->mirror) { + /* go to the next */ + temp = temp->mirror; + } + /* We reach the upstream, ensure its mirror is empty */ + assert(NULL == temp->mirror); + cur_sb->mirror = temp; + + return; +} + +/* Validate the mirror of each switch block is the upstream */ +boolean validate_mirror_switch_blocks() { + boolean ret = TRUE; + + /* Walkthrough each column, and find mirrors */ + for (int ix = 0; ix < (nx + 1); ++ix) { + for (int iy = 0; iy < (ny + 1); ++iy) { + if (FALSE == validate_one_switch_block_mirror(&(sb_info[ix][iy]))) { + ret = FALSE; + } + } + } + + return ret; +} + +/* Validate the mirror of each switch block is the upstream */ +void update_mirror_switch_blocks() { + + /* Walkthrough each column, and find mirrors */ + for (int ix = 0; ix < (nx + 1); ++ix) { + for (int iy = 0; iy < (ny + 1); ++iy) { + update_one_switch_block_mirror(&(sb_info[ix][iy])); + } + } + + return; +} + + + +void identify_mirror_switch_blocks() { + /* Assign the mirror of each switch block */ + assign_mirror_switch_blocks(); + + /* Ensure all the mirror are the upstream */ + update_mirror_switch_blocks(); + + /* Validate the mirror of switch blocks, everyone should be the upstream */ + assert(TRUE == validate_mirror_switch_blocks()); +} + +/* Idenify mirror Connection blocks */ +void identify_mirror_connection_blocks() { + return; +} + + +/* Rotatable will be done in the next step +void identify_rotatable_switch_blocks(); +void identify_rotatable_connection_blocks(); +*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.h new file mode 100644 index 000000000..bb3649850 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.h @@ -0,0 +1,13 @@ +/* Avoid repeated header inclusion */ +#ifndef FPGA_X2P_IDENTIFY_ROUTING +#define FPGA_X2P_IDENTIFY_ROUTING + +void identify_mirror_switch_blocks(); +void identify_mirror_connection_blocks(); + +/* Rotatable will be done in the next step +identify_rotatable_switch_blocks(); +identify_rotatable_connection_blocks(); +*/ + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index 8c828ac71..9ccc92fc7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -31,6 +31,7 @@ #include "fpga_x2p_backannotate_utils.h" #include "fpga_x2p_pbtypes_utils.h" #include "verilog_api.h" +#include "fpga_x2p_identify_routing.h" #include "fpga_x2p_setup.h" /***** Subroutines Declarations *****/ @@ -1302,7 +1303,7 @@ void fpga_x2p_free(t_arch* Arch) { /* Top-level function of FPGA-SPICE setup */ void fpga_x2p_setup(t_vpr_setup vpr_setup, - t_arch* Arch) { + t_arch* Arch) { int num_rename_violation = 0; int num_clocks = 0; float vpr_crit_path_delay = 0.; @@ -1386,6 +1387,17 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup, vpr_setup.FPGA_SPICE_Opts.read_act_file, vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_parasitic_net_estimation); + /* Try to use mirror SBs/CBs if enabled by user */ + if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) { + /* Idenify mirror and rotatable Switch blocks and Connection blocks */ + identify_mirror_switch_blocks(); + identify_mirror_connection_blocks(); + /* Rotatable will be done in the next step + identify_rotatable_switch_blocks(); + identify_rotatable_connection_blocks(); + */ + } + /* Not should be done when read_act_file is disabled */ if (FALSE == vpr_setup.FPGA_SPICE_Opts.read_act_file) { return; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.c index fd55acb66..0b3a9b449 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.c @@ -31,6 +31,7 @@ boolean shell_setup_fpga_x2p_setup(t_shell_env* env, t_opt_info* opts) { env->vpr_setup.FPGA_SPICE_Opts.rename_illegal_port = is_opt_set(opts, "rename_illegal_port", FALSE); env->vpr_setup.FPGA_SPICE_Opts.signal_density_weight = get_opt_float_val(opts, "signal_density_weight", 1.); env->vpr_setup.FPGA_SPICE_Opts.sim_window_size = get_opt_float_val(opts, "sim_window_size", 0.5); + env->vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy = is_opt_set(opts, "compact_routing_hierarchy", FALSE); return TRUE; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.h index 3d967900d..23b418dfa 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.h @@ -6,6 +6,7 @@ t_opt_info fpga_x2p_setup_opts[] = { {"rename_illegal_port", "-rip,--rename_illegal_port", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Rename illegal ports that violates Verilog syntax"}, {"signal_density_weight", "-sdw,--signal_density_weight", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, "Specify the signal density weight when doing the average number"}, {"sim_window_size", "-sws,--sim_window_size", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, "Specify the size of window when doing simulation"}, + {"compact_routing_hierarchy", "-crh,--compact_routing_hierarchy", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify if use a compact routing hierarchy in SPIC/Verilog generation"}, {HELP_OPT_TAG, HELP_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"}, {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"} }; From a9df9224129791cf368f1083bd218983833eac3f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 9 May 2019 21:31:39 -0600 Subject: [PATCH 2/4] finish the identification on mirror switch and connection blocks Verilog generator to be updated --- .../fpga_x2p/base/fpga_x2p_identify_routing.c | 503 ++++- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 12 +- vpr7_x2p/vpr/SRC/tags | 1773 +---------------- vpr7_x2p/vpr/go_fpga_verilog.sh | 2 +- 4 files changed, 553 insertions(+), 1737 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c index b9fa237a8..a58207993 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c @@ -30,8 +30,50 @@ #include "fpga_x2p_types.h" #include "fpga_x2p_globals.h" #include "fpga_x2p_utils.h" +#include "fpga_x2p_backannotate_utils.h" +#include "fpga_x2p_identify_routing.h" + +/***** subroutines declaration *****/ +void assign_switch_block_mirror(t_sb* src, t_sb* des); + +void assign_connection_block_mirror(t_cb* src, t_cb* des); + +boolean is_two_sb_rr_nodes_mirror(t_sb* src_sb, t_sb* des_sb, int side, + t_rr_node* src_rr_node, t_rr_node* des_rr_node); + +boolean is_two_cb_rr_nodes_mirror(t_cb* src_cb, t_cb* des_cb, + t_rr_node* src_rr_node, t_rr_node* des_rr_node); + +boolean is_two_switch_blocks_mirror(t_sb* src, t_sb* des); + +boolean is_two_connection_blocks_mirror(t_cb* src, t_cb* des); + +void assign_mirror_switch_blocks(); + +void assign_mirror_connection_blocks(); + +boolean validate_one_switch_block_mirror(t_sb* cur_sb); + +boolean validate_one_connection_block_mirror(t_cb* cur_cb); + +void update_one_switch_block_mirror(t_sb* cur_sb); + +void update_one_connection_block_mirror(t_cb* cur_cb); + +boolean validate_mirror_switch_blocks(); + +boolean validate_mirror_connection_blocks(); + +void update_mirror_switch_blocks(); + +void update_mirror_connection_blocks(); + +void print_mirror_switch_block_stats(); + +void print_mirror_connection_block_stats(); +/***** subroutines *****/ void assign_switch_block_mirror(t_sb* src, t_sb* des) { assert ( (NULL != src) && (NULL != des) ); /* check if the mirror of the first SB is assigned */ @@ -54,6 +96,111 @@ void assign_switch_block_mirror(t_sb* src, t_sb* des) { return; } +void assign_connection_block_mirror(t_cb* src, t_cb* des) { + assert ( (NULL != src) && (NULL != des) ); + /* check if the mirror of the first SB is assigned */ + if (NULL != src->mirror) { + /* Assign mirror of the first SB to the second SB */ + /* traceback to the upstream */ + t_cb* temp = src->mirror; + while (NULL != temp->mirror) { + /* go to the next */ + temp = temp->mirror; + } + /* We reach the upstream, ensure its mirror is empty */ + assert(NULL == temp->mirror); + des->mirror = temp; + } else { + /* Assign the first SB as the mirror to the second SB */ + des->mirror = src; + } + + return; +} + + +/* check if two rr_nodes have a similar set of drive_rr_nodes + * for each drive_rr_node: + * 1. CHANX or CHANY: should have the same side and index + * 2. OPIN or IPIN: should have the same side and index + * 3. each drive_rr_switch should be the same + */ +boolean is_two_sb_rr_nodes_mirror(t_sb* src_sb, t_sb* des_sb, int side, + t_rr_node* src_rr_node, t_rr_node* des_rr_node) { + + /* Ensure rr_nodes are either the output of short-connection or multiplexer */ + if ( check_drive_rr_node_imply_short(*src_sb, src_rr_node, side) + != check_drive_rr_node_imply_short(*des_sb, des_rr_node, side)) { + return FALSE; + } + /* Find the driving rr_node in this sb */ + if (TRUE == check_drive_rr_node_imply_short(*src_sb, src_rr_node, side)) { + /* Ensure we have the same track id for the driving nodes */ + if ( is_rr_node_exist_opposite_side_in_sb_info(*src_sb, src_rr_node, side) + != is_rr_node_exist_opposite_side_in_sb_info(*des_sb, des_rr_node, side)) { + return FALSE; + } + } else { /* check driving rr_nodes */ + if ( src_rr_node->num_drive_rr_nodes != des_rr_node->num_drive_rr_nodes ) { + return FALSE; + } + for (int inode = 0; inode < src_rr_node->num_drive_rr_nodes; ++inode) { + /* node type should be the same */ + if ( src_rr_node->drive_rr_nodes[inode]->type + != des_rr_node->drive_rr_nodes[inode]->type) { + return FALSE; + } + int src_node_id, des_node_id; + int src_node_side, des_node_side; + get_rr_node_side_and_index_in_sb_info(src_rr_node->drive_rr_nodes[inode], *src_sb, OUT_PORT, &src_node_side, &src_node_id); + get_rr_node_side_and_index_in_sb_info(des_rr_node->drive_rr_nodes[inode], *des_sb, OUT_PORT, &des_node_side, &des_node_id); + if (src_node_id != des_node_id) { + return FALSE; + } + if (src_node_side != des_node_side) { + return FALSE; + } + } + } + + return TRUE; +} + +/* check if two rr_nodes have a similar set of drive_rr_nodes + * for each drive_rr_node: + * 1. CHANX or CHANY: should have the same side and index + * 2. OPIN or IPIN: should have the same side and index + * 3. each drive_rr_switch should be the same + */ +boolean is_two_cb_rr_nodes_mirror(t_cb* src_cb, t_cb* des_cb, + t_rr_node* src_rr_node, t_rr_node* des_rr_node) { + + /* check driving rr_nodes */ + if ( src_rr_node->num_drive_rr_nodes != des_rr_node->num_drive_rr_nodes ) { + return FALSE; + } + for (int inode = 0; inode < src_rr_node->num_drive_rr_nodes; ++inode) { + /* node type should be the same */ + if ( src_rr_node->drive_rr_nodes[inode]->type + != des_rr_node->drive_rr_nodes[inode]->type) { + return FALSE; + } + int src_node_id, des_node_id; + int src_node_side, des_node_side; + get_rr_node_side_and_index_in_cb_info(src_rr_node->drive_rr_nodes[inode], *src_cb, OUT_PORT, &src_node_side, &src_node_id); + get_rr_node_side_and_index_in_cb_info(des_rr_node->drive_rr_nodes[inode], *des_cb, OUT_PORT, &des_node_side, &des_node_id); + if (src_node_id != des_node_id) { + return FALSE; + } + if (src_node_side != des_node_side) { + return FALSE; + } + } + + return TRUE; +} + + /* Idenify mirror Switch blocks * Check each two switch blocks: * 1. Number of channel/opin/ipin rr_nodes are same @@ -66,7 +213,54 @@ void assign_switch_block_mirror(t_sb* src, t_sb* des) { * If all above are satisfied, the two switch blocks are mirrors! */ boolean is_two_switch_blocks_mirror(t_sb* src, t_sb* des) { - return FALSE; + + /* check the numbers of sides */ + if (src->num_sides != des->num_sides) { + return FALSE; + } + + /* check the numbers/directionality of channel rr_nodes */ + for (int side = 0; side < src->num_sides; ++side) { + /* Ensure we have the same channel width on this side */ + if (src->chan_width[side] != des->chan_width[side]) { + return FALSE; + } + for (int itrack = 0; itrack < src->chan_width[side]; ++itrack) { + /* Check the directionality of each node */ + if (src->chan_rr_node_direction[side][itrack] != des->chan_rr_node_direction[side][itrack]) { + return FALSE; + } + /* Check the track_id of each node */ + if (src->chan_rr_node[side][itrack]->ptc_num != des->chan_rr_node[side][itrack]->ptc_num) { + return FALSE; + } + /* For OUT_PORT rr_node, we need to check fan-in */ + if (OUT_PORT != src->chan_rr_node_direction[side][itrack]) { + continue; /* skip IN_PORT */ + } + + if (FALSE == is_two_sb_rr_nodes_mirror(src, des, side, + src->chan_rr_node[side][itrack], + des->chan_rr_node[side][itrack])) { + return FALSE; + } + } + } + + /* check the numbers of opin_rr_nodes */ + for (int side = 0; side < src->num_sides; ++side) { + if (src->num_ipin_rr_nodes[side] != des->num_ipin_rr_nodes[side]) { + return FALSE; + } + } + + /* Make sure the number of conf bits are the same */ + if ( (src->conf_bits_msb - src->conf_bits_lsb) + != (des->conf_bits_msb - des->conf_bits_lsb)) { + return FALSE; + } + + return TRUE; } /* Walk through all the switch blocks, @@ -80,6 +274,10 @@ void assign_mirror_switch_blocks() { for (int ix = 0; ix < (nx + 1); ++ix) { for (int iy = 0; iy < (ny + 1); ++iy) { for (int jy = iy; jy < (ny + 1); ++jy) { + /* bypass the same one */ + if (iy == jy) { + continue; + } /* Do one-to-one comparison */ if (FALSE == is_two_switch_blocks_mirror(&(sb_info[ix][iy]), &(sb_info[ix][jy]))) { /* Nothing to do if the two switch blocks are not equivalent */ @@ -96,6 +294,10 @@ void assign_mirror_switch_blocks() { for (int iy = 0; iy < (ny + 1); ++iy) { for (int ix = 0; ix < (nx + 1); ++ix) { for (int jx = ix; jx < (nx + 1); ++jx) { + /* bypass the same one */ + if (ix == jx) { + continue; + } /* Do one-to-one comparison */ if (FALSE == is_two_switch_blocks_mirror(&(sb_info[ix][iy]), &(sb_info[jx][iy]))) { /* Nothing to do if the two switch blocks are not equivalent */ @@ -118,7 +320,23 @@ boolean validate_one_switch_block_mirror(t_sb* cur_sb) { /* This is the upstream */ return TRUE; } - if (NULL == cur_sb->mirror->mirror) { + /* If the upstream has a mirror, there is a bug */ + if (NULL != cur_sb->mirror->mirror) { + return FALSE; + } + return TRUE; +} + +/* Validate the mirror of a switch block is the upstream + * with NULL mirror + */ +boolean validate_one_connection_block_mirror(t_cb* cur_cb) { + if (NULL == cur_cb->mirror) { + /* This is the upstream */ + return TRUE; + } + /* If the upstream has a mirror, there is a bug */ + if (NULL != cur_cb->mirror->mirror) { return FALSE; } return TRUE; @@ -146,6 +364,29 @@ void update_one_switch_block_mirror(t_sb* cur_sb) { return; } +/* update the mirror of each switch block */ +void update_one_connection_block_mirror(t_cb* cur_cb) { + + if (NULL == cur_cb->mirror) { + /* This is the upstream */ + return; + } + + /* Assign mirror of the first SB to the second SB */ + /* traceback to the upstream */ + t_cb* temp = cur_cb->mirror; + while (NULL != temp->mirror) { + /* go to the next */ + temp = temp->mirror; + } + /* We reach the upstream, ensure its mirror is empty */ + assert(NULL == temp->mirror); + cur_cb->mirror = temp; + + return; +} + + /* Validate the mirror of each switch block is the upstream */ boolean validate_mirror_switch_blocks() { boolean ret = TRUE; @@ -162,6 +403,33 @@ boolean validate_mirror_switch_blocks() { return ret; } + +/* Validate the mirror of each connection block is the upstream */ +boolean validate_mirror_connection_blocks() { + boolean ret = TRUE; + + /* X - channels [1...nx][0..ny]*/ + for (int iy = 0; iy < (ny + 1); iy++) { + for (int ix = 1; ix < (nx + 1); ix++) { + if (FALSE == validate_one_connection_block_mirror(&(cbx_info[ix][iy]))) { + ret = FALSE; + } + } + } + + /* Y - channels [1...ny][0..nx]*/ + for (int ix = 0; ix < (nx + 1); ix++) { + for (int iy = 1; iy < (ny + 1); iy++) { + if (FALSE == validate_one_connection_block_mirror(&(cby_info[ix][iy]))) { + ret = FALSE; + } + } + } + + return ret; +} + + /* Validate the mirror of each switch block is the upstream */ void update_mirror_switch_blocks() { @@ -175,9 +443,83 @@ void update_mirror_switch_blocks() { return; } +/* Validate the mirror of each connection block is the upstream */ +void update_mirror_connection_blocks() { + /* X - channels [1...nx][0..ny]*/ + for (int iy = 0; iy < (ny + 1); iy++) { + for (int ix = 1; ix < (nx + 1); ix++) { + update_one_connection_block_mirror(&(cbx_info[ix][iy])); + } + } + + /* Y - channels [1...ny][0..nx]*/ + for (int ix = 0; ix < (nx + 1); ix++) { + for (int iy = 1; iy < (ny + 1); iy++) { + update_one_connection_block_mirror(&(cby_info[ix][iy])); + } + } + + return; +} + + +void print_mirror_switch_block_stats() { + int num_mirror_sb = 0; + + /* Walkthrough each column, and find mirrors */ + for (int ix = 0; ix < (nx + 1); ++ix) { + for (int iy = 0; iy < (ny + 1); ++iy) { + if (NULL == sb_info[ix][iy].mirror) { + num_mirror_sb++; + } + } + } + + /* Print stats */ + vpr_printf(TIO_MESSAGE_INFO, + "Detect %d independent switch blocks from %d switch blocks.\n", + num_mirror_sb, (nx + 1) * (ny + 1) ); + + return; +} + +void print_mirror_connection_block_stats() { + int num_mirror_cbx = 0; + int num_mirror_cby = 0; + + /* X - channels [1...nx][0..ny]*/ + for (int iy = 0; iy < (ny + 1); iy++) { + for (int ix = 1; ix < (nx + 1); ix++) { + if (NULL == cbx_info[ix][iy].mirror) { + num_mirror_cbx++; + } + } + } + + /* Y - channels [1...ny][0..nx]*/ + for (int ix = 0; ix < (nx + 1); ix++) { + for (int iy = 1; iy < (ny + 1); iy++) { + if (NULL == cby_info[ix][iy].mirror) { + num_mirror_cby++; + } + } + } + + /* Print stats */ + vpr_printf(TIO_MESSAGE_INFO, + "Detect %d independent connection blocks from %d X-channel connection blocks.\n", + num_mirror_cbx, (nx + 0) * (ny + 1) ); + + vpr_printf(TIO_MESSAGE_INFO, + "Detect %d independent connection blocks from %d Y-channel connection blocks.\n", + num_mirror_cby, (nx + 1) * (ny + 0) ); + + return; +} void identify_mirror_switch_blocks() { + /* Assign the mirror of each switch block */ assign_mirror_switch_blocks(); @@ -186,10 +528,167 @@ void identify_mirror_switch_blocks() { /* Validate the mirror of switch blocks, everyone should be the upstream */ assert(TRUE == validate_mirror_switch_blocks()); + + /* print the stats */ + print_mirror_switch_block_stats(); + + return; +} + +/* Idenify mirror connection blocks + * Check each two connection blocks: + * 1. Number of channel/opin/ipin rr_nodes are same + * For channel rr_nodes + * 2. check if their track_ids (ptc_num) are same + * 3. Check if the switches (ids) are same + * For opin/ipin rr_nodes, + * 4. check if their parent type_descriptors same, + * 5. check if pin class id and pin id are same + * If all above are satisfied, the two switch blocks are mirrors! + */ +boolean is_two_connection_blocks_mirror(t_cb* src, t_cb* des) { + + /* check the numbers of sides */ + if (src->num_sides != des->num_sides) { + return FALSE; + } + + /* check the numbers/directionality of channel rr_nodes */ + for (int side = 0; side < src->num_sides; ++side) { + /* Ensure we have the same channel width on this side */ + if (src->chan_width[side] != des->chan_width[side]) { + return FALSE; + } + for (int itrack = 0; itrack < src->chan_width[side]; ++itrack) { + /* Check the directionality of each node */ + if (src->chan_rr_node_direction[side][itrack] != des->chan_rr_node_direction[side][itrack]) { + return FALSE; + } + /* Check the track_id of each node */ + if (src->chan_rr_node[side][itrack]->ptc_num != des->chan_rr_node[side][itrack]->ptc_num) { + return FALSE; + } + } + } + + /* check the equivalence of ipins */ + for (int side = 0; side < src->num_sides; ++side) { + /* Ensure we have the same number of IPINs on this side */ + if (src->num_ipin_rr_nodes[side] != des->num_ipin_rr_nodes[side]) { + return FALSE; + } + for (int inode = 0; inode < src->num_ipin_rr_nodes[side]; ++inode) { + if (FALSE == is_two_cb_rr_nodes_mirror(src, des, + src->ipin_rr_node[side][inode], + des->ipin_rr_node[side][inode])) { + return FALSE; + } + } + } + + /* Make sure the number of conf bits are the same */ + if ( (src->conf_bits_msb - src->conf_bits_lsb) + != (des->conf_bits_msb - des->conf_bits_lsb)) { + return FALSE; + } + + return TRUE; +} + +void assign_mirror_connection_blocks() { + + /* X - channels [1...nx][0..ny]*/ + for (int iy = 0; iy < (ny + 1); iy++) { + for (int ix = 1; ix < (nx + 1); ix++) { + for (int jx = ix; jx < (nx + 1); jx++) { + /* bypass the same one */ + if (ix == jx) { + continue; + } + /* Do one-to-one comparison */ + if (FALSE == is_two_connection_blocks_mirror(&(cbx_info[ix][iy]), &(cbx_info[jx][iy]))) { + /* Nothing to do if the two switch blocks are not equivalent */ + continue; + } + /* configure the mirror of the second switch block */ + assign_connection_block_mirror(&(cbx_info[ix][iy]), &(cbx_info[jx][iy])); + } + } + } + + for (int ix = 1; ix < (nx + 1); ix++) { + for (int iy = 0; iy < (ny + 1); iy++) { + for (int jy = iy; jy < (ny + 1); jy++) { + /* bypass the same one */ + if (iy == jy) { + continue; + } + /* Do one-to-one comparison */ + if (FALSE == is_two_connection_blocks_mirror(&(cbx_info[ix][iy]), &(cbx_info[ix][jy]))) { + /* Nothing to do if the two switch blocks are not equivalent */ + continue; + } + /* configure the mirror of the second switch block */ + assign_connection_block_mirror(&(cbx_info[ix][iy]), &(cbx_info[ix][jy])); + } + } + } + + /* Y - channels [1...ny][0..nx]*/ + for (int ix = 0; ix < (nx + 1); ix++) { + for (int iy = 1; iy < (ny + 1); iy++) { + for (int jy = iy; jy < (ny + 1); jy++) { + /* bypass the same one */ + if (iy == jy) { + continue; + } + /* Do one-to-one comparison */ + if (FALSE == is_two_connection_blocks_mirror(&(cby_info[ix][iy]), &(cby_info[ix][jy]))) { + /* Nothing to do if the two switch blocks are not equivalent */ + continue; + } + /* configure the mirror of the second switch block */ + assign_connection_block_mirror(&(cby_info[ix][iy]), &(cby_info[ix][jy])); + } + } + } + + for (int iy = 1; iy < (ny + 1); iy++) { + for (int ix = 0; ix < (nx + 1); ix++) { + for (int jx = ix; jx < (nx + 1); jx++) { + /* bypass the same one */ + if (ix == jx) { + continue; + } + /* Do one-to-one comparison */ + if (FALSE == is_two_connection_blocks_mirror(&(cby_info[ix][iy]), &(cby_info[jx][iy]))) { + /* Nothing to do if the two switch blocks are not equivalent */ + continue; + } + /* configure the mirror of the second switch block */ + assign_connection_block_mirror(&(cby_info[ix][iy]), &(cby_info[jx][iy])); + } + } + } + + return; } /* Idenify mirror Connection blocks */ void identify_mirror_connection_blocks() { + + /* Assign the mirror of each switch block */ + assign_mirror_connection_blocks(); + + /* Ensure all the mirror are the upstream */ + update_mirror_connection_blocks(); + + /* Validate the mirror of switch blocks, everyone should be the upstream */ + assert(TRUE == validate_mirror_connection_blocks()); + + /* print the stats */ + print_mirror_connection_block_stats(); + return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index b56d08b2a..be4d993bf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -1,3 +1,6 @@ +#ifndef FPGA_X2P_UTILS_H +#define FPGA_X2P_UTILS_H + void my_free(void* ptr); char* my_gettime(); @@ -66,15 +69,8 @@ char* chomp_spice_node_prefix(char* spice_node_prefix); char* format_spice_node_prefix(char* spice_node_prefix); - -char* format_spice_node_prefix(char* spice_node_prefix); - - - t_block* search_mapped_block(int x, int y, int z); - - char** fpga_spice_strtok(char* str, char* delims, int* len); @@ -409,3 +405,5 @@ void get_fpga_x2p_global_op_clock_ports(t_llist* head, void get_fpga_x2p_global_all_clock_ports(t_llist* head, int* num_clock_ports, t_spice_model_port*** clock_port); + +#endif diff --git a/vpr7_x2p/vpr/SRC/tags b/vpr7_x2p/vpr/SRC/tags index 2810be8f3..285dc6e8a 100644 --- a/vpr7_x2p/vpr/SRC/tags +++ b/vpr7_x2p/vpr/SRC/tags @@ -10,7 +10,6 @@ AAPACK_MAX_NET_SINKS_IGNORE ./pack/cluster.c 36;" d file: AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST ./pack/cluster.c 33;" d file: AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC ./pack/cluster.c 32;" d file: ABORTED ./place/place.c /^ REJECTED, ACCEPTED, ABORTED$/;" e enum:swap_result file: -ABSOLUTE ../../libarchfpga/include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type ABS_DIFF ./place/place_stats.c 7;" d file: ACCEPTED ./place/place.c /^ REJECTED, ACCEPTED, ABORTED$/;" e enum:swap_result file: ACTIVITY_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 5;" d @@ -20,21 +19,15 @@ ANALYSIS_CMD ./fpga_x2p/shell/shell_types.h /^ ANALYSIS_CMD,$/;" e enum:e_cmd_c ANY ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: ANYBUT ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: ANYOF ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -ARCH_TYPES_H ../../libarchfpga/include/arch_types.h 9;" d AUTO_SCHED ./base/vpr_types.h /^ AUTO_SCHED, USER_SCHED$/;" e enum:sched_type ActFile ./base/ReadOptions.h /^ char *ActFile;$/;" m struct:s_options ActFile ./base/vpr_types.h /^ char *ActFile;$/;" m struct:s_file_name_opts AnnealSched ./base/vpr_types.h /^ struct s_annealing_sched AnnealSched; \/* Placement option annealing schedule *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_annealing_sched ArchFile ./base/ReadOptions.h /^ char *ArchFile;$/;" m struct:s_options ArchFile ./base/vpr_types.h /^ char *ArchFile;$/;" m struct:s_file_name_opts -Aspect ../../libarchfpga/include/physical_types.h /^ float Aspect;$/;" m struct:s_clb_grid -BACKCHAR ../../pcre/SRC/pcre.c 213;" d file: -BACKCHAR ../../pcre/SRC/pcre.c 290;" d file: BASIC_CMD ./fpga_x2p/shell/shell_types.h /^ BASIC_CMD,$/;" e enum:e_cmd_category -BEST_CORNER ../../libarchfpga/fpga_spice_include/spice_types.h /^ BEST_CORNER,$/;" e enum:e_process_corner BISQUE ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types BI_DIRECTION ./base/vpr_types.h /^ INC_DIRECTION = 0, DEC_DIRECTION = 1, BI_DIRECTION = 2$/;" e enum:e_direction -BI_DIRECTIONAL ../../libarchfpga/include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality BLACK ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types BLIF_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 1;" d BLIF_LUT_KEYWORD ./fpga_x2p/base/fpga_x2p_types.h 18;" d @@ -46,15 +39,10 @@ BLK_STATUS_UNDEFINED ./base/vpr_types.h /^ BLK_PASSED, BLK_FAILED_FEASIBLE, BLK_ BLOCK_COUNT ./place/timing_place_lookup.c 52;" d file: BLUE ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types BOL ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -BOOL ../../pcre/SRC/internal.h /^typedef int BOOL;$/;" t -BOTTOM ../../libarchfpga/include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side -BOUNDARY ../../libarchfpga/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type BOUNDING_BOX_PLACE ./base/vpr_types.h /^ BOUNDING_BOX_PLACE, NET_TIMING_DRIVEN_PLACE, PATH_TIMING_DRIVEN_PLACE$/;" e enum:e_place_algorithm BRANCH ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -BRASTACK_SIZE ../../pcre/SRC/pcre.c 68;" d file: BREADTH_FIRST ./base/vpr_types.h /^ BREADTH_FIRST, TIMING_DRIVEN, NO_TIMING$/;" e enum:e_router_algorithm BUFFER_INSERTION_H ./mrfpga/buffer_insertion.h 2;" d -BUFSIZE ../../libarchfpga/include/util.h 23;" d BUFSIZE ./base/graphics.c 184;" d file: BUF_AND_PTRANS_FLAG ./route/check_rr_graph.c 16;" d file: BUF_FLAG ./route/check_rr_graph.c 14;" d file: @@ -66,20 +54,14 @@ BitstreamGenOpts ./base/vpr_types.h /^ t_bitstream_gen_opts BitstreamGenOpts; \ BlifFile ./base/ReadOptions.h /^ char *BlifFile;$/;" m struct:s_options BlifFile ./base/vpr_types.h /^ char *BlifFile;$/;" m struct:s_file_name_opts ButtonsWND ./base/graphics.c /^ButtonsWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: -C ../../libarchfpga/include/arch_types_mrfpga.h /^ float C; $/;" m struct:s_memristor_inf -C ../../libarchfpga/include/arch_types_mrfpga.h /^ float C;$/;" m struct:s_buffer_inf -C ../../libarchfpga/include/physical_types.h /^ float C;$/;" m union:s_port_power::__anon22 C ./base/vpr_types.h /^ float C;$/;" m struct:s_rr_node -CAD_TYPES_H ../../libarchfpga/include/cad_types.h 5;" d CAL_CAPACITANCE_H ./mrfpga/cal_capacitance.h 2;" d CHANX ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type CHANX_COST_INDEX_START ./base/vpr_types.h /^ CHANX_COST_INDEX_START$/;" e enum:e_cost_indices CHANY ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type CHECK ./place/place.c /^ NORMAL, CHECK$/;" e enum:cost_methods file: CHECK_NETLIST_H ./base/check_netlist.h 2;" d -CHECK_RAND ../../libarchfpga/util.c 734;" d file: CHECK_RR_GRAPH_H ./route/check_rr_graph.h 2;" d -CHUNK_SIZE ../../libarchfpga/util.c 208;" d file: CLOCK_DENS ./power/power.h 37;" d CLOCK_PROB ./power/power.h 36;" d CLOSE ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: @@ -87,54 +69,33 @@ CLUSTER_FEASIBILITY_CHECK_H ./pack/cluster_feasibility_filter.h 23;" d CLUSTER_LEGALITY_H ./pack/cluster_legality.h 2;" d CLUSTER_PLACEMENT_H ./pack/cluster_placement.h 7;" d CMOS_TECH_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 7;" d -COL_REL ../../libarchfpga/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type -COL_REPEAT ../../libarchfpga/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type -COMPLETE_INTERC ../../libarchfpga/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect -CONV ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp CONVERT_NM_PER_M ./power/power.c 50;" d file: CONVERT_UM_PER_M ./power/power.c 51;" d file: CORAL ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types CREATE_ERROR ./base/graphics.c 219;" d file: -CREF_RECURSE ../../pcre/SRC/internal.h 476;" d CYAN ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types C_d ./power/power.h /^ float C_d;$/;" m struct:s_transistor_size_inf C_downstream ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: C_downstream ./route/route_tree_timing.h /^ float C_downstream;$/;" m struct:s_rt_node C_downstream ./timing/net_delay_types.h /^ float C_downstream;$/;" m struct:s_rc_node C_g ./power/power.h /^ float C_g;$/;" m struct:s_transistor_size_inf -C_internal ../../libarchfpga/include/physical_types.h /^ float C_internal; \/*Internal capacitance of the pb *\/$/;" m struct:s_pb_type_power -C_ipin_cblock ../../libarchfpga/include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_arch -C_ipin_cblock ../../libarchfpga/include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_timing_inf C_load ./base/vpr_types.h /^ float C_load;$/;" m struct:s_rr_indexed_data C_s ./power/power.h /^ float C_s;$/;" m struct:s_transistor_size_inf C_tile_per_m ./base/vpr_types.h /^ float C_tile_per_m;$/;" m struct:s_rr_indexed_data -C_wire ../../libarchfpga/include/physical_types.h /^ float C_wire; \/* Wire capacitance (per meter) *\/$/;" m struct:s_clock_network -C_wire ../../libarchfpga/include/physical_types.h /^ float C_wire;$/;" m struct:s_pb_graph_pin_power -C_wire_local ../../libarchfpga/include/physical_types.h /^ float C_wire_local; \/* Capacitance of local interconnect (per meter) *\/$/;" m struct:s_power_arch -Chans ../../libarchfpga/include/physical_types.h /^ t_chan_width_dist Chans;$/;" m struct:s_arch CheckArch ./base/CheckArch.c /^void CheckArch(INP t_arch Arch, INP boolean TimingEnabled) {$/;" f -CheckElement ../../libarchfpga/read_xml_util.c /^void CheckElement(INP ezxml_t Node, INP const char *Name) {$/;" f CheckGrid ./base/SetupGrid.c /^static void CheckGrid() {$/;" f file: CheckOptions ./base/CheckOptions.c /^void CheckOptions(INP t_options Options, INP boolean TimingEnabled) {$/;" f CheckSegments ./base/CheckArch.c /^static void CheckSegments(INP t_arch Arch) {$/;" f file: CheckSetup ./base/CheckSetup.c /^void CheckSetup(INP enum e_operation Operation,$/;" f CheckSwitches ./base/CheckArch.c /^static void CheckSwitches(INP t_arch Arch, INP boolean TimingEnabled) {$/;" f file: -Cin ../../libarchfpga/include/physical_types.h /^ float Cin;$/;" m struct:s_switch_inf CircuitName ./base/ReadOptions.h /^ char *CircuitName;$/;" m struct:s_options CircuitName ./base/vpr_types.h /^ char *CircuitName;$/;" m struct:s_file_name_opts -Cmetal ../../libarchfpga/include/physical_types.h /^ float Cmetal;$/;" m struct:s_segment_inf Cmetal ./base/vpr_types.h /^ float Cmetal;$/;" m struct:s_seg_details Cmetal_per_m ./base/vpr_types.h /^ float Cmetal_per_m; \/* Used for power *\/$/;" m struct:s_seg_details CmosTechFile ./base/ReadOptions.h /^ char *CmosTechFile;$/;" m struct:s_options CmosTechFile ./base/vpr_types.h /^ char *CmosTechFile;$/;" m struct:s_file_name_opts Count ./base/ReadOptions.h /^ int Count[OT_BASE_UNKNOWN];$/;" m struct:s_options -CountChildren ../../libarchfpga/read_xml_util.c /^extern int CountChildren(INP ezxml_t Node, INP const char *Name,$/;" f -CountTokens ../../libarchfpga/ReadLine.c /^int CountTokens(INP char **Tokens) {$/;" f -CountTokensInString ../../libarchfpga/read_xml_util.c /^extern void CountTokensInString(INP const char *Str, OUTP int *Num,$/;" f -Cout ../../libarchfpga/include/physical_types.h /^ float Cout;$/;" m struct:s_switch_inf CreateEchoFile ./base/ReadOptions.h /^ boolean CreateEchoFile;$/;" m struct:s_options -CreateModelLibrary ../../libarchfpga/read_xml_arch_file.c /^static void CreateModelLibrary(OUTP struct s_arch *arch) {$/;" f file: -Cseg_global ../../libarchfpga/include/arch_types_mrfpga.h /^ float Cseg_global;$/;" m struct:s_arch_mrfpga Cseg_global ./mrfpga/mrfpga_globals.c /^float Rseg_global, Cseg_global;$/;" v DARKGREEN ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types DARKGREY ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types @@ -151,15 +112,11 @@ DEFAULT_SWITCH_ID ./fpga_x2p/base/fpga_x2p_types.h 4;" d DEGTORAD ./base/graphics.c 228;" d file: DELAY_NORMALIZED ./base/vpr_types.h /^ INTRINSIC_DELAY, DELAY_NORMALIZED, DEMAND_ONLY$/;" e enum:e_base_cost_type DELETE_ERROR ./base/graphics.c 218;" d file: -DELTA ../../libarchfpga/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat DEMAND_ONLY ./base/vpr_types.h /^ INTRINSIC_DELAY, DELAY_NORMALIZED, DEMAND_ONLY$/;" e enum:e_base_cost_type DETAILED ./base/vpr_types.h /^ GLOBAL, DETAILED$/;" e enum:e_route_type DIGIT ./timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: -DIRECT_INTERC ../../libarchfpga/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect DISCOUNT_FUNCTION_BASE ./timing/path_delay.h 23;" d DO_NOT_ANALYSE ./timing/path_delay.h 4;" d -DPRINTF ../../pcre/SRC/pcre.c 44;" d file: -DPRINTF ../../pcre/SRC/pcre.c 46;" d file: DRAW_ALL_BUT_BUFFERS_RR ./base/draw.c /^ DRAW_ALL_BUT_BUFFERS_RR,$/;" e enum:e_draw_rr_toggle file: DRAW_ALL_RR ./base/draw.c /^ DRAW_ALL_RR,$/;" e enum:e_draw_rr_toggle file: DRAW_ERROR ./base/graphics.c 220;" d file: @@ -169,117 +126,21 @@ DRAW_NORMAL ./base/graphics.h /^enum e_draw_mode {DRAW_NORMAL = 0, DRAW_XOR};$/; DRAW_NO_RR ./base/draw.c /^ DRAW_NO_RR = 0,$/;" e enum:e_draw_rr_toggle file: DRAW_RR_TOGGLE_MAX ./base/draw.c /^ DRAW_RR_TOGGLE_MAX$/;" e enum:e_draw_rr_toggle file: DRAW_XOR ./base/graphics.h /^enum e_draw_mode {DRAW_NORMAL = 0, DRAW_XOR};$/;" e enum:e_draw_mode -DRIVER ../../libarchfpga/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type DUMPFILE ./place/timing_place_lookup.c 63;" d file: -Directs ../../libarchfpga/include/physical_types.h /^ t_direct_inf *Directs;$/;" m struct:s_arch EASYGL_CONSTANTS_H ./base/easygl_constants.h 2;" d EMPTY ./base/vpr_types.h 90;" d -EMPTY_TYPE ../../libarchfpga/read_xml_arch_file.c /^static t_type_ptr EMPTY_TYPE = NULL;$/;" v file: EMPTY_TYPE ./base/globals.c /^t_type_ptr EMPTY_TYPE = NULL;$/;" v EMPTY_TYPE_BACKUP ./place/timing_place_lookup.c /^static t_type_ptr EMPTY_TYPE_BACKUP;$/;" v file: -EMPTY_TYPE_INDEX ../../libarchfpga/include/read_xml_arch_file.h 15;" d ENABLE_REVERSE ./route/rr_graph2.c 21;" d file: END ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: EOL ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: EPSILON ./base/vpr_types.h 83;" d -ERR1 ../../pcre/SRC/internal.h 483;" d -ERR10 ../../pcre/SRC/internal.h 492;" d -ERR11 ../../pcre/SRC/internal.h 493;" d -ERR12 ../../pcre/SRC/internal.h 494;" d -ERR13 ../../pcre/SRC/internal.h 495;" d -ERR14 ../../pcre/SRC/internal.h 496;" d -ERR15 ../../pcre/SRC/internal.h 497;" d -ERR16 ../../pcre/SRC/internal.h 498;" d -ERR17 ../../pcre/SRC/internal.h 499;" d -ERR18 ../../pcre/SRC/internal.h 500;" d -ERR19 ../../pcre/SRC/internal.h 501;" d -ERR2 ../../pcre/SRC/internal.h 484;" d -ERR20 ../../pcre/SRC/internal.h 502;" d -ERR21 ../../pcre/SRC/internal.h 503;" d -ERR22 ../../pcre/SRC/internal.h 504;" d -ERR23 ../../pcre/SRC/internal.h 505;" d -ERR24 ../../pcre/SRC/internal.h 506;" d -ERR25 ../../pcre/SRC/internal.h 507;" d -ERR26 ../../pcre/SRC/internal.h 508;" d -ERR27 ../../pcre/SRC/internal.h 509;" d -ERR28 ../../pcre/SRC/internal.h 510;" d -ERR29 ../../pcre/SRC/internal.h 511;" d -ERR3 ../../pcre/SRC/internal.h 485;" d -ERR30 ../../pcre/SRC/internal.h 512;" d -ERR31 ../../pcre/SRC/internal.h 513;" d -ERR32 ../../pcre/SRC/internal.h 514;" d -ERR33 ../../pcre/SRC/internal.h 515;" d -ERR34 ../../pcre/SRC/internal.h 516;" d -ERR35 ../../pcre/SRC/internal.h 517;" d -ERR36 ../../pcre/SRC/internal.h 518;" d -ERR37 ../../pcre/SRC/internal.h 519;" d -ERR38 ../../pcre/SRC/internal.h 520;" d -ERR39 ../../pcre/SRC/internal.h 521;" d -ERR4 ../../pcre/SRC/internal.h 486;" d -ERR40 ../../pcre/SRC/internal.h 522;" d -ERR41 ../../pcre/SRC/internal.h 523;" d -ERR42 ../../pcre/SRC/internal.h 524;" d -ERR43 ../../pcre/SRC/internal.h 525;" d -ERR5 ../../pcre/SRC/internal.h 487;" d -ERR6 ../../pcre/SRC/internal.h 488;" d -ERR7 ../../pcre/SRC/internal.h 489;" d -ERR8 ../../pcre/SRC/internal.h 490;" d -ERR9 ../../pcre/SRC/internal.h 491;" d ERROR_THRESHOLD ./base/check_netlist.c 15;" d file: ERROR_TOL ./place/place.c 31;" d file: ERROR_TOL ./route/route_timing.c 884;" d file: -ERRTAG ../../libarchfpga/include/util.h 26;" d -ERR_PORT ../../libarchfpga/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -ESC_A ../../pcre/SRC/internal.h /^enum { ESC_A = 1, ESC_G, ESC_B, ESC_b, ESC_D, ESC_d, ESC_S, ESC_s, ESC_W,$/;" e enum:__anon24 -ESC_B ../../pcre/SRC/internal.h /^enum { ESC_A = 1, ESC_G, ESC_B, ESC_b, ESC_D, ESC_d, ESC_S, ESC_s, ESC_W,$/;" e enum:__anon24 -ESC_C ../../pcre/SRC/internal.h /^ ESC_w, ESC_dum1, ESC_C, ESC_Z, ESC_z, ESC_E, ESC_Q, ESC_REF };$/;" e enum:__anon24 -ESC_D ../../pcre/SRC/internal.h /^enum { ESC_A = 1, ESC_G, ESC_B, ESC_b, ESC_D, ESC_d, ESC_S, ESC_s, ESC_W,$/;" e enum:__anon24 -ESC_E ../../pcre/SRC/internal.h /^ ESC_w, ESC_dum1, ESC_C, ESC_Z, ESC_z, ESC_E, ESC_Q, ESC_REF };$/;" e enum:__anon24 -ESC_G ../../pcre/SRC/internal.h /^enum { ESC_A = 1, ESC_G, ESC_B, ESC_b, ESC_D, ESC_d, ESC_S, ESC_s, ESC_W,$/;" e enum:__anon24 -ESC_Q ../../pcre/SRC/internal.h /^ ESC_w, ESC_dum1, ESC_C, ESC_Z, ESC_z, ESC_E, ESC_Q, ESC_REF };$/;" e enum:__anon24 -ESC_REF ../../pcre/SRC/internal.h /^ ESC_w, ESC_dum1, ESC_C, ESC_Z, ESC_z, ESC_E, ESC_Q, ESC_REF };$/;" e enum:__anon24 -ESC_S ../../pcre/SRC/internal.h /^enum { ESC_A = 1, ESC_G, ESC_B, ESC_b, ESC_D, ESC_d, ESC_S, ESC_s, ESC_W,$/;" e enum:__anon24 -ESC_W ../../pcre/SRC/internal.h /^enum { ESC_A = 1, ESC_G, ESC_B, ESC_b, ESC_D, ESC_d, ESC_S, ESC_s, ESC_W,$/;" e enum:__anon24 -ESC_Z ../../pcre/SRC/internal.h /^ ESC_w, ESC_dum1, ESC_C, ESC_Z, ESC_z, ESC_E, ESC_Q, ESC_REF };$/;" e enum:__anon24 -ESC_b ../../pcre/SRC/internal.h /^enum { ESC_A = 1, ESC_G, ESC_B, ESC_b, ESC_D, ESC_d, ESC_S, ESC_s, ESC_W,$/;" e enum:__anon24 -ESC_d ../../pcre/SRC/internal.h /^enum { ESC_A = 1, ESC_G, ESC_B, ESC_b, ESC_D, ESC_d, ESC_S, ESC_s, ESC_W,$/;" e enum:__anon24 -ESC_dum1 ../../pcre/SRC/internal.h /^ ESC_w, ESC_dum1, ESC_C, ESC_Z, ESC_z, ESC_E, ESC_Q, ESC_REF };$/;" e enum:__anon24 -ESC_e ../../pcre/SRC/internal.h 235;" d -ESC_f ../../pcre/SRC/internal.h 239;" d -ESC_n ../../pcre/SRC/internal.h 243;" d -ESC_r ../../pcre/SRC/internal.h 247;" d -ESC_s ../../pcre/SRC/internal.h /^enum { ESC_A = 1, ESC_G, ESC_B, ESC_b, ESC_D, ESC_d, ESC_S, ESC_s, ESC_W,$/;" e enum:__anon24 -ESC_t ../../pcre/SRC/internal.h 251;" d -ESC_w ../../pcre/SRC/internal.h /^ ESC_w, ESC_dum1, ESC_C, ESC_Z, ESC_z, ESC_E, ESC_Q, ESC_REF };$/;" e enum:__anon24 -ESC_z ../../pcre/SRC/internal.h /^ ESC_w, ESC_dum1, ESC_C, ESC_Z, ESC_z, ESC_E, ESC_Q, ESC_REF };$/;" e enum:__anon24 EXACT ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -EXTRACT_BASIC_MAX ../../pcre/SRC/internal.h 472;" d -EZXML_BUFSIZE ../../libarchfpga/include/ezxml.h 37;" d -EZXML_DUP ../../libarchfpga/include/ezxml.h 40;" d -EZXML_ERRL ../../libarchfpga/include/ezxml.h 41;" d -EZXML_NAMEM ../../libarchfpga/include/ezxml.h 38;" d -EZXML_NIL ../../libarchfpga/ezxml.c /^char *EZXML_NIL[] = { NULL }; \/* empty, null terminated array of strings *\/$/;" v -EZXML_NOMMAP ../../libarchfpga/ezxml.c 26;" d file: -EZXML_TXTM ../../libarchfpga/include/ezxml.h 39;" d -EZXML_WS ../../libarchfpga/ezxml.c 64;" d file: -E_ANNOT_PIN_TO_PIN_CAPACITANCE ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE,$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_CAPACITANCE_C ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE_C = 0$/;" e enum:e_pin_to_pin_capacitance_annotations -E_ANNOT_PIN_TO_PIN_CONSTANT ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format -E_ANNOT_PIN_TO_PIN_DELAY ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY = 0,$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_MAX ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MAX,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_MIN ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MIN = 0,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_THOLD ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_THOLD$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_TSETUP ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_TSETUP,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_MATRIX ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format -E_ANNOT_PIN_TO_PIN_MODE_SELECT ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME = 0$/;" e enum:e_pin_to_pin_mode_select_annotations -E_ANNOT_PIN_TO_PIN_PACK_PATTERN ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN,$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME = 0$/;" e enum:e_pin_to_pin_pack_pattern_annotations E_CRITICALITY_FILE ./base/ReadOptions.h /^ E_CRITICALITY_FILE,$/;" e enum:e_output_files E_CRIT_PATH_FILE ./base/ReadOptions.h /^ E_CRIT_PATH_FILE,$/;" e enum:e_output_files -E_CUSTOM_PIN_DISTR ../../libarchfpga/include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr E_DETAILED_ROUTE_AT_END_ONLY ./pack/cluster.c /^ E_DETAILED_ROUTE_AT_END_ONLY = 0, E_DETAILED_ROUTE_FOR_EACH_ATOM, E_DETAILED_ROUTE_END$/;" e enum:e_detailed_routing_stages file: E_DETAILED_ROUTE_END ./pack/cluster.c /^ E_DETAILED_ROUTE_AT_END_ONLY = 0, E_DETAILED_ROUTE_FOR_EACH_ATOM, E_DETAILED_ROUTE_END$/;" e enum:e_detailed_routing_stages file: E_DETAILED_ROUTE_FOR_EACH_ATOM ./pack/cluster.c /^ E_DETAILED_ROUTE_AT_END_ONLY = 0, E_DETAILED_ROUTE_FOR_EACH_ATOM, E_DETAILED_ROUTE_END$/;" e enum:e_detailed_routing_stages file: @@ -326,75 +187,26 @@ E_ECHO_TIMING_GRAPH ./base/ReadOptions.h /^ E_ECHO_TIMING_GRAPH,$/;" e enum:e_ec E_EXIST_BUT_NOT_DIR ./fpga_x2p/base/fpga_x2p_utils.c /^ E_EXIST_BUT_NOT_DIR,$/;" e enum:e_dir_err file: E_FILE_END_TOKEN ./base/ReadOptions.h /^ E_FILE_END_TOKEN$/;" e enum:e_output_files E_SLACK_FILE ./base/ReadOptions.h /^ E_SLACK_FILE,$/;" e enum:e_output_files -E_SPREAD_PIN_DISTR ../../libarchfpga/include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr -EchoArch ../../libarchfpga/read_xml_arch_file.c /^void EchoArch(INP const char *EchoFile, INP const t_type_descriptor * Types,$/;" f EchoEnabled ./base/ReadOptions.c /^static boolean EchoEnabled;$/;" v file: Enum ./base/vpr_types.h /^ int Enum;$/;" m struct:s_TokenPair Error ./base/ReadOptions.c /^static void Error(INP const char *Token) {$/;" f file: -FALSE ../../libarchfpga/include/util.h /^ FALSE, TRUE$/;" e enum:__anon23 -FALSE ../../pcre/SRC/internal.h 227;" d FALSE ./base/graphics.c 146;" d file: -FC_ABS ../../libarchfpga/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: -FC_FRAC ../../libarchfpga/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: -FC_FULL ../../libarchfpga/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: FEASIBLE ./pack/cluster.c /^ FEASIBLE, INFEASIBLE$/;" e enum:e_feasibility file: -FF_FE ../../libarchfpga/fpga_spice_include/spice_types.h /^ FF_RE, FF_FE$/;" e enum:e_spice_ff_trigger_type -FF_RE ../../libarchfpga/fpga_spice_include/spice_types.h /^ FF_RE, FF_FE$/;" e enum:e_spice_ff_trigger_type -FF_size ../../libarchfpga/include/physical_types.h /^ float FF_size;$/;" m struct:s_power_arch -FILL ../../libarchfpga/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type -FILL_TYPE ../../libarchfpga/read_xml_arch_file.c /^static t_type_ptr FILL_TYPE = NULL;$/;" v file: FILL_TYPE ./base/globals.c /^t_type_ptr FILL_TYPE = NULL;$/;" v FILL_TYPE_BACKUP ./place/timing_place_lookup.c /^static t_type_ptr FILL_TYPE_BACKUP;$/;" v file: FINAL_DISCOUNT_FUNCTION_BASE ./timing/path_delay.h 28;" d FIRST_ITER_WIRELENTH_LIMIT ./base/vpr_types.h 88;" d FONTMAG ./base/graphics.c 229;" d file: FPGA_SPICE_Opts ./base/vpr_types.h /^ t_fpga_spice_opts FPGA_SPICE_Opts; \/* Xifan TANG: FPGA-SPICE support *\/$/;" m struct:s_vpr_setup -FRACTIONAL ../../libarchfpga/include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type -FRAGMENT_THRESHOLD ../../libarchfpga/util.c 209;" d file: +FPGA_X2P_IDENTIFY_ROUTING ./fpga_x2p/base/fpga_x2p_identify_routing.h 3;" d +FPGA_X2P_UTILS_H ./fpga_x2p/base/fpga_x2p_utils.h 2;" d FREE ./base/vpr_types.h /^ FREE, RANDOM, USER$/;" e enum:e_pad_loc_type FROM_X_TO_Y ./base/draw.c /^ FROM_X_TO_Y, FROM_Y_TO_X$/;" e enum:e_edge_dir file: FROM_Y_TO_X ./base/draw.c /^ FROM_X_TO_Y, FROM_Y_TO_X$/;" e enum:e_edge_dir file: -FULL ../../libarchfpga/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type -Fc ../../libarchfpga/include/physical_types.h /^ float *Fc; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -Fc_type ../../libarchfpga/read_xml_arch_file.c /^enum Fc_type {$/;" g file: FileNameOpts ./base/vpr_types.h /^ struct s_file_name_opts FileNameOpts; \/* File names *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_file_name_opts -FindElement ../../libarchfpga/read_xml_util.c /^ezxml_t FindElement(INP ezxml_t Parent, INP const char *Name,$/;" f -FindFirstElement ../../libarchfpga/read_xml_util.c /^ezxml_t FindFirstElement(INP ezxml_t Parent, INP const char *Name,$/;" f -FindProperty ../../libarchfpga/read_xml_util.c /^FindProperty(INP ezxml_t Parent, INP const char *Name, INP boolean Required) {$/;" f -FreeNode ../../libarchfpga/read_xml_util.c /^void FreeNode(INOUTP ezxml_t Node) {$/;" f -FreeSpice ../../libarchfpga/read_xml_spice_util.c /^void FreeSpice(t_spice* spice) {$/;" f -FreeSpiceMeasParams ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f -FreeSpiceModel ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModel(t_spice_model* spice_model) {$/;" f -FreeSpiceModelBuffer ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModelBuffer(t_spice_model_buffer* spice_model_buffer) {$/;" f -FreeSpiceModelNetlist ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist) {$/;" f -FreeSpiceModelPassGateLogic ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModelPassGateLogic(t_spice_model_pass_gate_logic* spice_model_pass_gate_logic) {$/;" f -FreeSpiceModelPort ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModelPort(t_spice_model_port* spice_model_port) {$/;" f -FreeSpiceModelWireParam ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModelWireParam(t_spice_model_wire_param* spice_model_wire_param) {$/;" f -FreeSpiceMonteCarloParams ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f -FreeSpiceMuxArch ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceMuxArch(t_spice_mux_arch* spice_mux_arch) {$/;" f -FreeSpiceParams ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceParams(t_spice_params* params) {$/;" f -FreeSpiceStimulateParams ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f -FreeSpiceVariationParams ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f -FreeSramInf ../../libarchfpga/read_xml_spice_util.c /^void FreeSramInf(t_sram_inf* sram_inf) {$/;" f -FreeSramInfOrgz ../../libarchfpga/read_xml_spice_util.c /^void FreeSramInfOrgz(t_sram_inf_orgz* sram_inf_orgz) {$/;" f -FreeTokens ../../libarchfpga/ReadLine.c /^void FreeTokens(INOUTP char ***TokensPtr) {$/;" f -Fs ../../libarchfpga/include/physical_types.h /^ int Fs;$/;" m struct:s_arch Fs ./base/vpr_types.h /^ int Fs;$/;" m struct:s_det_routing_arch Fs_seed ./base/globals.c /^int Fs_seed = -1;$/;" v GAIN ./pack/cluster.c /^ GAIN, NO_GAIN$/;" e enum:e_gain_update file: -GAUSSIAN ../../libarchfpga/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat -GET ../../pcre/SRC/internal.h 110;" d -GET ../../pcre/SRC/internal.h 124;" d -GET ../../pcre/SRC/internal.h 97;" d -GET2 ../../pcre/SRC/internal.h 148;" d -GETCHAR ../../pcre/SRC/pcre.c 209;" d file: -GETCHAR ../../pcre/SRC/pcre.c 220;" d file: -GETCHARINC ../../pcre/SRC/pcre.c 210;" d file: -GETCHARINC ../../pcre/SRC/pcre.c 238;" d file: -GETCHARINCTEST ../../pcre/SRC/pcre.c 211;" d file: -GETCHARINCTEST ../../pcre/SRC/pcre.c 254;" d file: -GETCHARLEN ../../pcre/SRC/pcre.c 212;" d file: -GETCHARLEN ../../pcre/SRC/pcre.c 271;" d file: GLOBAL ./base/vpr_types.h /^ GLOBAL, DETAILED$/;" e enum:e_route_type GLOBALS_H ./base/globals.h 13;" d GOT_FROM_SCRATCH ./place/place.c 47;" d file: @@ -406,21 +218,13 @@ GRAPH_UNIDIR_TILEABLE ./route/rr_graph.h /^ GRAPH_UNIDIR_TILEABLE \/* Detail uni GREEN ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types Generate_PostSynthesis_Netlist ./base/ReadOptions.c /^static boolean Generate_PostSynthesis_Netlist;$/;" v file: Generate_Post_Synthesis_Netlist ./base/ReadOptions.h /^ boolean Generate_Post_Synthesis_Netlist;$/;" m struct:s_options -GetBooleanProperty ../../libarchfpga/read_xml_util.c /^extern boolean GetBooleanProperty(INP ezxml_t Parent, INP char *Name,$/;" f -GetFloatProperty ../../libarchfpga/read_xml_util.c /^extern float GetFloatProperty(INP ezxml_t Parent, INP char *Name,$/;" f -GetIntProperty ../../libarchfpga/read_xml_util.c /^extern int GetIntProperty(INP ezxml_t Parent, INP char *Name,$/;" f -GetNodeTokens ../../libarchfpga/read_xml_util.c /^GetNodeTokens(INP ezxml_t Node) {$/;" f GetPostSynthesisOption ./base/ReadOptions.c /^boolean GetPostSynthesisOption(void){$/;" f GetTokenTypeFromChar ./util/token.c /^enum e_token_type GetTokenTypeFromChar(INP enum e_token_type cur_token_type,$/;" f GetTokensFromString ./util/token.c /^t_token *GetTokensFromString(INP const char* inString, OUTP int * num_tokens) {$/;" f GraphPause ./base/ReadOptions.h /^ int GraphPause;$/;" m struct:s_options GraphPause ./base/vpr_types.h /^ int GraphPause; \/* user interactiveness graphics option *\/$/;" m struct:s_vpr_setup GraphicsWND ./base/graphics.c /^GraphicsWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: -H ../../libarchfpga/include/physical_types.h /^ int H;$/;" m struct:s_clb_grid HASHSIZE ./util/hash.h 1;" d -HAVE_BCOPY ../../pcre/SRC/config.h 38;" d -HAVE_MEMMOVE ../../pcre/SRC/config.h 32;" d -HAVE_STRERROR ../../pcre/SRC/config.h 31;" d HELP_OPT_NAME ./fpga_x2p/shell/read_opt_types.h 54;" d HELP_OPT_TAG ./fpga_x2p/shell/read_opt_types.h 53;" d HIGHLIGHTED ./base/draw.c /^ ALL_NETS, HIGHLIGHTED$/;" e enum:e_draw_net_type file: @@ -428,90 +232,54 @@ HIGH_FANOUT_NET_LIM ./base/vpr_types.h 86;" d HILL_CLIMBING ./pack/cluster.c /^ HILL_CLIMBING, NOT_HILL_CLIMBING$/;" e enum:e_gain_type file: HUGE_NEGATIVE_FLOAT ./base/vpr_types.h 80;" d HUGE_POSITIVE_FLOAT ./base/vpr_types.h 79;" d -IA ../../libarchfpga/util.c 731;" d file: -IC ../../libarchfpga/util.c 732;" d file: -IM ../../libarchfpga/util.c 733;" d file: IMPOSSIBLE ./place/timing_place_lookup.h 1;" d INC_DIRECTION ./base/vpr_types.h /^ INC_DIRECTION = 0, DEC_DIRECTION = 1, BI_DIRECTION = 2$/;" e enum:e_direction INFEASIBLE ./pack/cluster.c /^ FEASIBLE, INFEASIBLE$/;" e enum:e_feasibility file: INFINITE ./base/place_and_route.h 1;" d -INOUTP ../../libarchfpga/include/util.h 21;" d -INOUT_PORT ../../libarchfpga/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -INP ../../libarchfpga/include/util.h 19;" d INPUT ./pack/cluster.c /^ INPUT, OUTPUT$/;" e enum:e_net_relation_to_clustered_block file: -INPUT2INPUT_INTERC ../../libarchfpga/fpga_spice_include/spice_types.h /^ INPUT2INPUT_INTERC, $/;" e enum:e_spice_pin2pin_interc_type INTRA_CLUSTER_EDGE ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type INTRINSIC_DELAY ./base/vpr_types.h /^ INTRINSIC_DELAY, DELAY_NORMALIZED, DEMAND_ONLY$/;" e enum:e_base_cost_type INV_1X_C ./power/power.h /^ float INV_1X_C;$/;" m struct:s_power_commonly_used INV_1X_C_in ./power/power.h /^ float INV_1X_C_in;$/;" m struct:s_power_commonly_used INV_2X_C ./power/power.h /^ float INV_2X_C;$/;" m struct:s_power_commonly_used -IN_PORT ../../libarchfpga/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -IO_TYPE ../../libarchfpga/read_xml_arch_file.c /^static t_type_ptr IO_TYPE = NULL;$/;" v file: IO_TYPE ./base/globals.c /^t_type_ptr IO_TYPE = NULL;$/;" v IO_TYPE_BACKUP ./place/timing_place_lookup.c /^static t_type_ptr IO_TYPE_BACKUP;$/;" v file: -IO_TYPE_INDEX ../../libarchfpga/include/read_xml_arch_file.h 16;" d IPIN ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type IPIN_COST_INDEX ./base/vpr_types.h /^ IPIN_COST_INDEX,$/;" e enum:e_cost_indices InEventLoop ./base/graphics.c /^static boolean InEventLoop = FALSE;$/;" v file: -InitSpice ../../libarchfpga/read_xml_spice_util.c /^void InitSpice(t_spice* spice) {$/;" f -InitSpiceMeasParams ../../libarchfpga/read_xml_spice_util.c /^void InitSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f -InitSpiceMonteCarloParams ../../libarchfpga/read_xml_spice_util.c /^void InitSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f -InitSpiceParams ../../libarchfpga/read_xml_spice_util.c /^void InitSpiceParams(t_spice_params* params) {$/;" f -InitSpiceStimulateParams ../../libarchfpga/read_xml_spice_util.c /^void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f -InitSpiceVariationParams ../../libarchfpga/read_xml_spice_util.c /^void InitSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f -IsAuto ../../libarchfpga/include/physical_types.h /^ boolean IsAuto;$/;" m struct:s_clb_grid IsEchoEnabled ./base/ReadOptions.c /^boolean IsEchoEnabled(INP t_options *Options) {$/;" f IsPostSynthesisEnabled ./base/ReadOptions.c /^boolean IsPostSynthesisEnabled(INP t_options *Options) {$/;" f IsTimingEnabled ./base/ReadOptions.c /^boolean IsTimingEnabled(INP t_options *Options) {$/;" f -IsWhitespace ../../libarchfpga/read_xml_util.c /^boolean IsWhitespace(char c) {$/;" f KHAKI ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types LAST_CMD_CATEGORY ./fpga_x2p/shell/shell_types.h /^ LAST_CMD_CATEGORY$/;" e enum:e_cmd_category LAST_CMD_NAME ./fpga_x2p/shell/shell_types.h 37;" d LAST_OPT_NAME ./fpga_x2p/shell/read_opt_types.h 57;" d LAST_OPT_TAG ./fpga_x2p/shell/read_opt_types.h 56;" d -LATCH_CLASS ../../libarchfpga/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class LEAVE_CLUSTERED ./pack/cluster.c /^ REMOVE_CLUSTERED, LEAVE_CLUSTERED$/;" e enum:e_removal_policy file: -LEFT ../../libarchfpga/include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side LIGHTBLUE ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types LIGHTGREY ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types LINELENGTH ./pack/output_blif.c 18;" d file: LINELENGTH ./pack/output_clustering.c 16;" d file: -LINKEDLIST_H ../../libarchfpga/fpga_spice_include/linkedlist.h 2;" d -LINK_SIZE ../../pcre/SRC/config.h 56;" d -LOGIC_TYPES_H ../../libarchfpga/include/logic_types.h 10;" d LONGLINE ./route/segment_stats.c 9;" d file: -LUT_CLASS ../../libarchfpga/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class -LUT_transistor_size ../../libarchfpga/include/physical_types.h /^ float LUT_transistor_size;$/;" m struct:s_power_arch L_wire ./fpga_x2p/verilog/verilog_report_timing.c /^ int L_wire;$/;" m struct:s_wireL_cnt file: -LookaheadNodeTokens ../../libarchfpga/read_xml_util.c /^LookaheadNodeTokens(INP ezxml_t Node) {$/;" f MAGENTA ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types -MAGIC_NUMBER ../../pcre/SRC/internal.h 210;" d MAJOR ./base/vpr_types.h 73;" d MARKED_FRAC ./pack/cluster.c 87;" d file: -MATCH_LIMIT ../../pcre/SRC/config.h 68;" d -MATCH_MATCH ../../pcre/SRC/pcre.c 178;" d file: -MATCH_NOMATCH ../../pcre/SRC/pcre.c 179;" d file: -MAXLIT ../../pcre/SRC/pcre.c 83;" d file: MAXPIXEL ./base/graphics.c 202;" d file: MAXPIXEL ./base/graphics.c 225;" d file: MAXPTS ./base/easygl_constants.h 10;" d MAX_ATOM_PARSE ./base/read_blif.c 20;" d file: MAX_BLOCK_COLOURS ./base/draw.c 21;" d file: -MAX_CHANNEL_WIDTH ../../libarchfpga/include/arch_types.h 25;" d MAX_FONT_SIZE ./base/graphics.c 179;" d file: MAX_INV_TIMING_COST ./place/place.c 64;" d file: MAX_LEN ./place/place_stats.c 9;" d file: MAX_LOGS ./power/power.h 33;" d MAX_MOVES_BEFORE_RECOMPUTE ./place/place.c 36;" d file: MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY ./place/place.c 41;" d file: -MAX_PATTERN_SIZE ../../pcre/SRC/internal.h 100;" d -MAX_PATTERN_SIZE ../../pcre/SRC/internal.h 113;" d -MAX_PATTERN_SIZE ../../pcre/SRC/internal.h 127;" d MAX_SHORT ./base/vpr_types.h 75;" d MAX_STRING_LEN ./util/vpr_utils.c 18;" d file: MAX_X ./place/place_stats.c 8;" d file: MEDIUMPURPLE ./base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types -MEMORY_CLASS ../../libarchfpga/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class MINOR ./base/vpr_types.h 72;" d MINPIXEL ./base/graphics.c 203;" d file: MINPIXEL ./base/graphics.c 226;" d file: @@ -521,16 +289,13 @@ MODEL_LOGIC ./base/vpr_types.h 297;" d MODEL_OUTPUT ./base/vpr_types.h 300;" d MOLECULE_FORCED_PACK ./base/vpr_types.h /^ MOLECULE_SINGLE_ATOM, MOLECULE_FORCED_PACK$/;" e enum:e_pack_pattern_molecule_type MOLECULE_SINGLE_ATOM ./base/vpr_types.h /^ MOLECULE_SINGLE_ATOM, MOLECULE_FORCED_PACK$/;" e enum:e_pack_pattern_molecule_type -MONO ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp MRFPGA_H ./mrfpga/mrfpga_globals.h 2;" d MULTI_BUFFERED ./base/vpr_types.h /^ MULTI_BUFFERED, SINGLE$/;" e enum:e_drivers -MUX_INTERC ../../libarchfpga/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect MWIDTH ./base/graphics.c 177;" d file: MainWND ./base/graphics.c /^MainWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: MergeOptions ./base/ReadOptions.c /^static void MergeOptions(INOUTP t_options * dest, INP t_options * src, int id)$/;" f file: NDEBUG ./base/vpr_types.h 63;" d NEGATIVE_EPSILON ./base/vpr_types.h 84;" d -NEM ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp NET_COUNT ./place/timing_place_lookup.c 41;" d file: NET_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 2;" d NET_TIMING_DRIVEN_PLACE ./base/vpr_types.h /^ BOUNDING_BOX_PLACE, NET_TIMING_DRIVEN_PLACE, PATH_TIMING_DRIVEN_PLACE$/;" e enum:e_place_algorithm @@ -538,7 +303,6 @@ NET_USED ./place/timing_place_lookup.c 45;" d file: NET_USED_SINK_BLOCK ./place/timing_place_lookup.c 48;" d file: NET_USED_SOURCE_BLOCK ./place/timing_place_lookup.c 47;" d file: NEVER_CLUSTER ./base/vpr_types.h 99;" d -NEWLINE ../../pcre/SRC/config.h 45;" d NMOS ./power/power.h /^ NMOS, PMOS$/;" e enum:__anon11 NMOS_1X_C_d ./power/power.h /^ float NMOS_1X_C_d;$/;" m struct:s_power_commonly_used NMOS_1X_C_g ./power/power.h /^ float NMOS_1X_C_g;$/;" m struct:s_power_commonly_used @@ -564,14 +328,12 @@ NO_TIMING ./base/vpr_types.h /^ BREADTH_FIRST, TIMING_DRIVEN, NO_TIMING$/;" e en NUM_BUCKETS ./timing/path_delay.c 148;" d file: NUM_COLOR ./base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types NUM_FONT_TYPES ./base/graphics.c 2781;" d file: -NUM_MODELS_IN_LIBRARY ../../libarchfpga/include/read_xml_arch_file.h 14;" d NUM_RR_TYPES ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type NUM_TYPES_USED ./place/timing_place_lookup.c 59;" d file: NetFile ./base/ReadOptions.h /^ char *NetFile;$/;" m struct:s_options NetFile ./base/vpr_types.h /^ char *NetFile;$/;" m struct:s_file_name_opts OFF ./base/graphics.c 1362;" d file: ON ./base/graphics.c 1363;" d file: -OPEN ../../libarchfpga/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type OPEN ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: OPIN ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type OPIN_COST_INDEX ./base/vpr_types.h /^ OPIN_COST_INDEX,$/;" e enum:e_cost_indices @@ -586,86 +348,6 @@ OPT_NONVAL ./fpga_x2p/shell/read_opt_types.h /^ OPT_NONVAL,$/;" e enum:opt_with OPT_OPT ./fpga_x2p/shell/read_opt_types.h /^ OPT_OPT$/;" e enum:opt_manda OPT_REQ ./fpga_x2p/shell/read_opt_types.h /^ OPT_REQ,$/;" e enum:opt_manda OPT_WITHVAL ./fpga_x2p/shell/read_opt_types.h /^ OPT_WITHVAL$/;" e enum:opt_with_val -OP_ALT ../../pcre/SRC/internal.h /^ OP_ALT, \/* 60 Start of alternation *\/$/;" e enum:__anon25 -OP_ANY ../../pcre/SRC/internal.h /^ OP_ANY, \/* 11 Match any character *\/$/;" e enum:__anon25 -OP_ANYBYTE ../../pcre/SRC/internal.h /^ OP_ANYBYTE, \/* 12 Match any byte (\\C); different to OP_ANY for UTF-8 *\/$/;" e enum:__anon25 -OP_ASSERT ../../pcre/SRC/internal.h /^ OP_ASSERT, \/* 64 Positive lookahead *\/$/;" e enum:__anon25 -OP_ASSERTBACK ../../pcre/SRC/internal.h /^ OP_ASSERTBACK, \/* 66 Positive lookbehind *\/$/;" e enum:__anon25 -OP_ASSERTBACK_NOT ../../pcre/SRC/internal.h /^ OP_ASSERTBACK_NOT, \/* 67 Negative lookbehind *\/$/;" e enum:__anon25 -OP_ASSERT_NOT ../../pcre/SRC/internal.h /^ OP_ASSERT_NOT, \/* 65 Negative lookahead *\/$/;" e enum:__anon25 -OP_BRA ../../pcre/SRC/internal.h /^ OP_BRA \/* 75 This and greater values are used for brackets that$/;" e enum:__anon25 -OP_BRAMINZERO ../../pcre/SRC/internal.h /^ OP_BRAMINZERO, \/* 73 order. *\/$/;" e enum:__anon25 -OP_BRANUMBER ../../pcre/SRC/internal.h /^ OP_BRANUMBER, \/* 74 Used for extracting brackets whose number is greater$/;" e enum:__anon25 -OP_BRAZERO ../../pcre/SRC/internal.h /^ OP_BRAZERO, \/* 72 These two must remain together and in this *\/$/;" e enum:__anon25 -OP_CALLOUT ../../pcre/SRC/internal.h /^ OP_CALLOUT, \/* 59 Call out to external function if provided *\/$/;" e enum:__anon25 -OP_CHARS ../../pcre/SRC/internal.h /^ OP_CHARS, \/* 18 Match string of characters *\/$/;" e enum:__anon25 -OP_CIRC ../../pcre/SRC/internal.h /^ OP_CIRC, \/* 16 Start of line - varies with multiline switch *\/$/;" e enum:__anon25 -OP_CLASS ../../pcre/SRC/internal.h /^ OP_CLASS, \/* 55 Match a character class, chars < 256 only *\/$/;" e enum:__anon25 -OP_COND ../../pcre/SRC/internal.h /^ OP_COND, \/* 70 Conditional group *\/$/;" e enum:__anon25 -OP_CREF ../../pcre/SRC/internal.h /^ OP_CREF, \/* 71 Used to hold an extraction string number (cond ref) *\/$/;" e enum:__anon25 -OP_CRMINPLUS ../../pcre/SRC/internal.h /^ OP_CRMINPLUS, \/* 50 be in exactly the same order as those above. *\/$/;" e enum:__anon25 -OP_CRMINQUERY ../../pcre/SRC/internal.h /^ OP_CRMINQUERY, \/* 52 *\/$/;" e enum:__anon25 -OP_CRMINRANGE ../../pcre/SRC/internal.h /^ OP_CRMINRANGE, \/* 54 *\/$/;" e enum:__anon25 -OP_CRMINSTAR ../../pcre/SRC/internal.h /^ OP_CRMINSTAR, \/* 48 all these opcodes must come in pairs, with *\/$/;" e enum:__anon25 -OP_CRPLUS ../../pcre/SRC/internal.h /^ OP_CRPLUS, \/* 49 the minimizing one second. These codes must *\/$/;" e enum:__anon25 -OP_CRQUERY ../../pcre/SRC/internal.h /^ OP_CRQUERY, \/* 51 These are for character classes and back refs *\/$/;" e enum:__anon25 -OP_CRRANGE ../../pcre/SRC/internal.h /^ OP_CRRANGE, \/* 53 These are different to the three seta above. *\/$/;" e enum:__anon25 -OP_CRSTAR ../../pcre/SRC/internal.h /^ OP_CRSTAR, \/* 47 The maximizing and minimizing versions of *\/$/;" e enum:__anon25 -OP_DIGIT ../../pcre/SRC/internal.h /^ OP_DIGIT, \/* 6 \\d *\/$/;" e enum:__anon25 -OP_DOLL ../../pcre/SRC/internal.h /^ OP_DOLL, \/* 17 End of line - varies with multiline switch *\/$/;" e enum:__anon25 -OP_END ../../pcre/SRC/internal.h /^ OP_END, \/* 0 End of pattern *\/$/;" e enum:__anon25 -OP_EOD ../../pcre/SRC/internal.h /^ OP_EOD, \/* 14 End of data: \\z *\/$/;" e enum:__anon25 -OP_EODN ../../pcre/SRC/internal.h /^ OP_EODN, \/* 13 End of data or \\n at end of data: \\Z. *\/$/;" e enum:__anon25 -OP_EXACT ../../pcre/SRC/internal.h /^ OP_EXACT, \/* 28 Exactly n matches *\/$/;" e enum:__anon25 -OP_KET ../../pcre/SRC/internal.h /^ OP_KET, \/* 61 End of group that doesn't have an unbounded repeat *\/$/;" e enum:__anon25 -OP_KETRMAX ../../pcre/SRC/internal.h /^ OP_KETRMAX, \/* 62 These two must remain together and in this *\/$/;" e enum:__anon25 -OP_KETRMIN ../../pcre/SRC/internal.h /^ OP_KETRMIN, \/* 63 order. They are for groups the repeat for ever. *\/$/;" e enum:__anon25 -OP_LENGTHS ../../pcre/SRC/internal.h 425;" d -OP_MINPLUS ../../pcre/SRC/internal.h /^ OP_MINPLUS, \/* 23 This first set applies to single characters *\/$/;" e enum:__anon25 -OP_MINQUERY ../../pcre/SRC/internal.h /^ OP_MINQUERY, \/* 25 *\/$/;" e enum:__anon25 -OP_MINSTAR ../../pcre/SRC/internal.h /^ OP_MINSTAR, \/* 21 all these opcodes must come in pairs, with *\/$/;" e enum:__anon25 -OP_MINUPTO ../../pcre/SRC/internal.h /^ OP_MINUPTO, \/* 27 *\/$/;" e enum:__anon25 -OP_NAME_LIST ../../pcre/SRC/internal.h 402;" d -OP_NCLASS ../../pcre/SRC/internal.h /^ OP_NCLASS, \/* 56 Same, but the bitmap was created from a negative$/;" e enum:__anon25 -OP_NOT ../../pcre/SRC/internal.h /^ OP_NOT, \/* 19 Match anything but the following char *\/$/;" e enum:__anon25 -OP_NOTEXACT ../../pcre/SRC/internal.h /^ OP_NOTEXACT, \/* 37 Exactly n matches *\/$/;" e enum:__anon25 -OP_NOTMINPLUS ../../pcre/SRC/internal.h /^ OP_NOTMINPLUS, \/* 32 This set applies to "not" single characters *\/$/;" e enum:__anon25 -OP_NOTMINQUERY ../../pcre/SRC/internal.h /^ OP_NOTMINQUERY, \/* 34 *\/$/;" e enum:__anon25 -OP_NOTMINSTAR ../../pcre/SRC/internal.h /^ OP_NOTMINSTAR, \/* 30 all these opcodes must come in pairs, with *\/$/;" e enum:__anon25 -OP_NOTMINUPTO ../../pcre/SRC/internal.h /^ OP_NOTMINUPTO, \/* 36 *\/$/;" e enum:__anon25 -OP_NOTPLUS ../../pcre/SRC/internal.h /^ OP_NOTPLUS, \/* 31 the minimizing one second. *\/$/;" e enum:__anon25 -OP_NOTQUERY ../../pcre/SRC/internal.h /^ OP_NOTQUERY, \/* 33 *\/$/;" e enum:__anon25 -OP_NOTSTAR ../../pcre/SRC/internal.h /^ OP_NOTSTAR, \/* 29 The maximizing and minimizing versions of *\/$/;" e enum:__anon25 -OP_NOTUPTO ../../pcre/SRC/internal.h /^ OP_NOTUPTO, \/* 35 From 0 to n matches *\/$/;" e enum:__anon25 -OP_NOT_DIGIT ../../pcre/SRC/internal.h /^ OP_NOT_DIGIT, \/* 5 \\D *\/$/;" e enum:__anon25 -OP_NOT_WHITESPACE ../../pcre/SRC/internal.h /^ OP_NOT_WHITESPACE, \/* 7 \\S *\/$/;" e enum:__anon25 -OP_NOT_WORDCHAR ../../pcre/SRC/internal.h /^ OP_NOT_WORDCHAR, \/* 9 \\W *\/$/;" e enum:__anon25 -OP_NOT_WORD_BOUNDARY ../../pcre/SRC/internal.h /^ OP_NOT_WORD_BOUNDARY, \/* 3 \\B *\/$/;" e enum:__anon25 -OP_ONCE ../../pcre/SRC/internal.h /^ OP_ONCE, \/* 69 Once matched, don't back up into the subpattern *\/$/;" e enum:__anon25 -OP_OPT ../../pcre/SRC/internal.h /^ OP_OPT, \/* 15 Set runtime options *\/$/;" e enum:__anon25 -OP_PLUS ../../pcre/SRC/internal.h /^ OP_PLUS, \/* 22 the minimizing one second. *\/$/;" e enum:__anon25 -OP_QUERY ../../pcre/SRC/internal.h /^ OP_QUERY, \/* 24 *\/$/;" e enum:__anon25 -OP_RECURSE ../../pcre/SRC/internal.h /^ OP_RECURSE, \/* 58 Match a numbered subpattern (possibly recursive) *\/$/;" e enum:__anon25 -OP_REF ../../pcre/SRC/internal.h /^ OP_REF, \/* 57 Match a back reference *\/$/;" e enum:__anon25 -OP_REVERSE ../../pcre/SRC/internal.h /^ OP_REVERSE, \/* 68 Move pointer back - used in lookbehind assertions *\/$/;" e enum:__anon25 -OP_SOD ../../pcre/SRC/internal.h /^ OP_SOD, \/* 1 Start of data: \\A *\/$/;" e enum:__anon25 -OP_SOM ../../pcre/SRC/internal.h /^ OP_SOM, \/* 2 Start of match (subject + offset): \\G *\/$/;" e enum:__anon25 -OP_STAR ../../pcre/SRC/internal.h /^ OP_STAR, \/* 20 The maximizing and minimizing versions of *\/$/;" e enum:__anon25 -OP_TYPEEXACT ../../pcre/SRC/internal.h /^ OP_TYPEEXACT, \/* 46 Exactly n matches *\/$/;" e enum:__anon25 -OP_TYPEMINPLUS ../../pcre/SRC/internal.h /^ OP_TYPEMINPLUS, \/* 41 be in exactly the same order as those above. *\/$/;" e enum:__anon25 -OP_TYPEMINQUERY ../../pcre/SRC/internal.h /^ OP_TYPEMINQUERY, \/* 43 *\/$/;" e enum:__anon25 -OP_TYPEMINSTAR ../../pcre/SRC/internal.h /^ OP_TYPEMINSTAR, \/* 39 all these opcodes must come in pairs, with *\/$/;" e enum:__anon25 -OP_TYPEMINUPTO ../../pcre/SRC/internal.h /^ OP_TYPEMINUPTO, \/* 45 *\/$/;" e enum:__anon25 -OP_TYPEPLUS ../../pcre/SRC/internal.h /^ OP_TYPEPLUS, \/* 40 the minimizing one second. These codes must *\/$/;" e enum:__anon25 -OP_TYPEQUERY ../../pcre/SRC/internal.h /^ OP_TYPEQUERY, \/* 42 This set applies to character types such as \\d *\/$/;" e enum:__anon25 -OP_TYPESTAR ../../pcre/SRC/internal.h /^ OP_TYPESTAR, \/* 38 The maximizing and minimizing versions of *\/$/;" e enum:__anon25 -OP_TYPEUPTO ../../pcre/SRC/internal.h /^ OP_TYPEUPTO, \/* 44 From 0 to n matches *\/$/;" e enum:__anon25 -OP_UPTO ../../pcre/SRC/internal.h /^ OP_UPTO, \/* 26 From 0 to n matches *\/$/;" e enum:__anon25 -OP_WHITESPACE ../../pcre/SRC/internal.h /^ OP_WHITESPACE, \/* 8 \\s *\/$/;" e enum:__anon25 -OP_WORDCHAR ../../pcre/SRC/internal.h /^ OP_WORDCHAR, \/* 10 \\w *\/$/;" e enum:__anon25 -OP_WORD_BOUNDARY ../../pcre/SRC/internal.h /^ OP_WORD_BOUNDARY, \/* 4 \\b *\/$/;" e enum:__anon25 -OP_XCLASS ../../pcre/SRC/internal.h /^ OP_XCLASS, \/* 56 Extended class for handling UTF-8 chars within the$/;" e enum:__anon25 -OP_lengths ../../pcre/SRC/pcre.c /^static uschar OP_lengths[] = { OP_LENGTHS };$/;" v file: OT_ACC_FAC ./base/OptionTokens.h /^ OT_ACC_FAC,$/;" e enum:e_OptionBaseToken OT_ACTIVITY_FILE ./base/OptionTokens.h /^ OT_ACTIVITY_FILE,$/;" e enum:e_OptionBaseToken OT_ALLOW_EARLY_EXIT ./base/OptionTokens.h /^ OT_ALLOW_EARLY_EXIT,$/;" e enum:e_OptionBaseToken @@ -733,6 +415,7 @@ OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SY OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH, \/* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist *\/$/;" e enum:e_OptionBaseToken OT_FPGA_VERILOG_SYN_PRINT_USER_DEFINED_TEMPLATE ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_PRINT_USER_DEFINED_TEMPLATE,$/;" e enum:e_OptionBaseToken OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH,$/;" e enum:e_OptionBaseToken +OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY ./base/OptionTokens.h /^ OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY, \/* use a compact routing hierarchy in SPICE\/Verilog generation *\/$/;" e enum:e_OptionBaseToken OT_FPGA_X2P_RENAME_ILLEGAL_PORT ./base/OptionTokens.h /^ OT_FPGA_X2P_RENAME_ILLEGAL_PORT, $/;" e enum:e_OptionBaseToken OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT ./base/OptionTokens.h /^ OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT, \/* The weight of signal density in determining number of clock cycles in simulation *\/$/;" e enum:e_OptionBaseToken OT_FPGA_X2P_SIM_WINDOW_SIZE ./base/OptionTokens.h /^ OT_FPGA_X2P_SIM_WINDOW_SIZE, \/* Window size in determining number of clock cycles in simulation *\/$/;" e enum:e_OptionBaseToken @@ -798,11 +481,7 @@ OT_TIMING_DRIVEN ./base/OptionTokens.h /^ OT_TIMING_DRIVEN,$/;" e enum:e_OptionA OT_TIMING_DRIVEN_CLUSTERING ./base/OptionTokens.h /^ OT_TIMING_DRIVEN_CLUSTERING,$/;" e enum:e_OptionBaseToken OT_TIMING_TRADEOFF ./base/OptionTokens.h /^ OT_TIMING_TRADEOFF,$/;" e enum:e_OptionBaseToken OT_VERIFY_BINARY_SEARCH ./base/OptionTokens.h /^ OT_VERIFY_BINARY_SEARCH,$/;" e enum:e_OptionBaseToken -OUTP ../../libarchfpga/include/util.h 20;" d OUTPUT ./pack/cluster.c /^ INPUT, OUTPUT$/;" e enum:e_net_relation_to_clustered_block file: -OUTPUT2OUTPUT_INTERC ../../libarchfpga/fpga_spice_include/spice_types.h /^ OUTPUT2OUTPUT_INTERC$/;" e enum:e_spice_pin2pin_interc_type -OUT_PORT ../../libarchfpga/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -OVECCOUNT ../../pcre/SRC/main.c 23;" d file: Operation ./base/vpr_types.h /^ enum e_operation Operation; \/* run VPR or do analysis only *\/$/;" m struct:s_vpr_setup typeref:enum:s_vpr_setup::e_operation OptionArgTokenList ./base/OptionTokens.c /^struct s_TokenPair OptionArgTokenList[] = { { "on", OT_ON }, { "off", OT_OFF },$/;" v typeref:struct:s_TokenPair OptionBaseTokenList ./base/OptionTokens.c /^struct s_TokenPair OptionBaseTokenList[] = {$/;" v typeref:struct:s_TokenPair @@ -813,73 +492,9 @@ PACK_PATH_WEIGHT ./timing/path_delay.h 34;" d PALCE_MACRO_H ./place/place_macro.h 136;" d PATH_DELAY ./timing/path_delay.h 2;" d PATH_TIMING_DRIVEN_PLACE ./base/vpr_types.h /^ BOUNDING_BOX_PLACE, NET_TIMING_DRIVEN_PLACE, PATH_TIMING_DRIVEN_PLACE$/;" e enum:e_place_algorithm -PB_PIN_CLOCK ../../libarchfpga/include/physical_types.h /^ PB_PIN_CLOCK$/;" e enum:e_pb_graph_pin_type PB_PIN_EQ_AUTO_DETECT_H ./route/pb_pin_eq_auto_detect.h 3;" d -PB_PIN_INPAD ../../libarchfpga/include/physical_types.h /^ PB_PIN_INPAD,$/;" e enum:e_pb_graph_pin_type -PB_PIN_NORMAL ../../libarchfpga/include/physical_types.h /^ PB_PIN_NORMAL = 0,$/;" e enum:e_pb_graph_pin_type -PB_PIN_OUTPAD ../../libarchfpga/include/physical_types.h /^ PB_PIN_OUTPAD,$/;" e enum:e_pb_graph_pin_type -PB_PIN_SEQUENTIAL ../../libarchfpga/include/physical_types.h /^ PB_PIN_SEQUENTIAL,$/;" e enum:e_pb_graph_pin_type -PB_PIN_TERMINAL ../../libarchfpga/include/physical_types.h /^ PB_PIN_TERMINAL,$/;" e enum:e_pb_graph_pin_type PB_TYPE_GRAPH_ANNOTATIONS_H ./pack/pb_type_graph_annotations.h 8;" d PB_TYPE_GRAPH_H ./pack/pb_type_graph.h 2;" d -PCRAM_Pierre ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -PCRAM_Xie ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -PCRE_ANCHORED ../../pcre/SRC/pcre.h 51;" d -PCRE_CASELESS ../../pcre/SRC/pcre.h 47;" d -PCRE_CONFIG_LINK_SIZE ../../pcre/SRC/pcre.h 92;" d -PCRE_CONFIG_MATCH_LIMIT ../../pcre/SRC/pcre.h 94;" d -PCRE_CONFIG_NEWLINE ../../pcre/SRC/pcre.h 91;" d -PCRE_CONFIG_POSIX_MALLOC_THRESHOLD ../../pcre/SRC/pcre.h 93;" d -PCRE_CONFIG_UTF8 ../../pcre/SRC/pcre.h 90;" d -PCRE_DATA_SCOPE ../../pcre/SRC/pcre.h 22;" d -PCRE_DATA_SCOPE ../../pcre/SRC/pcre.h 26;" d -PCRE_DATA_SCOPE ../../pcre/SRC/pcre.h 31;" d -PCRE_DATE ../../pcre/SRC/pcre.h 15;" d -PCRE_DEFINITION ../../pcre/SRC/internal.h 164;" d -PCRE_DOLLAR_ENDONLY ../../pcre/SRC/pcre.h 52;" d -PCRE_DOTALL ../../pcre/SRC/pcre.h 49;" d -PCRE_ERROR_BADMAGIC ../../pcre/SRC/pcre.h 66;" d -PCRE_ERROR_BADOPTION ../../pcre/SRC/pcre.h 65;" d -PCRE_ERROR_CALLOUT ../../pcre/SRC/pcre.h 71;" d -PCRE_ERROR_MATCHLIMIT ../../pcre/SRC/pcre.h 70;" d -PCRE_ERROR_NOMATCH ../../pcre/SRC/pcre.h 63;" d -PCRE_ERROR_NOMEMORY ../../pcre/SRC/pcre.h 68;" d -PCRE_ERROR_NOSUBSTRING ../../pcre/SRC/pcre.h 69;" d -PCRE_ERROR_NULL ../../pcre/SRC/pcre.h 64;" d -PCRE_ERROR_UNKNOWN_NODE ../../pcre/SRC/pcre.h 67;" d -PCRE_EXTENDED ../../pcre/SRC/pcre.h 50;" d -PCRE_EXTRA ../../pcre/SRC/pcre.h 53;" d -PCRE_EXTRA_CALLOUT_DATA ../../pcre/SRC/pcre.h 100;" d -PCRE_EXTRA_MATCH_LIMIT ../../pcre/SRC/pcre.h 99;" d -PCRE_EXTRA_STUDY_DATA ../../pcre/SRC/pcre.h 98;" d -PCRE_FIRSTSET ../../pcre/SRC/internal.h 186;" d -PCRE_ICHANGED ../../pcre/SRC/internal.h 189;" d -PCRE_IMS ../../pcre/SRC/internal.h 178;" d -PCRE_INFO_BACKREFMAX ../../pcre/SRC/pcre.h 78;" d -PCRE_INFO_CAPTURECOUNT ../../pcre/SRC/pcre.h 77;" d -PCRE_INFO_FIRSTBYTE ../../pcre/SRC/pcre.h 79;" d -PCRE_INFO_FIRSTCHAR ../../pcre/SRC/pcre.h 80;" d -PCRE_INFO_FIRSTTABLE ../../pcre/SRC/pcre.h 81;" d -PCRE_INFO_LASTLITERAL ../../pcre/SRC/pcre.h 82;" d -PCRE_INFO_NAMECOUNT ../../pcre/SRC/pcre.h 84;" d -PCRE_INFO_NAMEENTRYSIZE ../../pcre/SRC/pcre.h 83;" d -PCRE_INFO_NAMETABLE ../../pcre/SRC/pcre.h 85;" d -PCRE_INFO_OPTIONS ../../pcre/SRC/pcre.h 75;" d -PCRE_INFO_SIZE ../../pcre/SRC/pcre.h 76;" d -PCRE_INFO_STUDYSIZE ../../pcre/SRC/pcre.h 86;" d -PCRE_MAJOR ../../pcre/SRC/pcre.h 13;" d -PCRE_MINOR ../../pcre/SRC/pcre.h 14;" d -PCRE_MULTILINE ../../pcre/SRC/pcre.h 48;" d -PCRE_NOTBOL ../../pcre/SRC/pcre.h 54;" d -PCRE_NOTEMPTY ../../pcre/SRC/pcre.h 57;" d -PCRE_NOTEOL ../../pcre/SRC/pcre.h 55;" d -PCRE_NO_AUTO_CAPTURE ../../pcre/SRC/pcre.h 59;" d -PCRE_REQCHSET ../../pcre/SRC/internal.h 187;" d -PCRE_STARTLINE ../../pcre/SRC/internal.h 188;" d -PCRE_STUDY_MAPPED ../../pcre/SRC/internal.h 193;" d -PCRE_UNGREEDY ../../pcre/SRC/pcre.h 56;" d -PCRE_UTF8 ../../pcre/SRC/pcre.h 58;" d -PHYSICAL_TYPES_H ../../libarchfpga/include/physical_types.h 27;" d PI ./base/graphics.c 181;" d file: PLACEMENT ./base/vpr_types.h /^ NO_PICTURE, PLACEMENT, ROUTING$/;" e enum:pic_type PLACE_ALWAYS ./base/vpr_types.h /^ PLACE_NEVER, PLACE_ONCE, PLACE_ALWAYS$/;" e enum:pfreq @@ -899,8 +514,6 @@ PMOS_1X_st_leakage ./power/power.h /^ float PMOS_1X_st_leakage;$/;" m struct:s_p PMOS_2X_st_leakage ./power/power.h /^ float PMOS_2X_st_leakage;$/;" m struct:s_power_commonly_used PMOS_inf ./power/power.h /^ t_transistor_inf PMOS_inf;$/;" m struct:s_power_tech PN_ratio ./power/power.h /^ float PN_ratio; \/* Ratio of PMOS to NMOS in inverter *\/$/;" m struct:s_power_tech -PORTS ../../libarchfpga/include/logic_types.h /^enum PORTS {$/;" g -POSIX_MALLOC_THRESHOLD ../../pcre/SRC/internal.h 661;" d POSTSCRIPT ./base/graphics.c /^ POSTSCRIPT = 1$/;" e enum:__anon2 file: POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES$/;" e enum:__anon8 file: POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT,$/;" e enum:__anon8 file: @@ -908,10 +521,6 @@ POWER_BREAKDOWN_ENTRY_TYPE_INTERC ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_ POWER_BREAKDOWN_ENTRY_TYPE_MODE ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_MODE,$/;" e enum:__anon8 file: POWER_BREAKDOWN_ENTRY_TYPE_PB ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_PB,$/;" e enum:__anon8 file: POWER_BREAKDOWN_ENTRY_TYPE_TITLE ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_TITLE = 0,$/;" e enum:__anon8 file: -POWER_BUFFER_TYPE_ABSOLUTE_SIZE ../../libarchfpga/include/physical_types.h /^ POWER_BUFFER_TYPE_ABSOLUTE_SIZE$/;" e enum:__anon21 -POWER_BUFFER_TYPE_AUTO ../../libarchfpga/include/physical_types.h /^ POWER_BUFFER_TYPE_AUTO,$/;" e enum:__anon21 -POWER_BUFFER_TYPE_NONE ../../libarchfpga/include/physical_types.h /^ POWER_BUFFER_TYPE_NONE,$/;" e enum:__anon21 -POWER_BUFFER_TYPE_UNDEFINED ../../libarchfpga/include/physical_types.h /^ POWER_BUFFER_TYPE_UNDEFINED = 0,$/;" e enum:__anon21 POWER_CALLIB_COMPONENT_BUFFER ./power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_BUFFER = 0,$/;" e enum:__anon12 POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR ./power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR,$/;" e enum:__anon12 POWER_CALLIB_COMPONENT_FF ./power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_FF,$/;" e enum:__anon12 @@ -944,39 +553,15 @@ POWER_LOG_NUM_TYPES ./power/power.h /^ POWER_LOG_ERROR, POWER_LOG_WARNING, POWER POWER_LOG_WARNING ./power/power.h /^ POWER_LOG_ERROR, POWER_LOG_WARNING, POWER_LOG_NUM_TYPES$/;" e enum:__anon10 POWER_LUT_SLOW ./power/power_components.h 37;" d POWER_LUT_SLOW ./power/power_components.h 39;" d -POWER_METHOD_ABSOLUTE ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_ABSOLUTE \/* Dynamic: Aboslute, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_AUTO_SIZES ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_AUTO_SIZES, \/* Transistor-level, auto-sized buffers\/wires *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_C_INTERNAL ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_C_INTERNAL, \/* Dynamic: Equiv. Internal capacitance, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_IGNORE ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_SPECIFY_SIZES ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_SPECIFY_SIZES, \/* Transistor-level, user-specified buffers\/wires *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_SUM_OF_CHILDREN ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_SUM_OF_CHILDREN, \/* Ignore power of this PB, but consider children *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_TOGGLE_PINS ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_TOGGLE_PINS, \/* Dynamic: Energy per pin toggle, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_UNDEFINED ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ POWER_MTA_L ./power/power_sizing.h 39;" d POWER_MTA_W ./power/power_sizing.h 38;" d POWER_RET_CODE_ERRORS ./power/power.h /^ POWER_RET_CODE_SUCCESS = 0, POWER_RET_CODE_ERRORS, POWER_RET_CODE_WARNINGS$/;" e enum:__anon9 POWER_RET_CODE_SUCCESS ./power/power.h /^ POWER_RET_CODE_SUCCESS = 0, POWER_RET_CODE_ERRORS, POWER_RET_CODE_WARNINGS$/;" e enum:__anon9 POWER_RET_CODE_WARNINGS ./power/power.h /^ POWER_RET_CODE_SUCCESS = 0, POWER_RET_CODE_ERRORS, POWER_RET_CODE_WARNINGS$/;" e enum:__anon9 -POWER_WIRE_TYPE_ABSOLUTE_LENGTH ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_ABSOLUTE_LENGTH,$/;" e enum:__anon20 -POWER_WIRE_TYPE_AUTO ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_AUTO$/;" e enum:__anon20 -POWER_WIRE_TYPE_C ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_C,$/;" e enum:__anon20 -POWER_WIRE_TYPE_IGNORED ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_IGNORED,$/;" e enum:__anon20 -POWER_WIRE_TYPE_RELATIVE_LENGTH ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_RELATIVE_LENGTH,$/;" e enum:__anon20 -POWER_WIRE_TYPE_UNDEFINED ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_UNDEFINED = 0,$/;" e enum:__anon20 PREPACK_H ./pack/prepack.h 8;" d PROC_TIME ./base/place_and_route.h 6;" d PRODUCTION_CMD ./fpga_x2p/shell/shell_types.h /^ PRODUCTION_CMD,$/;" e enum:e_cmd_category PTRANS_FLAG ./route/check_rr_graph.c 15;" d file: -PUBLIC_EXEC_OPTIONS ../../pcre/SRC/internal.h 203;" d -PUBLIC_OPTIONS ../../pcre/SRC/internal.h 198;" d -PUBLIC_STUDY_OPTIONS ../../pcre/SRC/internal.h 206;" d -PULSE ../../libarchfpga/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat -PUT ../../pcre/SRC/internal.h 105;" d -PUT ../../pcre/SRC/internal.h 118;" d -PUT ../../pcre/SRC/internal.h 93;" d -PUT2 ../../pcre/SRC/internal.h 144;" d -PUT2INC ../../pcre/SRC/internal.h 151;" d -PUTINC ../../pcre/SRC/internal.h 137;" d PackerOpts ./base/vpr_types.h /^ struct s_packer_opts PackerOpts; \/* Options for packer *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_packer_opts PinFile ./base/ReadOptions.h /^ char *PinFile;$/;" m struct:s_options PlaceAlgorithm ./base/ReadOptions.h /^ enum e_place_algorithm PlaceAlgorithm;$/;" m struct:s_options typeref:enum:s_options::e_place_algorithm @@ -998,93 +583,24 @@ PowerFile ./base/vpr_types.h /^ char *PowerFile;$/;" m struct:s_file_name_opts PowerOpts ./base/vpr_types.h /^ t_power_opts PowerOpts;$/;" m struct:s_vpr_setup PowerSpicedComponent ./power/PowerSpicedComponent.c /^PowerSpicedComponent::PowerSpicedComponent($/;" f class:PowerSpicedComponent PowerSpicedComponent ./power/PowerSpicedComponent.h /^class PowerSpicedComponent {$/;" c -PrintPb_types_rec ../../libarchfpga/read_xml_arch_file.c /^static void PrintPb_types_rec(INP FILE * Echo, INP const t_pb_type * pb_type,$/;" f file: ProceedPressed ./base/graphics.c /^static int ProceedPressed;$/;" v file: -ProcessCB_SB ../../libarchfpga/read_xml_arch_file.c /^static void ProcessCB_SB(INOUTP ezxml_t Node, INOUTP boolean * list,$/;" f file: -ProcessChanWidthDistr ../../libarchfpga/read_xml_arch_file.c /^static void ProcessChanWidthDistr(INOUTP ezxml_t Node,$/;" f file: -ProcessChanWidthDistrDir ../../libarchfpga/read_xml_arch_file.c /^static void ProcessChanWidthDistrDir(INOUTP ezxml_t Node, OUTP t_chan * chan) {$/;" f file: -ProcessClocks ../../libarchfpga/read_xml_arch_file.c /^static void ProcessClocks(ezxml_t Parent, t_clock_arch * clocks) {$/;" f file: -ProcessComplexBlockProps ../../libarchfpga/read_xml_arch_file.c /^static void ProcessComplexBlockProps(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: -ProcessComplexBlocks ../../libarchfpga/read_xml_arch_file.c /^static void ProcessComplexBlocks(INOUTP ezxml_t Node,$/;" f file: -ProcessDevice ../../libarchfpga/read_xml_arch_file.c /^static void ProcessDevice(INOUTP ezxml_t Node, OUTP struct s_arch *arch,$/;" f file: -ProcessDirects ../../libarchfpga/read_xml_arch_file.c /^static void ProcessDirects(INOUTP ezxml_t Parent, OUTP t_direct_inf **Directs,$/;" f file: -ProcessInterconnect ../../libarchfpga/read_xml_arch_file.c /^static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {$/;" f file: -ProcessLayout ../../libarchfpga/read_xml_arch_file.c /^static void ProcessLayout(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: -ProcessLutClass ../../libarchfpga/read_xml_arch_file.c /^void ProcessLutClass(INOUTP t_pb_type *lut_pb_type) {$/;" f -ProcessMemoryClass ../../libarchfpga/read_xml_arch_file.c /^static void ProcessMemoryClass(INOUTP t_pb_type *mem_pb_type) {$/;" f file: -ProcessMode ../../libarchfpga/read_xml_arch_file.c /^static void ProcessMode(INOUTP ezxml_t Parent, t_mode * mode,$/;" f file: -ProcessModels ../../libarchfpga/read_xml_arch_file.c /^static void ProcessModels(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: -ProcessMrFPGATiming ../../libarchfpga/read_xml_mrfpga.c /^void ProcessMrFPGATiming(INOUTP ezxml_t Cur, $/;" f ProcessOption ./base/ReadOptions.c /^ProcessOption(INP char **Args, INOUTP t_options * Options) {$/;" f file: -ProcessPb_Type ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_Type(INOUTP ezxml_t Parent, t_pb_type * pb_type,$/;" f file: -ProcessPb_TypePort ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_TypePort(INOUTP ezxml_t Parent, t_port * port,$/;" f file: -ProcessPb_TypePort_Power ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_TypePort_Power(ezxml_t Parent, t_port * port,$/;" f file: -ProcessPb_TypePower ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_TypePower(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: -ProcessPb_TypePowerEstMethod ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_TypePowerEstMethod(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: -ProcessPb_TypePowerPinToggle ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_TypePowerPinToggle(ezxml_t parent, t_pb_type * pb_type) {$/;" f file: -ProcessPinToPinAnnotations ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPinToPinAnnotations(ezxml_t Parent,$/;" f file: -ProcessPower ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPower( INOUTP ezxml_t parent,$/;" f file: -ProcessSegments ../../libarchfpga/read_xml_arch_file.c /^static void ProcessSegments(INOUTP ezxml_t Parent,$/;" f file: -ProcessSpiceMCVariationParams ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceMCVariationParams(ezxml_t Parent,$/;" f file: -ProcessSpiceMeasParams ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceMeasParams(ezxml_t Parent,$/;" f file: -ProcessSpiceModel ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModel(ezxml_t Parent,$/;" f file: -ProcessSpiceModelBuffer ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelBuffer(ezxml_t Node,$/;" f file: -ProcessSpiceModelDelayInfo ../../libarchfpga/read_xml_spice.c /^void ProcessSpiceModelDelayInfo(ezxml_t Node, $/;" f file: -ProcessSpiceModelGate ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelGate(ezxml_t Node, $/;" f file: -ProcessSpiceModelLUT ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelLUT(ezxml_t Node, $/;" f file: -ProcessSpiceModelMUX ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelMUX(ezxml_t Node, $/;" f file: -ProcessSpiceModelPassGateLogic ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelPassGateLogic(ezxml_t Node,$/;" f file: -ProcessSpiceModelPort ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelPort(ezxml_t Node,$/;" f file: -ProcessSpiceModelPortLutOutputMask ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelPortLutOutputMask(ezxml_t Node,$/;" f file: -ProcessSpiceModelRRAM ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelRRAM(ezxml_t Node, $/;" f file: -ProcessSpiceModelWireParam ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelWireParam(ezxml_t Parent,$/;" f file: -ProcessSpiceMonteCarloParams ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceMonteCarloParams(ezxml_t Parent, $/;" f file: -ProcessSpiceParams ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceParams(ezxml_t Parent,$/;" f file: -ProcessSpiceSRAM ../../libarchfpga/read_xml_spice.c /^void ProcessSpiceSRAM(INOUTP ezxml_t Node, OUTP struct s_arch* arch) {$/;" f -ProcessSpiceSRAMOrganization ../../libarchfpga/read_xml_spice.c /^void ProcessSpiceSRAMOrganization(INOUTP ezxml_t Node, $/;" f file: -ProcessSpiceSettings ../../libarchfpga/read_xml_spice.c /^void ProcessSpiceSettings(ezxml_t Parent,$/;" f -ProcessSpiceStimulateParams ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceStimulateParams(ezxml_t Parent,$/;" f file: -ProcessSpiceStimulateParamsRiseFall ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceStimulateParamsRiseFall(ezxml_t Parent,$/;" f file: -ProcessSpiceTechLibTransistors ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceTechLibTransistors(ezxml_t Parent,$/;" f file: -ProcessSpiceTransistorType ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceTransistorType(ezxml_t Parent,$/;" f file: -ProcessSwitchSegmentPatterns ../../libarchfpga/read_xml_arch_file.c /^static void ProcessSwitchSegmentPatterns(INOUTP ezxml_t Parent,$/;" f file: -ProcessSwitches ../../libarchfpga/read_xml_arch_file.c /^static void ProcessSwitches(INOUTP ezxml_t Parent,$/;" f file: -ProcessTechComp ../../libarchfpga/read_xml_mrfpga.c /^ProcessTechComp(INOUTP ezxml_t Node,$/;" f -ProcessTechHack ../../libarchfpga/read_xml_mrfpga.c /^ProcessTechHack(INOUTP ezxml_t Node,$/;" f -ProcessTechnology ../../libarchfpga/read_xml_mrfpga.c /^ProcessTechnology(INOUTP ezxml_t Node,$/;" f -ProcessWireBuffer ../../libarchfpga/read_xml_mrfpga.c /^ProcessWireBuffer(INOUTP ezxml_t Node,$/;" f -Process_Fc ../../libarchfpga/read_xml_arch_file.c /^static void Process_Fc(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: -ProcessmrFPGA ../../libarchfpga/read_xml_mrfpga.c /^ProcessmrFPGA(INOUTP ezxml_t Node,$/;" f Provenance ./base/ReadOptions.h /^ int Provenance[OT_BASE_UNKNOWN];$/;" m struct:s_options QUEST ./timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: -R ../../libarchfpga/include/arch_types_mrfpga.h /^ float R; $/;" m struct:s_memristor_inf -R ../../libarchfpga/include/arch_types_mrfpga.h /^ float R;$/;" m struct:s_buffer_inf -R ../../libarchfpga/include/physical_types.h /^ float R;$/;" m struct:s_switch_inf R ./base/vpr_types.h /^ float R;$/;" m struct:s_rr_node RANDOM ./base/vpr_types.h /^ FREE, RANDOM, USER$/;" e enum:e_pad_loc_type -READLINE_H ../../libarchfpga/include/ReadLine.h 2;" d READOPTIONS_H ./base/ReadOptions.h 2;" d READ_BLIF_H ./base/read_blif.h 2;" d READ_NETLIST_H ./base/read_netlist.h 9;" d READ_PLACE_H ./base/read_place.h 2;" d READ_SDC_H ./timing/read_sdc.h 2;" d READ_SETTINGS_H ./base/read_settings.h 2;" d -READ_XML_ARCH_FILE_H ../../libarchfpga/include/read_xml_arch_file.h 2;" d -READ_XML_UTIL_H ../../libarchfpga/include/read_xml_util.h 2;" d -RECEIVER ../../libarchfpga/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type -REC_STACK_SAVE_MAX ../../pcre/SRC/pcre.c 75;" d file: RED ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types REJECTED ./place/place.c /^ REJECTED, ACCEPTED, ABORTED$/;" e enum:swap_result file: REMOVE_CLUSTERED ./pack/cluster.c /^ REMOVE_CLUSTERED, LEAVE_CLUSTERED$/;" e enum:e_removal_policy file: -REQ_BYTE_MAX ../../pcre/SRC/pcre.c 89;" d file: -REQ_CASELESS ../../pcre/SRC/internal.h 220;" d -REQ_NONE ../../pcre/SRC/internal.h 215;" d -REQ_UNSET ../../pcre/SRC/internal.h 214;" d -REQ_VARY ../../pcre/SRC/internal.h 221;" d RET_SWSEG_TRACK_APPLIED ./route/rr_graph_swseg.c /^ RET_SWSEG_TRACK_APPLIED$/;" e enum:ret_track_swseg_pattern file: RET_SWSEG_TRACK_DIR_UNMATCH ./route/rr_graph_swseg.c /^ RET_SWSEG_TRACK_DIR_UNMATCH,$/;" e enum:ret_track_swseg_pattern file: RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN ./route/rr_graph_swseg.c /^ RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN,$/;" e enum:ret_track_swseg_pattern file: -RIGHT ../../libarchfpga/include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side ROUND_UP ./route/route_timing.c 682;" d file: ROUTE_CMD ./fpga_x2p/shell/shell_types.h /^ ROUTE_CMD,$/;" e enum:e_cmd_category ROUTE_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 4;" d @@ -1097,12 +613,8 @@ RR_GRAPH_SBOX_H ./route/rr_graph_sbox.h 2;" d RR_GRAPH_WARN_CHAN_WIDTH_CHANGED ./route/rr_graph.h /^ RR_GRAPH_WARN_CHAN_WIDTH_CHANGED = 0x02$/;" e enum:__anon17 RR_GRAPH_WARN_FC_CLIPPED ./route/rr_graph.h /^ RR_GRAPH_WARN_FC_CLIPPED = 0x01,$/;" e enum:__anon17 RUN_FLOW ./base/vpr_types.h /^ RUN_FLOW, TIMING_ANALYSIS_ONLY$/;" e enum:e_operation -R_minW_nmos ../../libarchfpga/include/physical_types.h /^ float R_minW_nmos;$/;" m struct:s_arch R_minW_nmos ./base/vpr_types.h /^ float R_minW_nmos;$/;" m struct:s_det_routing_arch -R_minW_pmos ../../libarchfpga/include/physical_types.h /^ float R_minW_pmos;$/;" m struct:s_arch R_minW_pmos ./base/vpr_types.h /^ float R_minW_pmos;$/;" m struct:s_det_routing_arch -R_opin_cblock ../../libarchfpga/include/arch_types_mrfpga.h /^ float R_opin_cblock;$/;" m struct:s_arch_mrfpga -R_opin_cblock ../../libarchfpga/include/physical_types.h /^ float R_opin_cblock;$/;" m struct:s_timing_inf R_upstream ./route/route_common.h /^ float R_upstream;$/;" m struct:s_heap R_upstream ./route/route_tree_timing.h /^ float R_upstream;$/;" m struct:s_rt_node ReadBaseCostType ./base/ReadOptions.c /^ReadBaseCostType(INP char **Args, OUTP enum e_base_cost_type *BaseCostType) {$/;" f file: @@ -1111,7 +623,6 @@ ReadClusterSeed ./base/ReadOptions.c /^ReadClusterSeed(INP char **Args, OUTP enu ReadFixPins ./base/ReadOptions.c /^ReadFixPins(INP char **Args, OUTP char **PinFile) {$/;" f file: ReadFloat ./base/ReadOptions.c /^ReadFloat(INP char ** Args, OUTP float *Val) {$/;" f file: ReadInt ./base/ReadOptions.c /^ReadInt(INP char **Args, OUTP int *Val) {$/;" f file: -ReadLineTokens ../../libarchfpga/ReadLine.c /^ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum) {$/;" f ReadOnOff ./base/ReadOptions.c /^ReadOnOff(INP char **Args, OUTP boolean * Val) {$/;" f file: ReadOptions ./base/ReadOptions.c /^void ReadOptions(INP int argc, INP char **argv, OUTP t_options * Options) {$/;" f ReadPackerAlgorithm ./base/ReadOptions.c /^ReadPackerAlgorithm(INP char **Args, OUTP enum e_packer_algorithm *Algo) {$/;" f file: @@ -1121,7 +632,6 @@ ReadRouterAlgorithm ./base/ReadOptions.c /^ReadRouterAlgorithm(INP char **Args, ReadString ./base/ReadOptions.c /^ReadString(INP char **Args, OUTP char **Val) {$/;" f file: ReadToken ./base/ReadOptions.c /^ReadToken(INP char **Args, OUTP enum e_OptionArgToken *Token) {$/;" f file: RecomputeCritIter ./base/ReadOptions.h /^ int RecomputeCritIter;$/;" m struct:s_options -Rmetal ../../libarchfpga/include/physical_types.h /^ float Rmetal;$/;" m struct:s_segment_inf Rmetal ./base/vpr_types.h /^ float Rmetal;$/;" m struct:s_seg_details RouteChanWidth ./base/ReadOptions.h /^ int RouteChanWidth;$/;" m struct:s_options RouteFile ./base/ReadOptions.h /^ char *RouteFile;$/;" m struct:s_options @@ -1130,15 +640,12 @@ RouteType ./base/ReadOptions.h /^ enum e_route_type RouteType;$/;" m struct:s_op RouterAlgorithm ./base/ReadOptions.h /^ enum e_router_algorithm RouterAlgorithm;$/;" m struct:s_options typeref:enum:s_options::e_router_algorithm RouterOpts ./base/vpr_types.h /^ struct s_router_opts RouterOpts; \/* router options *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_router_opts RoutingArch ./base/vpr_types.h /^ struct s_det_routing_arch RoutingArch; \/* routing architecture *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_det_routing_arch -Rseg_global ../../libarchfpga/include/arch_types_mrfpga.h /^ float Rseg_global;$/;" m struct:s_arch_mrfpga Rseg_global ./mrfpga/mrfpga_globals.c /^float Rseg_global, Cseg_global;$/;" v SAME_TRACK ./route/rr_graph2.c 23;" d file: SBOX_ERROR ./route/rr_graph_sbox.c 99;" d file: -SBType ../../libarchfpga/include/physical_types.h /^ enum e_switch_block_type SBType;$/;" m struct:s_arch typeref:enum:s_arch::e_switch_block_type SCALE_DISTANCE_VAL ./pack/cluster.c 48;" d file: SCALE_NUM_PATHS ./pack/cluster.c 39;" d file: SCREEN ./base/graphics.c /^ SCREEN = 0,$/;" e enum:__anon2 file: -SDCFile ../../libarchfpga/include/physical_types.h /^ char * SDCFile; \/* only here for convenience of passing to path_delay.c *\/$/;" m struct:s_timing_inf SDCFile ./base/ReadOptions.h /^ char *SDCFile;$/;" m struct:s_options SDCFile ./base/vpr_types.h /^ char *SDCFile;$/;" m struct:s_file_name_opts SDC_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 8;" d @@ -1171,87 +678,19 @@ SOURCE ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_C SOURCE_BLOCK ./place/timing_place_lookup.c 49;" d file: SOURCE_COST_INDEX ./base/vpr_types.h /^ SOURCE_COST_INDEX = 0,$/;" e enum:e_cost_indices SPACE ./timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: -SPICE_ABS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type -SPICE_CB_MUX_TB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_CB_MUX_TB, $/;" e enum:e_spice_tb_type -SPICE_CB_TB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_CB_TB,$/;" e enum:e_spice_tb_type -SPICE_FRAC ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type -SPICE_GRID_TB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_GRID_TB,$/;" e enum:e_spice_tb_type -SPICE_HARDLOGIC_TB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_HARDLOGIC_TB$/;" e enum:e_spice_tb_type -SPICE_IO_TB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_IO_TB,$/;" e enum:e_spice_tb_type -SPICE_LIB_ACADEMIA ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_LIB_ACADEMIA$/;" e enum:e_spice_tech_lib_type -SPICE_LIB_INDUSTRY ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_LIB_INDUSTRY,$/;" e enum:e_spice_tech_lib_type -SPICE_LUT_TB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_LUT_TB,$/;" e enum:e_spice_tb_type SPICE_MEASURE_DYNAMIC_POWER ./fpga_x2p/spice/spice_utils.h /^ SPICE_MEASURE_LEAKAGE_POWER, SPICE_MEASURE_DYNAMIC_POWER$/;" e enum:e_measure_type SPICE_MEASURE_LEAKAGE_POWER ./fpga_x2p/spice/spice_utils.h /^ SPICE_MEASURE_LEAKAGE_POWER, SPICE_MEASURE_DYNAMIC_POWER$/;" e enum:e_measure_type -SPICE_MODEL_BUF_BUF ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_BUF$/;" e enum:e_spice_model_buffer_type -SPICE_MODEL_BUF_INV ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_INV, $/;" e enum:e_spice_model_buffer_type -SPICE_MODEL_CHAN_WIRE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_CHAN_WIRE, $/;" e enum:e_spice_model_type -SPICE_MODEL_DELAY_FALL ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DELAY_FALL$/;" e enum:spice_model_delay_type -SPICE_MODEL_DELAY_RISE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DELAY_RISE, $/;" e enum:spice_model_delay_type -SPICE_MODEL_DESIGN_CMOS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_CMOS, $/;" e enum:e_spice_model_design_tech -SPICE_MODEL_DESIGN_RRAM ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_RRAM$/;" e enum:e_spice_model_design_tech -SPICE_MODEL_FF ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_FF, $/;" e enum:e_spice_model_type -SPICE_MODEL_GATE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_GATE $/;" e enum:e_spice_model_type -SPICE_MODEL_GATE_AND ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_GATE_AND, $/;" e enum:e_spice_model_gate_type -SPICE_MODEL_GATE_OR ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_GATE_OR$/;" e enum:e_spice_model_gate_type -SPICE_MODEL_HARDLOGIC ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_HARDLOGIC,$/;" e enum:e_spice_model_type -SPICE_MODEL_INVBUF ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_INVBUF, $/;" e enum:e_spice_model_type -SPICE_MODEL_IOPAD ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_IOPAD, $/;" e enum:e_spice_model_type -SPICE_MODEL_LUT ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_LUT, $/;" e enum:e_spice_model_type -SPICE_MODEL_MUX ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_MUX, $/;" e enum:e_spice_model_type -SPICE_MODEL_PASSGATE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASSGATE, $/;" e enum:e_spice_model_type -SPICE_MODEL_PASS_GATE_TRANSISTOR ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSISTOR$/;" e enum:e_spice_model_pass_gate_logic_type -SPICE_MODEL_PASS_GATE_TRANSMISSION ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSMISSION, $/;" e enum:e_spice_model_pass_gate_logic_type -SPICE_MODEL_PORT_BL ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BL,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_BLB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BLB,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_CLOCK ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_CLOCK, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_INOUT ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INOUT, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_INPUT ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INPUT, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_OUTPUT ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_OUTPUT, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_SRAM ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_SRAM,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_WL ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WL,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_WLB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WLB$/;" e enum:e_spice_model_port_type -SPICE_MODEL_SCFF ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_SCFF,$/;" e enum:e_spice_model_type -SPICE_MODEL_SRAM ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_SRAM, $/;" e enum:e_spice_model_type -SPICE_MODEL_STRUCTURE_CROSSBAR ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_CROSSBAR $/;" e enum:e_spice_model_structure -SPICE_MODEL_STRUCTURE_MULTILEVEL ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_MULTILEVEL, $/;" e enum:e_spice_model_structure -SPICE_MODEL_STRUCTURE_ONELEVEL ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_ONELEVEL, $/;" e enum:e_spice_model_structure -SPICE_MODEL_STRUCTURE_TREE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_TREE, $/;" e enum:e_spice_model_structure -SPICE_MODEL_WIRE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_WIRE, $/;" e enum:e_spice_model_type -SPICE_PB_MUX_TB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_PB_MUX_TB, $/;" e enum:e_spice_tb_type -SPICE_PB_PORT_CLOCK ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_PB_PORT_CLOCK$/;" e enum:e_spice_pb_port_type -SPICE_PB_PORT_INPUT ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_PB_PORT_INPUT,$/;" e enum:e_spice_pb_port_type -SPICE_PB_PORT_OUTPUT ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_PB_PORT_OUTPUT,$/;" e enum:e_spice_pb_port_type -SPICE_SB_MUX_TB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_SB_MUX_TB, $/;" e enum:e_spice_tb_type -SPICE_SB_TB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_SB_TB,$/;" e enum:e_spice_tb_type -SPICE_SRAM_MEMORY_BANK ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_SRAM_MEMORY_BANK$/;" e enum:e_sram_orgz -SPICE_SRAM_SCAN_CHAIN ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_SRAM_SCAN_CHAIN,$/;" e enum:e_sram_orgz -SPICE_SRAM_STANDALONE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_SRAM_STANDALONE,$/;" e enum:e_sram_orgz -SPICE_TRANS_IO_NMOS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_TRANS_IO_NMOS, $/;" e enum:e_spice_trans_type -SPICE_TRANS_IO_PMOS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type -SPICE_TRANS_NMOS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, $/;" e enum:e_spice_trans_type -SPICE_TRANS_PMOS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_TRANS_PMOS, $/;" e enum:e_spice_trans_type STAR ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: STARQ ./timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: -STRING ../../pcre/SRC/pcre.c 387;" d file: -STTRAM ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -SUBSET ../../libarchfpga/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type -SWSEG_UNBUF_CB ../../libarchfpga/include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type -SWSEG_UNBUF_SB ../../libarchfpga/include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type Seed ./base/ReadOptions.h /^ int Seed;$/;" m struct:s_options -Segments ../../libarchfpga/include/physical_types.h /^ t_segment_inf * Segments;$/;" m struct:s_arch Segments ./base/vpr_types.h /^ t_segment_inf * Segments; \/* wires in routing architecture *\/$/;" m struct:s_vpr_setup SetPostSynthesisOption ./base/ReadOptions.c /^void SetPostSynthesisOption(boolean post_synthesis_enabled){$/;" f SettingsFile ./base/ReadOptions.h /^ char *SettingsFile;$/;" m struct:s_options SetupAnnealSched ./base/SetupVPR.c /^static void SetupAnnealSched(INP t_options Options,$/;" f file: SetupBitstreamGenOpts ./base/SetupVPR.c /^static void SetupBitstreamGenOpts(t_options Options, $/;" f file: -SetupEmptyType ../../libarchfpga/read_xml_arch_file.c /^static void SetupEmptyType(void) {$/;" f file: SetupFpgaSpiceOpts ./base/SetupVPR.c /^static void SetupFpgaSpiceOpts(t_options Options, $/;" f file: -SetupGridLocations ../../libarchfpga/read_xml_arch_file.c /^static void SetupGridLocations(ezxml_t Locations, t_type_descriptor * Type) {$/;" f file: SetupOperation ./base/SetupVPR.c /^static void SetupOperation(INP t_options Options,$/;" f file: SetupPackerOpts ./base/SetupVPR.c /^void SetupPackerOpts(INP t_options Options, INP boolean TimingEnabled,$/;" f -SetupPinEquivalenceAutoDetect ../../libarchfpga/read_xml_arch_file.c /^void SetupPinEquivalenceAutoDetect(ezxml_t Parent, t_type_descriptor* Type) {$/;" f file: -SetupPinLocationsAndPinClasses ../../libarchfpga/read_xml_arch_file.c /^static void SetupPinLocationsAndPinClasses(ezxml_t Locations,$/;" f file: SetupPlacerOpts ./base/SetupVPR.c /^static void SetupPlacerOpts(INP t_options Options, INP boolean TimingEnabled,$/;" f file: SetupPowerOpts ./base/SetupVPR.c /^static void SetupPowerOpts(t_options Options, t_power_opts *power_opts,$/;" f file: SetupRouterOpts ./base/SetupVPR.c /^static void SetupRouterOpts(INP t_options Options, INP boolean TimingEnabled,$/;" f file: @@ -1274,10 +713,7 @@ ShowSetup ./base/ShowSetup.c /^void ShowSetup(INP t_options options, INP t_vpr_s SpiceOpts ./base/vpr_types.h /^ t_spice_opts SpiceOpts; \/* Xifan TANG: SPICE Support*\/$/;" m struct:s_fpga_spice_opts StatusWND ./base/graphics.c /^StatusWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: Str ./base/vpr_types.h /^ const char *Str;$/;" m struct:s_TokenPair -Switches ../../libarchfpga/include/physical_types.h /^ struct s_switch_inf *Switches;$/;" m struct:s_arch typeref:struct:s_arch::s_switch_inf SynVerilogOpts ./base/vpr_types.h /^ t_syn_verilog_opts SynVerilogOpts; \/* Xifan TANG: Synthesizable verilog dumping*\/$/;" m struct:s_fpga_spice_opts -SyncModelsPbTypes ../../libarchfpga/read_xml_arch_file.c /^static void SyncModelsPbTypes(INOUTP struct s_arch *arch,$/;" f file: -SyncModelsPbTypes_rec ../../libarchfpga/read_xml_arch_file.c /^static void SyncModelsPbTypes_rec(INOUTP struct s_arch *arch,$/;" f file: TABLENGTH ./pack/output_blif.c 19;" d file: TAB_LENGTH ./pack/output_clustering.c 17;" d file: THISTLE ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types @@ -1300,7 +736,6 @@ TN_OUTPAD_IPIN ./base/vpr_types.h /^ TN_OUTPAD_IPIN, \/* input to an output I\/O TN_OUTPAD_SINK ./base/vpr_types.h /^ TN_OUTPAD_SINK, \/* output from an output I\/O pad *\/$/;" e enum:__anon7 TN_PRIMITIVE_IPIN ./base/vpr_types.h /^ TN_PRIMITIVE_IPIN, \/* input pin to a primitive (e.g. a LUT) *\/$/;" e enum:__anon7 TN_PRIMITIVE_OPIN ./base/vpr_types.h /^ TN_PRIMITIVE_OPIN, \/* output pin from a primitive (e.g. a LUT) *\/$/;" e enum:__anon7 -TOKENS ../../libarchfpga/include/arch_types.h 19;" d TOKENS ./base/vpr_types.h 66;" d TOKEN_CLOSE_SQUARE_BRACKET ./util/token.h /^ TOKEN_CLOSE_SQUARE_BRACKET,$/;" e enum:e_token_type TOKEN_CLOSE_SQUIG_BRACKET ./util/token.h /^ TOKEN_CLOSE_SQUIG_BRACKET,$/;" e enum:e_token_type @@ -1312,25 +747,14 @@ TOKEN_NULL ./util/token.h /^ TOKEN_NULL,$/;" e enum:e_token_type TOKEN_OPEN_SQUARE_BRACKET ./util/token.h /^ TOKEN_OPEN_SQUARE_BRACKET,$/;" e enum:e_token_type TOKEN_OPEN_SQUIG_BRACKET ./util/token.h /^ TOKEN_OPEN_SQUIG_BRACKET,$/;" e enum:e_token_type TOKEN_STRING ./util/token.h /^ TOKEN_STRING,$/;" e enum:e_token_type -TOP ../../libarchfpga/include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side -TRUE ../../libarchfpga/include/util.h /^ FALSE, TRUE$/;" e enum:__anon23 -TRUE ../../pcre/SRC/internal.h 228;" d TRUE ./base/graphics.c 145;" d file: TURQUOISE ./base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types -TYPICAL_CORNER ../../libarchfpga/fpga_spice_include/spice_types.h /^ TYPICAL_CORNER,$/;" e enum:e_process_corner T_AREA_HEIGHT ./base/graphics.c 178;" d file: T_arr ./base/vpr_types.h /^ float T_arr; \/* Arrival time of the last input signal to this node. *\/$/;" m struct:s_tnode T_crit ./power/power.h /^ float T_crit;$/;" m struct:s_solution_inf -T_ipin_cblock ../../libarchfpga/include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_arch -T_ipin_cblock ../../libarchfpga/include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_timing_inf T_linear ./base/vpr_types.h /^ float T_linear;$/;" m struct:s_rr_indexed_data -T_opin_cblock ../../libarchfpga/include/arch_types_mrfpga.h /^ float T_opin_cblock;$/;" m struct:s_arch_mrfpga -T_opin_cblock ../../libarchfpga/include/physical_types.h /^ float T_opin_cblock;$/;" m struct:s_timing_inf T_quadratic ./base/vpr_types.h /^ float T_quadratic;$/;" m struct:s_rr_indexed_data T_req ./base/vpr_types.h /^ float T_req; \/* Required arrival time of the last input signal to this node $/;" m struct:s_tnode -Tdel ../../libarchfpga/include/arch_types_mrfpga.h /^ float Tdel; $/;" m struct:s_memristor_inf -Tdel ../../libarchfpga/include/arch_types_mrfpga.h /^ float Tdel;$/;" m struct:s_buffer_inf -Tdel ../../libarchfpga/include/physical_types.h /^ float Tdel;$/;" m struct:s_switch_inf Tdel ./base/vpr_types.h /^ float Tdel; \/* delay to go to to_node along this edge *\/$/;" m struct:s_tedge Tdel ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: Tdel ./route/route_tree_timing.h /^ float Tdel;$/;" m struct:s_rt_node @@ -1338,18 +762,11 @@ Tdel ./timing/net_delay_types.h /^ float Tdel;$/;" m struct:s_rc_node Timing ./base/vpr_types.h /^ t_timing_inf Timing; \/* timing information *\/$/;" m struct:s_vpr_setup TimingAnalysis ./base/ReadOptions.h /^ boolean TimingAnalysis;$/;" m struct:s_options TimingEnabled ./base/vpr_types.h /^ boolean TimingEnabled; \/* Is VPR timing enabled *\/$/;" m struct:s_vpr_setup -UNDEFINED ../../libarchfpga/include/arch_types.h 22;" d UNDEFINED ./base/vpr_types.h 103;" d -UNIFORM ../../libarchfpga/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat -UNIVERSAL ../../libarchfpga/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type -UNI_DIRECTIONAL ../../libarchfpga/include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality -UNKNOWN_CLASS ../../libarchfpga/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class UN_SET ./route/rr_graph2.c 24;" d file: UPDATED_ONCE ./place/place.c 46;" d file: USER ./base/vpr_types.h /^ FREE, RANDOM, USER$/;" e enum:e_pad_loc_type USER_SCHED ./base/vpr_types.h /^ AUTO_SCHED, USER_SCHED$/;" e enum:sched_type -UTIL_H ../../libarchfpga/include/util.h 2;" d -UpdateAndCheckModels ../../libarchfpga/read_xml_arch_file.c /^static void UpdateAndCheckModels(INOUTP struct s_arch *arch) {$/;" f file: VERILOG_PORT_CONKT ./fpga_x2p/verilog/verilog_global.h /^VERILOG_PORT_CONKT$/;" e enum:e_dump_verilog_port_type VERILOG_PORT_INOUT ./fpga_x2p/verilog/verilog_global.h /^VERILOG_PORT_INOUT,$/;" e enum:e_dump_verilog_port_type VERILOG_PORT_INPUT ./fpga_x2p/verilog/verilog_global.h /^VERILOG_PORT_INPUT,$/;" e enum:e_dump_verilog_port_type @@ -1371,36 +788,20 @@ VPRSetupArch ./base/SetupVPR.c /^void VPRSetupArch(t_arch* arch, $/;" f VPR_API_H ./base/vpr_api.h 27;" d VPR_TYPES_H ./base/vpr_types.h 34;" d VPR_UTILS_H ./util/vpr_utils.h 2;" d -VPR_VERSION ../../libarchfpga/include/arch_types.h 16;" d Vdd ./power/power.h /^ float Vdd;$/;" m struct:s_power_tech -W ../../libarchfpga/include/physical_types.h /^ int W;$/;" m struct:s_clb_grid -WARNTAG ../../libarchfpga/include/util.h 27;" d WHITE ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types -WILTON ../../libarchfpga/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type WIRED_LUT_LOGICAL_BLOCK_ID ./fpga_x2p/base/fpga_x2p_types.h 16;" d WIRED_LUT_MODE_INDEX ./fpga_x2p/base/fpga_x2p_types.h 24;" d -WIRE_MODEL_PIE ../../libarchfpga/fpga_spice_include/spice_types.h /^ WIRE_MODEL_PIE,$/;" e enum:e_wire_model_type -WIRE_MODEL_T ../../libarchfpga/fpga_spice_include/spice_types.h /^ WIRE_MODEL_T$/;" e enum:e_wire_model_type -WIRE_SEGMENT_LENGTH ./base/vpr_api.c 517;" d file: +WIRE_SEGMENT_LENGTH ./base/vpr_api.c 518;" d file: WL ./base/place_and_route.h 5;" d WNEED ./base/place_and_route.h 4;" d -WORST_CORNER ../../libarchfpga/fpga_spice_include/spice_types.h /^ WORST_CORNER$/;" e enum:e_process_corner W_seed ./base/globals.c /^int W_seed = -1;$/;" v X11 ./base/graphics.h 13;" d -XCL_END ../../pcre/SRC/internal.h 274;" d -XCL_MAP ../../pcre/SRC/internal.h 272;" d -XCL_NOT ../../pcre/SRC/internal.h 271;" d -XCL_RANGE ../../pcre/SRC/internal.h 276;" d -XCL_SINGLE ../../pcre/SRC/internal.h 275;" d XPOST ./base/graphics.c 161;" d file: -XSTRING ../../pcre/SRC/pcre.c 388;" d file: XTOWORLD ./base/graphics.c 167;" d file: -XmlReadArch ../../libarchfpga/read_xml_arch_file.c /^void XmlReadArch(INP const char *ArchFile, INP boolean timing_enabled,$/;" f YELLOW ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types YPOST ./base/graphics.c 162;" d file: YTOWORLD ./base/graphics.c 168;" d file: -_EZXML_H ../../libarchfpga/include/ezxml.h 26;" d -_PCRE_H ../../pcre/SRC/pcre.h 8;" d __POWER_CMOS_TECH_H__ ./power/power_cmos_tech.h 26;" d __POWER_COMPONENTS_H__ ./power/power_components.h 24;" d __POWER_H__ ./power/power.h 23;" d @@ -1410,19 +811,13 @@ __POWER_POWERSPICEDCOMPONENT_NMOS_H__ ./power/PowerSpicedComponent.h 19;" d __POWER_TRANSISTOR_CNT_H__ ./power/power_sizing.h 24;" d __POWER_UTIL_H__ ./power/power_util.h 23;" d _drawcurve ./base/graphics.c /^static void _drawcurve(t_point *points, int npoints, int fill) {$/;" f file: -abs_variation ../../libarchfpga/fpga_spice_include/spice_types.h /^ float abs_variation;$/;" m struct:s_spice_mc_variation_params -absolute_length ../../libarchfpga/include/physical_types.h /^ float absolute_length;$/;" m union:s_port_power::__anon22 -absolute_power_per_instance ../../libarchfpga/include/physical_types.h /^ t_power_usage absolute_power_per_instance; \/* User-provided absolute power per block *\/$/;" m struct:s_pb_type_power absorb_buffer_luts ./base/read_blif.c /^static void absorb_buffer_luts(void) {$/;" f file: acc_cost ./route/route_common.h /^ float acc_cost;$/;" m struct:__anon15 acc_fac ./base/ReadOptions.h /^ float acc_fac;$/;" m struct:s_options acc_fac ./base/vpr_types.h /^ float acc_fac;$/;" m struct:s_router_opts -accuracy ../../libarchfpga/fpga_spice_include/spice_types.h /^ float accuracy;$/;" m struct:s_spice_meas_params -accuracy_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type accuracy_type;$/;" m struct:s_spice_meas_params typeref:enum:s_spice_meas_params::e_spice_accuracy_type adapt_truth_table_for_frac_lut ./fpga_x2p/base/fpga_x2p_lut_utils.c /^void adapt_truth_table_for_frac_lut(t_pb_graph_pin* lut_out_pb_graph_pin, $/;" f add_activity_to_net ./base/read_blif.c /^bool add_activity_to_net(char * net_name, float probability, float density) {$/;" f add_conf_bit_info_to_llist ./fpga_x2p/base/fpga_x2p_utils.c /^add_conf_bit_info_to_llist(t_llist* head, int index, $/;" f -add_const_input ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean add_const_input;$/;" m struct:s_spice_model_mux add_data_point ./power/PowerSpicedComponent.c /^void PowerSpicedComponent::add_data_point(int num_inputs, float transistor_size,$/;" f class:PowerSpicedComponent add_delay_to_array ./mrfpga/buffer_insertion.c /^static void add_delay_to_array( float* sink_delay, t_linked_int* index, float delay_addition )$/;" f file: add_delay_to_buffer_list ./mrfpga/buffer_insertion.c /^static void add_delay_to_buffer_list( t_buffer_plan_list list, float Tdel , boolean skip_first )$/;" f file: @@ -1468,13 +863,10 @@ add_to_sort_heap ./util/heapsort.c /^static void add_to_sort_heap(int *heap, flo add_virtual_sources_to_rr_graph_multi_sources ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^int add_virtual_sources_to_rr_graph_multi_sources(t_rr_graph* local_rr_graph) {$/;" f add_vpack_net ./base/read_blif.c /^static int add_vpack_net(char *ptr, int type, int bnum, int bport, int bpin,$/;" f file: add_wire_to_switch ./base/SetupVPR.c /^static void add_wire_to_switch(struct s_det_routing_arch *det_routing_arch) {$/;" f file: -addr ../../libarchfpga/fpga_spice_include/spice_types.h /^ int addr; \/* Address to write the value *\/$/;" m struct:s_conf_bit adjustButton ./base/graphics.c /^static int windowAdjustFlag = 0, adjustButton = -1;$/;" v file: adjustRect ./base/graphics.c /^static RECT adjustRect, updateRect;$/;" v file: adjust_one_rr_occ_and_pcost ./route/route_common.c /^static void adjust_one_rr_occ_and_pcost(int inode, int add_or_sub,$/;" f file: adjustwin ./base/graphics.c /^adjustwin (void (*drawscreen) (void)) $/;" f file: -advanced_rram_design ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean advanced_rram_design;$/;" m struct:s_spice_model_mux -after_call ../../pcre/SRC/internal.h /^ const uschar *after_call; \/* "Return value": points after the call in the expr *\/$/;" m struct:recursion_info alloc_SRAM_values_from_truth_table ./power/power_util.c /^char * alloc_SRAM_values_from_truth_table(int LUT_size,$/;" f alloc_and_add_fully_capacity_rr_edges_to_one_grid ./route/pb_pin_eq_auto_detect.c /^int alloc_and_add_fully_capacity_rr_edges_to_one_grid(int grid_x, int grid_y, int grid_z,$/;" f alloc_and_add_fully_capacity_rr_edges_to_source_opin ./route/pb_pin_eq_auto_detect.c /^int alloc_and_add_fully_capacity_rr_edges_to_source_opin(t_type_ptr cur_type_descriptor,$/;" f @@ -1497,7 +889,6 @@ alloc_and_load_cluster_info ./pack/cluster.c /^static void alloc_and_load_cluste alloc_and_load_cluster_legality_checker ./pack/cluster_legality.c /^void alloc_and_load_cluster_legality_checker(void) {$/;" f alloc_and_load_cluster_placement_stats ./pack/cluster_placement.c /^t_cluster_placement_stats *alloc_and_load_cluster_placement_stats(void) {$/;" f alloc_and_load_complete_interc_edges ./pack/pb_type_graph.c /^static void alloc_and_load_complete_interc_edges($/;" f file: -alloc_and_load_default_child_for_pb_type ../../libarchfpga/read_xml_arch_file.c /^static void alloc_and_load_default_child_for_pb_type( INOUTP t_pb_type *pb_type,$/;" f file: alloc_and_load_direct_interc_edges ./pack/pb_type_graph.c /^static void alloc_and_load_direct_interc_edges($/;" f file: alloc_and_load_echo_file_info ./base/ReadOptions.c /^void alloc_and_load_echo_file_info() {$/;" f alloc_and_load_edges_and_switches ./route/rr_graph.c /^void alloc_and_load_edges_and_switches(INP t_rr_node * L_rr_node, INP int inode,$/;" f @@ -1568,15 +959,11 @@ alloc_hash_table ./util/hash.c /^alloc_hash_table(void) {$/;" f alloc_heap_data ./route/route_common.c /^alloc_heap_data(void) {$/;" f file: alloc_internal_cb_nets ./base/read_netlist.c /^static void alloc_internal_cb_nets(INOUTP t_pb *top_level,$/;" f file: alloc_isink_to_inode ./mrfpga/buffer_insertion.c /^static int alloc_isink_to_inode( int inet, int** isink_to_inode_ptr )$/;" f file: -alloc_ivector_and_copy_int_list ../../libarchfpga/util.c /^void alloc_ivector_and_copy_int_list(t_linked_int ** list_head_ptr,$/;" f alloc_legal_placements ./place/place.c /^static void alloc_legal_placements() {$/;" f file: alloc_linked_f_pointer ./route/route_common.c /^alloc_linked_f_pointer(void) {$/;" f file: alloc_linked_rc_edge ./timing/net_delay.c /^alloc_linked_rc_edge(t_linked_rc_edge ** rc_edge_free_list_ptr) {$/;" f alloc_linked_rt_edge ./route/route_tree_timing.c /^alloc_linked_rt_edge(void) {$/;" f file: alloc_lookups_and_criticalities ./place/timing_place.c /^t_slack * alloc_lookups_and_criticalities(t_chan_width_dist chan_width_dist,$/;" f -alloc_matrix ../../libarchfpga/util.c /^alloc_matrix(int nrmin, int nrmax, int ncmin, int ncmax, size_t elsize) {$/;" f -alloc_matrix3 ../../libarchfpga/util.c /^alloc_matrix3(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f -alloc_matrix4 ../../libarchfpga/util.c /^alloc_matrix4(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f alloc_net ./place/timing_place_lookup.c /^static void alloc_net(void) {$/;" f file: alloc_net_delay ./timing/net_delay.c /^alloc_net_delay(t_chunk *chunk_list_ptr, struct s_net *nets,$/;" f alloc_net_rr_terminals ./route/rr_graph.c /^static void alloc_net_rr_terminals(void) {$/;" f file: @@ -1627,27 +1014,24 @@ annotate_pb_type_port_to_phy_pb_type ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^ annotate_physical_mode_pin_to_pb_type ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void annotate_physical_mode_pin_to_pb_type(t_port* cur_pb_type_port,$/;" f annotate_physical_mode_pins_in_pb_graph_node ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void annotate_physical_mode_pins_in_pb_graph_node() {$/;" f annotate_spice_model_timing ./fpga_x2p/base/fpga_x2p_timing_utils.c /^void annotate_spice_model_timing(t_spice_model* cur_spice_model) {$/;" f -annotations ../../libarchfpga/include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_interconnect -annotations ../../libarchfpga/include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_pb_type anyof ./timing/slre.c /^static void anyof(struct slre *r, const char **re) {$/;" f file: apply_swseg_pattern_chanx_track ./route/rr_graph_swseg.c /^ apply_swseg_pattern_chanx_track(INP int track_id,$/;" f file: apply_swseg_pattern_chany_track ./route/rr_graph_swseg.c /^ apply_swseg_pattern_chany_track(INP int track_id,$/;" f file: arch ./fpga_x2p/shell/shell_types.h /^ t_arch arch;$/;" m struct:s_shell_env -arch_mrfpga ../../libarchfpga/include/physical_types.h /^ t_arch_mrfpga arch_mrfpga;$/;" m struct:s_arch -area ../../libarchfpga/fpga_spice_include/spice_types.h /^ float area; \/\/Xifan TANG$/;" m struct:s_sram_inf -area ../../libarchfpga/include/physical_types.h /^ float area;$/;" m struct:s_type_descriptor aspect ./base/vpr_types.h /^ float aspect;$/;" m struct:s_packer_opts assess_swap ./place/place.c /^static enum swap_result assess_swap(float delta_c, float t) {$/;" f file: assign_blocks_and_route_net ./place/timing_place_lookup.c /^static float assign_blocks_and_route_net(t_type_ptr source_type,$/;" f file: +assign_connection_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void assign_connection_block_mirror(t_cb* src, t_cb* des) {$/;" f assign_locations ./place/timing_place_lookup.c /^static void assign_locations(t_type_ptr source_type, int source_x_loc,$/;" f file: assign_lut_truth_table ./fpga_x2p/base/fpga_x2p_lut_utils.c /^char** assign_lut_truth_table(t_logical_block* mapped_logical_block,$/;" f +assign_mirror_connection_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void assign_mirror_connection_blocks() {$/;" f +assign_mirror_switch_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void assign_mirror_switch_blocks() {$/;" f assign_pb_graph_node_pin_temp_net_num_by_mode_index ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void assign_pb_graph_node_pin_temp_net_num_by_mode_index(t_pb_graph_pin* cur_pb_graph_pin,$/;" f assign_post_routing_lut_truth_table ./fpga_x2p/base/fpga_x2p_lut_utils.c /^char** assign_post_routing_lut_truth_table(t_logical_block* mapped_logical_block,$/;" f assign_post_routing_wired_lut_truth_table ./fpga_x2p/base/fpga_x2p_lut_utils.c /^char** assign_post_routing_wired_lut_truth_table(int lut_output_vpack_net_num,$/;" f +assign_switch_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void assign_switch_block_mirror(t_sb* src, t_sb* des) {$/;" f astar_fac ./base/ReadOptions.h /^ float astar_fac;$/;" m struct:s_options astar_fac ./base/vpr_types.h /^ float astar_fac;$/;" m struct:s_router_opts -attr ../../libarchfpga/include/ezxml.h /^ char ***attr; \/* default attributes *\/$/;" m struct:ezxml_root -attr ../../libarchfpga/include/ezxml.h /^ char **attr; \/* tag attributes { name, value, name, value, ... NULL } *\/$/;" m struct:ezxml auto_compute_inter_cluster_net_delay ./base/vpr_types.h /^ boolean auto_compute_inter_cluster_net_delay;$/;" m struct:s_packer_opts auto_detect_and_reserve_locally_used_opins ./route/route_common.c /^void auto_detect_and_reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins,$/;" f auto_detect_and_reserve_used_opins ./route/pb_pin_eq_auto_detect.c /^void auto_detect_and_reserve_used_opins(float pres_fac) {$/;" f @@ -1656,13 +1040,11 @@ auto_select_max_sim_num_clock_cycles ./fpga_x2p/spice/spice_mux_testbench.c /^st auto_select_max_sim_num_clock_cycles ./fpga_x2p/spice/spice_primitive_testbench.c /^static int auto_select_max_sim_num_clock_cycles = TRUE;$/;" v file: auto_select_max_sim_num_clock_cycles ./fpga_x2p/spice/spice_routing_testbench.c /^static int auto_select_max_sim_num_clock_cycles = TRUE;$/;" v file: auto_select_num_sim_clock_cycle ./fpga_x2p/base/fpga_x2p_utils.c /^void auto_select_num_sim_clock_cycle(t_spice* spice,$/;" f -auto_select_sim_num_clk_cycle ../../libarchfpga/fpga_spice_include/spice_types.h /^ int auto_select_sim_num_clk_cycle;$/;" m struct:s_spice_meas_params autocheck_testbench_postfix ./fpga_x2p/verilog/verilog_global.c /^char* autocheck_testbench_postfix = "_autocheck";$/;" v autocheck_testbench_reference_output_postfix ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^static char* autocheck_testbench_reference_output_postfix = "_benchmark";$/;" v file: autocheck_testbench_verification_output_postfix ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^static char* autocheck_testbench_verification_output_postfix = "_verification";$/;" v file: autocheck_top_testbench_verilog_file_postfix ./fpga_x2p/verilog/verilog_global.c /^char* autocheck_top_testbench_verilog_file_postfix = "_autocheck_top_tb.v"; \/* !!! must be consist with the modelsim_autocheck_testbench_module_postfix *\/ $/;" v autochecked_simulation_flag ./fpga_x2p/verilog/verilog_global.c /^char* autochecked_simulation_flag = "AUTOCHECKED_SIMULATION"; \/\/ the flag to enable autochecked functional verification$/;" v -autosize_buffer ../../libarchfpga/include/physical_types.h /^ boolean autosize_buffer; \/* autosize clock buffers *\/$/;" m struct:s_clock_network back_annotate_one_pb_rr_node_map_info_rec ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void back_annotate_one_pb_rr_node_map_info_rec(t_pb* cur_pb,$/;" f file: back_annotate_pb_rr_node_map_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void back_annotate_pb_rr_node_map_info() {$/;" f file: back_annotate_rr_node_map_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void back_annotate_rr_node_map_info() {$/;" f file: @@ -1674,15 +1056,12 @@ backannotate_pb_wired_luts ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void backannotate_rr_graph_routing_results_to_net_name ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void backannotate_rr_graph_routing_results_to_net_name(t_rr_graph* local_rr_graph) {$/;" f backannotate_rr_nodes_parasitic_net_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void backannotate_rr_nodes_parasitic_net_info() {$/;" f file: background_cindex ./base/graphics.c /^ int background_cindex;$/;" m struct:__anon5 file: -backref_map ../../pcre/SRC/internal.h /^ unsigned int backref_map; \/* Bitmap of low back refs *\/$/;" m struct:compile_data backup_one_pb_rr_node_pack_prev_node_edge ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void backup_one_pb_rr_node_pack_prev_node_edge(t_rr_node* pb_rr_node) {$/;" f backward_expand_pack_pattern_from_edge ./pack/prepack.c /^static void backward_expand_pack_pattern_from_edge($/;" f file: backward_infer_pattern ./pack/prepack.c /^static void backward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin) {$/;" f file: backward_path_cost ./route/route_common.h /^ float backward_path_cost;$/;" m struct:__anon15 backward_path_cost ./route/route_common.h /^ float backward_path_cost;$/;" m struct:s_heap backward_weight ./base/vpr_types.h /^ float forward_weight, backward_weight; \/* Weightings of the importance of paths $/;" m struct:s_tnode -base_cost ../../libarchfpga/include/cad_types.h /^ float base_cost; \/* base cost of pattern eg. If a group of logical blocks match a pattern of smaller primitives, that is better than the same group using bigger primitives *\/$/;" m struct:s_pack_patterns -base_cost ../../libarchfpga/include/cad_types.h /^ float base_cost; \/* cost independant of current status of packing *\/$/;" m struct:s_cluster_placement_primitive base_cost ./base/vpr_types.h /^ float base_cost;$/;" m struct:s_rr_indexed_data base_cost_type ./base/ReadOptions.h /^ enum e_base_cost_type base_cost_type;$/;" m struct:s_options typeref:enum:s_options::e_base_cost_type base_cost_type ./base/vpr_types.h /^ enum e_base_cost_type base_cost_type;$/;" m struct:s_router_opts typeref:enum:s_router_opts::e_base_cost_type @@ -1704,12 +1083,10 @@ binary_search ./base/globals.c /^int binary_search = -1;$/;" v binary_search_place_and_route ./base/place_and_route.c /^static int binary_search_place_and_route(struct s_placer_opts placer_opts,$/;" f file: bitfield ./base/vpr_types.h /^typedef size_t bitfield;$/;" t bitstream_output_file ./base/vpr_types.h /^ char* bitstream_output_file;$/;" m struct:s_bitstream_gen_opts -bl ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_conf_bit* bl;$/;" m struct:s_conf_bit_info blif ./base/read_blif.c /^static FILE *blif;$/;" v file: blif_circuit_name ./base/globals.c /^char *blif_circuit_name = NULL;$/;" v blif_file_name ./base/vpr_types.h /^ char *blif_file_name;$/;" m struct:s_packer_opts blif_hash ./base/read_blif.c /^static struct s_hash **blif_hash;$/;" v typeref:struct:s_hash file: -blif_model ../../libarchfpga/include/physical_types.h /^ char *blif_model;$/;" m struct:s_pb_type blif_testbench_verilog_file_postfix ./fpga_x2p/verilog/verilog_global.c /^char* blif_testbench_verilog_file_postfix = "_blif_tb.v";$/;" v blk_index ./place/place_macro.h /^ int blk_index;$/;" m struct:s_pl_macro_member block ./base/globals.c /^struct s_block *block = NULL;$/;" v typeref:struct:s_block @@ -1721,14 +1098,9 @@ block_delay ./base/ReadOptions.h /^ float block_delay;$/;" m struct:s_options block_delay ./base/vpr_types.h /^ float block_delay;$/;" m struct:s_packer_opts block_dist ./base/ReadOptions.h /^ int block_dist;$/;" m struct:s_options block_dist ./base/vpr_types.h /^ int block_dist;$/;" m struct:s_placer_opts -block_id ../../libarchfpga/include/cad_types.h /^ int block_id;$/;" m struct:s_pack_pattern_block block_num ./place/place.c /^ int block_num;$/;" m struct:s_pl_moved_block file: blocks ./base/vpr_types.h /^ int *blocks;$/;" m struct:s_grid_tile blocks_affected ./place/place.c /^static t_pl_blocks_to_be_moved blocks_affected;$/;" v file: -boolean ../../libarchfpga/include/util.h /^typedef int boolean;$/;" t -boolean ../../libarchfpga/include/util.h /^} boolean;$/;" t typeref:enum:__anon23 -branch_chain ../../pcre/SRC/internal.h /^typedef struct branch_chain {$/;" s -branch_chain ../../pcre/SRC/internal.h /^} branch_chain;$/;" t typeref:struct:branch_chain breadth_first_add_one_source_to_rr_graph_heap ./fpga_x2p/router/fpga_x2p_router.c /^void breadth_first_add_one_source_to_rr_graph_heap(t_rr_graph* local_rr_graph,$/;" f breadth_first_add_source_to_heap ./route/route_breadth_first.c /^static void breadth_first_add_source_to_heap(int inet) {$/;" f file: breadth_first_add_source_to_heap_cluster ./pack/cluster_legality.c /^static void breadth_first_add_source_to_heap_cluster(int inet) {$/;" f file: @@ -1746,15 +1118,8 @@ breadth_first_route_one_net_pb_rr_graph ./fpga_x2p/router/fpga_x2p_router.c /^bo breadth_first_route_one_single_source_net_pb_rr_graph ./fpga_x2p/router/fpga_x2p_router.c /^boolean breadth_first_route_one_single_source_net_pb_rr_graph(t_rr_graph* local_rr_graph, $/;" f break_loops ./fpga_x2p/verilog/verilog_sdc.c /^ boolean break_loops;$/;" m struct:s_sdc_opts file: break_loops_mux ./fpga_x2p/verilog/verilog_sdc.c /^ boolean break_loops_mux;$/;" m struct:s_sdc_opts file: -buf_size ../../libarchfpga/include/physical_types.h /^ float buf_size;$/;" m struct:s_switch_inf -buffer_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* buffer_info;$/;" m struct:s_spice_model_design_tech_info buffer_net ./place/timing_place_lookup.c /^static void buffer_net( float* cur_net_delay )$/;" f file: -buffer_size ../../libarchfpga/include/physical_types.h /^ float buffer_size; \/* if not autosized, the clock buffer size *\/$/;" m struct:s_clock_network -buffer_size ../../libarchfpga/include/physical_types.h /^ float buffer_size;$/;" m struct:s_pb_graph_pin_power -buffer_size ../../libarchfpga/include/physical_types.h /^ float buffer_size;$/;" m struct:s_port_power buffer_size_inf ./power/power.h /^ t_power_buffer_size_inf * buffer_size_inf;$/;" m struct:s_power_tech -buffer_type ../../libarchfpga/include/physical_types.h /^ e_power_buffer_type buffer_type;$/;" m struct:s_port_power -buffered ../../libarchfpga/include/physical_types.h /^ boolean buffered;$/;" m struct:s_switch_inf buffered ./base/vpr_types.h /^ int buffered;$/;" m struct:s_rr_node build_bidir_rr_opins ./route/rr_graph.c /^static void build_bidir_rr_opins(INP int i, INP int j,$/;" f file: build_default_menu ./base/graphics.c /^build_default_menu (void) $/;" f file: @@ -1774,74 +1139,35 @@ calc_buffer_stage_effort ./power/power_util.c /^float calc_buffer_stage_effort(i calculate_constraint ./timing/read_sdc.c /^static float calculate_constraint(t_sdc_clock source_domain, t_sdc_clock sink_domain) {$/;" f file: callibrate ./power/PowerSpicedComponent.c /^void PowerCallibInputs::callibrate() {$/;" f class:PowerCallibInputs callibrate ./power/PowerSpicedComponent.c /^void PowerSpicedComponent::callibrate(void) {$/;" f class:PowerSpicedComponent -callout_data ../../pcre/SRC/internal.h /^ void *callout_data; \/* To pass back to callouts *\/$/;" m struct:match_data -callout_data ../../pcre/SRC/pcre.h /^ void *callout_data; \/* Data passed in with the call *\/$/;" m struct:pcre_callout_block -callout_data ../../pcre/SRC/pcre.h /^ void *callout_data; \/* Data passed back in callouts *\/$/;" m struct:pcre_extra -callout_number ../../pcre/SRC/pcre.h /^ int callout_number; \/* Number compiled into pattern *\/$/;" m struct:pcre_callout_block cap ./timing/slre.c /^struct cap {$/;" s file: -cap_val ../../libarchfpga/fpga_spice_include/spice_types.h /^ float cap_val; $/;" m struct:s_spice_model_wire_param -capacitance ../../libarchfpga/include/physical_types.h /^ float capacitance;$/;" m struct:s_pb_graph_edge -capacity ../../libarchfpga/include/physical_types.h /^ int capacity;$/;" m struct:s_type_descriptor capacity ./base/vpr_types.h /^ float capacity;$/;" m struct:s_place_region capacity ./base/vpr_types.h /^ short capacity;$/;" m struct:s_rr_node -captab ../../libarchfpga/fpga_spice_include/spice_types.h /^ int captab;$/;" m struct:s_spice_params capture ./timing/slre.c /^static const char *capture(const struct cap *caps, int num_caps, va_list ap) {$/;" f file: capture_float ./timing/slre.c /^static const char *capture_float(const struct cap *cap, void *p, size_t len) {$/;" f file: capture_int ./timing/slre.c /^static const char *capture_int(const struct cap *cap, void *p, size_t len) {$/;" f file: -capture_last ../../pcre/SRC/internal.h /^ int capture_last; \/* Most recent capture number *\/$/;" m struct:match_data -capture_last ../../pcre/SRC/pcre.h /^ int capture_last; \/* Most recently closed capture *\/$/;" m struct:pcre_callout_block capture_string ./timing/slre.c /^static const char *capture_string(const struct cap *cap, void *p, size_t len) {$/;" f file: -capture_top ../../pcre/SRC/pcre.h /^ int capture_top; \/* Max current capture *\/$/;" m struct:pcre_callout_block casecmp ./timing/slre.c /^static int casecmp(const void *p1, const void *p2, size_t len) {$/;" f file: -cat_llists ../../libarchfpga/linkedlist.c /^t_llist* cat_llists(t_llist* head1,$/;" f category ./fpga_x2p/shell/shell_types.h /^ e_cmd_category category;$/;" m struct:s_shell_cmd -cb ../../libarchfpga/include/physical_types.h /^ boolean *cb;$/;" m struct:s_segment_inf cb ./base/vpr_types.h /^ boolean *cb;$/;" m struct:s_seg_details -cb_len ../../libarchfpga/include/physical_types.h /^ int cb_len;$/;" m struct:s_segment_inf -cb_switches ../../libarchfpga/include/physical_types.h /^ t_switch_inf* cb_switches;$/;" m struct:s_arch -cb_type_descriptors ../../libarchfpga/read_xml_arch_file.c /^static struct s_type_descriptor *cb_type_descriptors;$/;" v typeref:struct:s_type_descriptor file: -cbit_cntrl ../../pcre/SRC/internal.h 647;" d -cbit_digit ../../pcre/SRC/internal.h 640;" d -cbit_graph ../../pcre/SRC/internal.h 644;" d -cbit_length ../../pcre/SRC/internal.h 648;" d -cbit_lower ../../pcre/SRC/internal.h 642;" d -cbit_print ../../pcre/SRC/internal.h 645;" d -cbit_punct ../../pcre/SRC/internal.h 646;" d -cbit_space ../../pcre/SRC/internal.h 638;" d -cbit_upper ../../pcre/SRC/internal.h 641;" d -cbit_word ../../pcre/SRC/internal.h 643;" d -cbit_xdigit ../../pcre/SRC/internal.h 639;" d -cbits ../../pcre/SRC/internal.h /^ const uschar *cbits; \/* Points to character type table *\/$/;" m struct:compile_data -cbits_offset ../../pcre/SRC/internal.h 655;" d -cbx_index_high ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** cbx_index_high;$/;" m struct:s_spice_model -cbx_index_low ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** cbx_index_low;$/;" m struct:s_spice_model cbx_info ./base/globals.c /^t_cb** cbx_info = NULL;$/;" v cbx_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* cbx_spice_file_name_prefix = "cbx_";$/;" v cbx_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* cbx_verilog_file_name_prefix = "cbx_";$/;" v -cby_index_high ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** cby_index_high;$/;" m struct:s_spice_model -cby_index_low ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** cby_index_low;$/;" m struct:s_spice_model cby_info ./base/globals.c /^t_cb** cby_info = NULL;$/;" v cby_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* cby_spice_file_name_prefix = "cby_";$/;" v cby_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* cby_verilog_file_name_prefix = "cby_";$/;" v cc_constraints ./base/vpr_types.h /^ t_override_constraint * cc_constraints; \/* [0..num_cc_constraints - 1] array of such constraints *\/$/;" m struct:s_timing_constraints cf_constraints ./base/vpr_types.h /^ t_override_constraint * cf_constraints; \/* [0..num_cf_constraints - 1] array of such constraints *\/$/;" m struct:s_timing_constraints -chain_name ../../libarchfpga/include/physical_types.h /^ char *chain_name;$/;" m struct:s_port chain_pattern ./base/vpr_types.h /^ t_model_chain_pattern *chain_pattern; \/* If this is a chain molecule, chain that this molecule matches *\/$/;" m struct:s_pack_molecule -chain_root_pin ../../libarchfpga/include/cad_types.h /^ t_pb_graph_pin *chain_root_pin; \/* pointer to logic block input pin that drives this chain from the preceding logic block *\/ $/;" m struct:s_pack_patterns -chan_length ../../libarchfpga/fpga_spice_include/spice_types.h /^ float chan_length;$/;" m struct:s_spice_transistor_type chan_rr_node ./base/vpr_types.h /^ t_rr_node*** chan_rr_node;$/;" m struct:s_cb chan_rr_node ./base/vpr_types.h /^ t_rr_node*** chan_rr_node;$/;" m struct:s_sb chan_rr_node_direction ./base/vpr_types.h /^ enum PORTS** chan_rr_node_direction;$/;" m struct:s_cb typeref:enum:s_cb::PORTS chan_rr_node_direction ./base/vpr_types.h /^ enum PORTS** chan_rr_node_direction;$/;" m struct:s_sb typeref:enum:s_sb::PORTS chan_width ./base/vpr_types.h /^ int* chan_width;$/;" m struct:s_cb chan_width ./base/vpr_types.h /^ int* chan_width;$/;" m struct:s_sb -chan_width_io ../../libarchfpga/include/physical_types.h /^ float chan_width_io;$/;" m struct:s_chan_width_dist chan_width_x ./base/globals.c /^int *chan_width_x = NULL; \/* [0..ny] *\/$/;" v chan_width_x ./base/globals_declare.h /^int *chan_width_x, *chan_width_y; \/* numerical form *\/$/;" v chan_width_y ./base/globals.c /^int *chan_width_y = NULL; \/* [0..nx] *\/$/;" v chan_width_y ./base/globals_declare.h /^int *chan_width_x, *chan_width_y; \/* numerical form *\/$/;" v -chan_x_dist ../../libarchfpga/include/physical_types.h /^ t_chan chan_x_dist;$/;" m struct:s_chan_width_dist -chan_y_dist ../../libarchfpga/include/physical_types.h /^ t_chan chan_y_dist;$/;" m struct:s_chan_width_dist change_button_text ./base/graphics.c /^void change_button_text(const char *button_name, const char *new_button_text) {$/;" f change_button_text ./base/graphics.c /^void change_button_text(const char *button_text, const char *new_button_text) { }$/;" f channel_width ./power/power.h /^ int channel_width;$/;" m struct:s_solution_inf @@ -1868,9 +1194,7 @@ check_conflict_syntax_char_in_string ./fpga_x2p/base/fpga_x2p_setup.c /^int chec check_connections_to_global_clb_pins ./base/check_netlist.c /^static int check_connections_to_global_clb_pins(int inet) {$/;" f file: check_consistency_logical_block_net_num ./fpga_x2p/base/fpga_x2p_utils.c /^int check_consistency_logical_block_net_num(t_logical_block* lgk_blk, $/;" f check_des_blk_pin ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int check_des_blk_pin(int n_blks, t_block* blk,$/;" f -check_dptr_exist_in_llist ../../libarchfpga/linkedlist.c /^boolean check_dptr_exist_in_llist(t_llist* head, void* data_ptr) {$/;" f check_drive_rr_node_imply_short ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^boolean check_drive_rr_node_imply_short(t_sb cur_sb_info,$/;" f -check_escape ../../pcre/SRC/pcre.c /^check_escape(const uschar **ptrptr, const char **errorptr, int bracount,$/;" f file: check_ff_spice_model_ports ./fpga_x2p/base/fpga_x2p_utils.c /^void check_ff_spice_model_ports(t_spice_model* cur_spice_model,$/;" f check_fontsize ./base/graphics.c /^static int check_fontsize(int pointsize,$/;" f file: check_for_duplicated_names ./base/check_netlist.c /^static int check_for_duplicated_names(void) {$/;" f file: @@ -1891,8 +1215,6 @@ check_pb_graph_edge ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void check_pb_gra check_pb_graph_pin_edges ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void check_pb_graph_pin_edges(t_pb_graph_pin pb_graph_pin) {$/;" f check_pin_number_match_phy_pb_graph_pin ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^boolean check_pin_number_match_phy_pb_graph_pin(t_pb_graph_pin* cur_pb_graph_pin, $/;" f check_place ./place/place.c /^static void check_place(float bb_cost, float timing_cost, $/;" f file: -check_posix_name ../../pcre/SRC/pcre.c /^check_posix_name(const uschar *ptr, int len)$/;" f file: -check_posix_syntax ../../pcre/SRC/pcre.c /^check_posix_syntax(const uschar *ptr, const uschar **endptr, compile_data *cd)$/;" f file: check_primitives ./base/check_netlist.c /^static int check_primitives(int iblk, int isub) {$/;" f file: check_route ./route/check_route.c /^void check_route(enum e_route_type route_type, int num_switch,$/;" f check_rr_graph ./route/check_rr_graph.c /^void check_rr_graph(INP t_graph_type graph_type, INP t_type_ptr types,$/;" f @@ -1900,7 +1222,6 @@ check_sink ./route/check_route.c /^static void check_sink(int inode, int inet, b check_source ./route/check_route.c /^static void check_source(int inode, int inet) {$/;" f file: check_spice_model_name_conflict_syntax_char ./fpga_x2p/base/fpga_x2p_setup.c /^void check_spice_model_name_conflict_syntax_char(t_arch Arch,$/;" f file: check_spice_model_structure_match_switch_inf ./fpga_x2p/base/fpga_x2p_utils.c /^boolean check_spice_model_structure_match_switch_inf(t_switch_inf target_switch_inf) {$/;" f -check_spice_models ../../libarchfpga/read_xml_spice.c /^static void check_spice_models(int num_spice_model,$/;" f file: check_spice_models_grid_tb_cnt ./fpga_x2p/base/fpga_x2p_utils.c /^void check_spice_models_grid_tb_cnt(int num_spice_models,$/;" f check_sram_spice_model_ports ./fpga_x2p/base/fpga_x2p_utils.c /^void check_sram_spice_model_ports(t_spice_model* cur_spice_model,$/;" f check_src_blk_pin ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int check_src_blk_pin(int n_blks, t_block* blk,$/;" f @@ -1908,31 +1229,24 @@ check_subblock_internal_nets ./base/check_netlist.c /^static int check_subblock_ check_subblocks ./base/check_netlist.c /^static int check_subblocks(int iblk) {$/;" f file: check_subckt_file_exist_in_llist ./fpga_x2p/base/fpga_x2p_utils.c /^boolean check_subckt_file_exist_in_llist(t_llist* subckt_llist_head,$/;" f check_switch ./route/check_route.c /^static void check_switch(struct s_trace *tptr, int num_switch) {$/;" f file: -check_tech_lib ../../libarchfpga/read_xml_spice.c /^static void check_tech_lib(t_spice_tech_lib tech_lib, $/;" f file: check_timing_graph ./timing/path_delay2.c /^void check_timing_graph(int num_sinks) {$/;" f -child ../../libarchfpga/include/ezxml.h /^ ezxml_t child; \/* head of sub tag list, NULL if none *\/$/;" m struct:ezxml child ./route/route_tree_timing.h /^ struct s_rt_node *child;$/;" m struct:s_linked_rt_edge typeref:struct:s_linked_rt_edge::s_rt_node child ./timing/net_delay_types.h /^ struct s_rc_node *child;$/;" m struct:s_linked_rc_edge typeref:struct:s_linked_rc_edge::s_rc_node child_list ./route/route_tree_timing.h /^ t_linked_rt_edge *child_list;$/;" m union:s_rt_node::__anon16 child_list ./timing/net_delay_types.h /^ t_linked_rc_edge *child_list;$/;" m union:s_rc_node::__anon18 -child_pb_graph_nodes ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_node ***child_pb_graph_nodes; \/* [0..num_modes-1][0..num_pb_type_in_mode-1][0..num_pb-1] *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node child_pbs ./base/vpr_types.h /^ struct s_pb **child_pbs; \/* children pbs attached to this pb [0..num_child_pb_types - 1][0..child_type->num_pb - 1] *\/$/;" m struct:s_pb typeref:struct:s_pb::s_pb child_pbs ./fpga_x2p/base/fpga_x2p_types.h /^ t_phy_pb **child_pbs; \/* children pbs attached to this pb [0..num_child_pb_types - 1][0..child_type->num_pb - 1] *\/$/;" m struct:fpga_spice_phy_pb children ./power/power.h /^ t_mux_node * children; \/* Multiplexers that drive the inputs [0..num_inputs-1] *\/$/;" m struct:s_mux_node chomp_file_name_postfix ./fpga_x2p/base/fpga_x2p_utils.c /^char* chomp_file_name_postfix(char* file_name) {$/;" f chomp_spice_node_prefix ./fpga_x2p/base/fpga_x2p_utils.c /^char* chomp_spice_node_prefix(char* spice_node_prefix) {$/;" f -chomp_verilog_node_prefix ./fpga_x2p/verilog/verilog_utils.c /^char* chomp_verilog_node_prefix(char* verilog_node_prefix) {$/;" f -chunk_ptr_head ../../libarchfpga/include/util.h /^ struct s_linked_vptr *chunk_ptr_head; $/;" m struct:s_chunk typeref:struct:s_chunk::s_linked_vptr +chomp_verilog_prefix ./fpga_x2p/verilog/verilog_utils.c /^char* chomp_verilog_prefix(char* verilog_node_prefix) {$/;" f circuit_p_io_removed ./base/globals.c /^struct s_linked_vptr *circuit_p_io_removed = NULL;$/;" v typeref:struct:s_linked_vptr -class ../../pcre/SRC/pcre.c 58;" d file: -class_inf ../../libarchfpga/include/physical_types.h /^ struct s_class *class_inf; \/* [0..num_class-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_class -class_type ../../libarchfpga/include/physical_types.h /^ enum e_pb_type_class class_type;$/;" m struct:s_pb_type typeref:enum:s_pb_type::e_pb_type_class clay_logical_equivalence_handling ./base/vpr_api.c /^static void clay_logical_equivalence_handling(const t_arch *arch) {$/;" f file: clay_lut_input_rebalancing ./base/vpr_api.c /^static void clay_lut_input_rebalancing(int iblock, t_pb *pb) {$/;" f file: clay_reload_ble_locations ./base/vpr_api.c /^static void clay_reload_ble_locations(int iblock) {$/;" f file: clb2clb_direct ./base/globals.c /^t_clb_to_clb_directs* clb2clb_direct = NULL;$/;" v -clb_grid ../../libarchfpga/include/physical_types.h /^ struct s_clb_grid clb_grid;$/;" m struct:s_arch typeref:struct:s_arch::s_clb_grid clb_index ./base/vpr_types.h /^ int clb_index; \/* Complex block index that this logical block got mapped to *\/$/;" m struct:s_logical_block +clb_iteration ./fpga_x2p/verilog/verilog_formality_autodeck.c /^static void clb_iteration(FILE *fp, char* chomped_circuit_name, int h){$/;" f file: clb_net ./base/globals.c /^struct s_net *clb_net = NULL;$/;" v typeref:struct:s_net clb_net_density ./power/power_util.c /^float clb_net_density(int net_idx) {$/;" f clb_net_prob ./power/power_util.c /^float clb_net_prob(int net_idx) {$/;" f @@ -1941,41 +1255,27 @@ clb_to_vpack_net_mapping ./base/globals.c /^int *clb_to_vpack_net_mapping = NULL clear_buffer ./mrfpga/buffer_insertion.c /^void clear_buffer( )$/;" f clearscreen ./base/graphics.c /^clearscreen (void) $/;" f clearscreen ./base/graphics.c /^void clearscreen (void) { }$/;" f -clock ../../libarchfpga/include/physical_types.h /^ char * clock;$/;" m struct:s_pin_to_pin_annotation clock_delay ./base/vpr_types.h /^ float clock_delay; \/* The time taken for a clock signal to get to the flip-flop or I\/O (assumed 0 for I\/Os). *\/$/;" m struct:s_tnode clock_domain ./base/vpr_types.h /^ int clock_domain; \/* Index of the clock in g_sdc->constrained_clocks which this flip-flop or I\/O is constrained on. *\/$/;" m struct:s_tnode -clock_inf ../../libarchfpga/include/physical_types.h /^ t_clock_network *clock_inf; \/* Details about each clock *\/$/;" m struct:s_clock_arch clock_input_name ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^static char* clock_input_name = NULL;$/;" v file: clock_name ./base/vpr_types.h /^ char * clock_name; \/* Clock it was constrained on *\/$/;" m struct:s_io clock_names ./timing/read_sdc.c /^ char ** clock_names;$/;" m struct:s_sdc_exclusive_group file: clock_net ./base/vpr_types.h /^ int clock_net; \/* Clock net connected to this logical_block. *\/$/;" m struct:s_logical_block clock_net ./base/vpr_types.h /^ int clock_net; \/* Records clock net driving a flip-flop, valid only for lowest-level, flip-flop PBs *\/$/;" m struct:s_pb clock_net_tnode ./base/vpr_types.h /^ struct s_tnode *clock_net_tnode; \/* correspnding clock net tnode *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_tnode -clock_pins ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin **clock_pins; \/* [0..num_clock_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node -clock_slew_fall_time ../../libarchfpga/fpga_spice_include/spice_types.h /^ float clock_slew_fall_time; $/;" m struct:s_spice_stimulate_params -clock_slew_fall_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -clock_slew_rise_time ../../libarchfpga/fpga_spice_include/spice_types.h /^ float clock_slew_rise_time; $/;" m struct:s_spice_stimulate_params -clock_slew_rise_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -clocks ../../libarchfpga/include/physical_types.h /^ t_clock_arch * clocks;$/;" m struct:s_arch -close ../../libarchfpga/ezxml.c 61;" d file: close_graphics ./base/graphics.c /^close_graphics (void) $/;" f close_graphics ./base/graphics.c /^void close_graphics (void) { }$/;" f close_postscript ./base/graphics.c /^void close_postscript (void) $/;" f close_postscript ./base/graphics.c /^void close_postscript (void) { }$/;" f -cluster_placement_primitive ../../libarchfpga/include/physical_types.h /^ struct s_cluster_placement_primitive *cluster_placement_primitive; \/* pointer to indexing structure useful during packing stage *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_cluster_placement_primitive cluster_seed_type ./base/ReadOptions.h /^ enum e_cluster_seed cluster_seed_type;$/;" m struct:s_options typeref:enum:s_options::e_cluster_seed cluster_seed_type ./base/vpr_types.h /^ enum e_cluster_seed cluster_seed_type;$/;" m struct:s_packer_opts typeref:enum:s_packer_opts::e_cluster_seed cluster_size ./base/ReadOptions.h /^ int cluster_size;$/;" m struct:s_options cmd ./fpga_x2p/shell/shell_types.h /^ t_shell_cmd* cmd;$/;" m struct:s_shell_env cmd_category ./fpga_x2p/shell/shell_cmds.h /^t_cmd_category cmd_category[] = {$/;" v cmd_category ./fpga_x2p/shell/shell_types.h /^ t_cmd_category* cmd_category;$/;" m struct:s_shell_env -cmos_variation ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params cmos_variation;$/;" m struct:s_spice_mc_params -cnt ../../libarchfpga/fpga_spice_include/spice_types.h /^ int cnt; \/* Used in mux_testbench only*\/$/;" m struct:s_spice_mux_model -cnt ../../libarchfpga/fpga_spice_include/spice_types.h /^ int cnt;$/;" m struct:s_spice_model cnt ./fpga_x2p/verilog/verilog_report_timing.c /^ int cnt;$/;" m struct:s_wireL_cnt file: code ./timing/slre.c /^ unsigned char code[256];$/;" m struct:slre file: code_size ./timing/slre.c /^ int code_size;$/;" m struct:slre file: -col_rel ../../libarchfpga/include/physical_types.h /^ float col_rel;$/;" m struct:s_grid_loc_def color_types ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" g colors ./base/graphics.c /^static int colors[NUM_COLOR];$/;" v file: combine_buffer_plan ./mrfpga/buffer_insertion.c /^static t_buffer_plan combine_buffer_plan( t_buffer_plan slow_branch, t_buffer_plan* plan_whole, int num_whole, int num_pins )$/;" f file: @@ -1986,6 +1286,7 @@ comp_delta_td_cost ./place/place.c /^static void comp_delta_td_cost(float *delta comp_td_costs ./place/place.c /^static void comp_td_costs(float *timing_cost, float *connection_delay_sum) {$/;" f file: comp_td_point_to_point_delay ./place/place.c /^static float comp_td_point_to_point_delay(int inet, int ipin) {$/;" f file: comp_width ./base/place_and_route.c /^static float comp_width(t_chan * chan, float x, float separation) {$/;" f file: +compact_routing_hierarchy ./base/vpr_types.h /^ boolean compact_routing_hierarchy; \/* use compact routing hierarchy *\/$/;" m struct:s_fpga_spice_opts compact_verilog_get_grid_phy_block_subckt_name ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^char* compact_verilog_get_grid_phy_block_subckt_name(t_type_ptr grid_type_descriptor,$/;" f compact_verilog_update_grid_spice_model_and_sram_orgz_info ./fpga_x2p/verilog/verilog_compact_netlist.c /^void compact_verilog_update_grid_spice_model_and_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info,$/;" f file: compact_verilog_update_one_spice_model_grid_index ./fpga_x2p/verilog/verilog_compact_netlist.c /^void compact_verilog_update_one_spice_model_grid_index(t_type_ptr phy_block_type,$/;" f file: @@ -1994,10 +1295,6 @@ compare_molecule_gain ./pack/cluster.c /^static int compare_molecule_gain(const compare_pack_pattern ./pack/prepack.c /^static int compare_pack_pattern(const t_pack_patterns *pattern_a, const t_pack_patterns *pattern_b) {$/;" f file: compile ./timing/slre.c /^static void compile(struct slre *r, const char **re) {$/;" f file: compile2 ./timing/slre.c /^static const char *compile2(struct slre *r, const char *re) {$/;" f file: -compile_branch ../../pcre/SRC/pcre.c /^compile_branch(int *optionsptr, int *brackets, uschar **codeptr,$/;" f file: -compile_data ../../pcre/SRC/internal.h /^typedef struct compile_data {$/;" s -compile_data ../../pcre/SRC/internal.h /^} compile_data;$/;" t typeref:struct:compile_data -compile_regex ../../pcre/SRC/pcre.c /^compile_regex(int options, int oldims, int *brackets, uschar **codeptr,$/;" f file: complete_truth_table_line ./fpga_x2p/base/fpga_x2p_lut_utils.c /^char* complete_truth_table_line(int lut_size,$/;" f component_callibration ./power/power.h /^ PowerSpicedComponent ** component_callibration;$/;" m struct:s_power_commonly_used component_usage ./power/PowerSpicedComponent.h /^ float (*component_usage)(int num_inputs, float transistor_size);$/;" m class:PowerSpicedComponent @@ -2012,7 +1309,6 @@ compute_delta_clb_to_io ./place/timing_place_lookup.c /^static void compute_delt compute_delta_io_to_clb ./place/timing_place_lookup.c /^static void compute_delta_io_to_clb(struct s_router_opts router_opts,$/;" f file: compute_delta_io_to_io ./place/timing_place_lookup.c /^static void compute_delta_io_to_io(struct s_router_opts router_opts,$/;" f file: compute_primitive_base_cost ./util/vpr_utils.c /^float compute_primitive_base_cost(INP t_pb_graph_node *primitive) {$/;" f -conf_bit_head ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_llist* conf_bit_head; $/;" m struct:s_sram_orgz_info conf_bits_head ./fpga_x2p/verilog/verilog_global.c /^t_llist* conf_bits_head = NULL;$/;" v conf_bits_lsb ./base/vpr_types.h /^ int conf_bits_lsb; \/* LSB of configuration bits *\/$/;" m struct:s_cb conf_bits_lsb ./base/vpr_types.h /^ int conf_bits_lsb; \/* LSB of configuration bits *\/$/;" m struct:s_sb @@ -2032,8 +1328,6 @@ connect_pb_des_pin_to_src_pin ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^vo connection_driven ./base/ReadOptions.h /^ boolean connection_driven;$/;" m struct:s_options connection_driven ./base/vpr_types.h /^ boolean connection_driven;$/;" m struct:s_packer_opts connectiongain ./base/vpr_types.h /^ std::map connectiongain; \/* [0..num_logical_blocks-1] Weighted sum of connections to attraction function *\/$/;" m struct:s_pb_stats -connections ../../libarchfpga/include/cad_types.h /^ struct s_pack_pattern_connections *connections; \/* linked list of connections of logic blocks in pattern *\/$/;" m struct:s_pack_pattern_block typeref:struct:s_pack_pattern_block::s_pack_pattern_connections -const_input_val ../../libarchfpga/fpga_spice_include/spice_types.h /^ int const_input_val;$/;" m struct:s_spice_model_mux constant_net_delay ./base/ReadOptions.h /^ float constant_net_delay;$/;" m struct:s_options constant_net_delay ./base/vpr_types.h /^ float constant_net_delay; \/* timing information when place and route not run *\/$/;" m struct:s_vpr_setup constrain_cbs ./fpga_x2p/verilog/verilog_sdc.c /^ boolean constrain_cbs;$/;" m struct:s_sdc_opts file: @@ -2044,7 +1338,6 @@ constrained_clocks ./base/vpr_types.h /^ t_clock * constrained_clocks; \/* [0..g constrained_inputs ./base/vpr_types.h /^ t_io * constrained_inputs; \/* [0..num_constrained_inputs - 1] array of inputs with timing constraints *\/$/;" m struct:s_timing_constraints constrained_outputs ./base/vpr_types.h /^ t_io * constrained_outputs; \/* [0..num_constrained_outputs - 1] array of outputs with timing constraints *\/$/;" m struct:s_timing_constraints constraint ./base/vpr_types.h /^ float constraint;$/;" m struct:s_override_constraint -cont ../../libarchfpga/util.c /^static int cont; \/* line continued? *\/$/;" v file: convert_cb_type_to_string ./fpga_x2p/base/fpga_x2p_utils.c /^char* convert_cb_type_to_string(t_rr_type chan_type) {$/;" f convert_chan_rr_node_direction_to_string ./fpga_x2p/base/fpga_x2p_utils.c /^char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction) {$/;" f convert_chan_type_to_string ./fpga_x2p/base/fpga_x2p_utils.c /^char* convert_chan_type_to_string(t_rr_type chan_type) {$/;" f @@ -2057,13 +1350,12 @@ convert_spice_model_port_type_to_verilog_port_type ./fpga_x2p/verilog/verilog_ut copy_delay ./mrfpga/buffer_insertion.c /^static void copy_delay( float* base, float* source, t_linked_int* index )$/;" f file: copy_from_float_array ./mrfpga/buffer_insertion.c /^static float* copy_from_float_array( float* source, int num )$/;" f file: copy_from_list ./mrfpga/mrfpga_util.c /^t_linked_int* copy_from_list( t_linked_int* base, t_linked_int* target )$/;" f +copy_nb_clusters ./base/globals.c /^int copy_nb_clusters = 0;$/;" v copy_sram_orgz_info ./fpga_x2p/base/fpga_x2p_utils.c /^void copy_sram_orgz_info(t_sram_orgz_info* des_sram_orgz_info,$/;" f cost ./base/vpr_types.h /^ float cost;$/;" m struct:s_place_region cost ./route/route_common.h /^ float cost;$/;" m struct:s_heap cost_index ./base/vpr_types.h /^ short cost_index;$/;" m struct:s_rr_node cost_methods ./place/place.c /^enum cost_methods {$/;" g file: -could_be_empty ../../pcre/SRC/pcre.c /^could_be_empty(const uschar *code, const uschar *endcode, branch_chain *bcptr,$/;" f file: -could_be_empty_branch ../../pcre/SRC/pcre.c /^could_be_empty_branch(const uschar *code, const uschar *endcode, BOOL utf8)$/;" f file: count ./base/read_blif.c /^ int count;$/;" m struct:s_model_stats file: count ./util/hash.h /^ int count;$/;" m struct:s_hash count_bidir_routing_transistors ./route/rr_graph_area.c /^void count_bidir_routing_transistors(int num_switch, float R_minW_nmos,$/;" f @@ -2114,41 +1406,24 @@ cpt_subckt_name ./fpga_x2p/spice/spice_globals.c /^char* cpt_subckt_name = "cpt" create_button ./base/graphics.c /^void create_button (const char *prev_button_text , const char *button_text, $/;" f create_button ./base/graphics.c /^void create_button (const char *prev_button_text , const char *button_text,$/;" f create_dir_path ./fpga_x2p/base/fpga_x2p_utils.c /^int create_dir_path(char* dir_path) {$/;" f -create_llist ../../libarchfpga/linkedlist.c /^t_llist* create_llist(int len) {$/;" f create_wireL_report_timing_tcl_file_handler ./fpga_x2p/verilog/verilog_report_timing.c /^FILE* create_wireL_report_timing_tcl_file_handler(t_trpt_opts trpt_opts, $/;" f criticality_exp ./base/ReadOptions.h /^ float criticality_exp;$/;" m struct:s_options criticality_exp ./base/vpr_types.h /^ float criticality_exp;$/;" m struct:s_router_opts critindexarray ./pack/cluster.c /^static int *critindexarray = NULL;$/;" v file: cross_count ./place/place.c /^static const float cross_count[50] = { \/* [0..49] *\/1.0, 1.0, 1.0, 1.0828, 1.1536, 1.2206, 1.2823, 1.3385, 1.3991, 1.4493, 1.4974,$/;" v file: -ctype_digit ../../pcre/SRC/internal.h 630;" d -ctype_letter ../../pcre/SRC/internal.h 629;" d -ctype_meta ../../pcre/SRC/internal.h 633;" d -ctype_space ../../pcre/SRC/internal.h 628;" d -ctype_word ../../pcre/SRC/internal.h 632;" d -ctype_xdigit ../../pcre/SRC/internal.h 631;" d -ctypes ../../pcre/SRC/internal.h /^ const uschar *ctypes; \/* Points to table of type maps *\/$/;" m struct:compile_data -ctypes ../../pcre/SRC/internal.h /^ const uschar *ctypes; \/* Points to table of type maps *\/$/;" m struct:match_data -ctypes_offset ../../pcre/SRC/internal.h 656;" d -cur ../../libarchfpga/include/ezxml.h /^ ezxml_t cur; \/* current xml tree insertion point *\/$/;" m struct:ezxml_root curr_cluster_index ./pack/cluster_legality.c /^static int curr_cluster_index;$/;" v file: curr_molecule ./base/vpr_types.h /^ t_pack_molecule *curr_molecule; \/* current molecule being considered for packing *\/$/;" m struct:s_cluster_placement_stats -current ../../pcre/SRC/internal.h /^ uschar *current;$/;" m struct:branch_chain current_draw_mode ./base/graphics.c /^static e_draw_mode current_draw_mode;$/;" v file: current_gc ./base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: -current_position ../../pcre/SRC/pcre.h /^ int current_position; \/* Where we currently are *\/$/;" m struct:pcre_callout_block -current_random ../../libarchfpga/util.c /^static unsigned int current_random = 0;$/;" v file: currentcolor ./base/graphics.c /^static int currentcolor;$/;" v file: currentfontsize ./base/graphics.c /^static int currentfontsize;$/;" v file: currentlinestyle ./base/graphics.c /^static int currentlinestyle;$/;" v file: currentlinewidth ./base/graphics.c /^static int currentlinewidth;$/;" v file: cxClient ./base/graphics.c /^static int cxClient, cyClient;$/;" v file: cyClient ./base/graphics.c /^static int cxClient, cyClient;$/;" v file: -data ../../libarchfpga/include/util.h /^ int data;$/;" m struct:s_linked_int data ./timing/slre.c /^ unsigned char data[256];$/;" m struct:slre file: data ./util/token.h /^ char *data;$/;" m struct:s_token data_size ./timing/slre.c /^ int data_size;$/;" m struct:slre file: -data_vptr ../../libarchfpga/include/util.h /^ void *data_vptr;$/;" m struct:s_linked_vptr -dc ../../libarchfpga/include/physical_types.h /^ float dc;$/;" m struct:s_chan dealloc_mux_graph ./power/power.c /^static void dealloc_mux_graph(t_mux_node * node) {$/;" f file: dealloc_mux_graph_rec ./power/power.c /^static void dealloc_mux_graph_rec(t_mux_node * node) {$/;" f file: decode_and_add_sram_membank_conf_bit_to_llist ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^decode_and_add_sram_membank_conf_bit_to_llist(t_sram_orgz_info* cur_sram_orgz_info,$/;" f @@ -2165,10 +1440,6 @@ decode_tree_mux_sram_bits ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int* decode_tre def_clk_name ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^static char* def_clk_name = "clk";$/;" v file: default_lb_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_lb_dir_name = "lb\/";$/;" v default_message ./base/draw.c /^static char default_message[BUFSIZE]; \/* Default screen message on screen *\/$/;" v file: -default_mode_num_conf_bits ../../libarchfpga/include/physical_types.h /^ int default_mode_num_conf_bits;$/;" m struct:s_pb_type -default_mode_num_iopads ../../libarchfpga/include/physical_types.h /^ int default_mode_num_iopads;$/;" m struct:s_pb_type -default_mode_num_mode_bits ../../libarchfpga/include/physical_types.h /^ int default_mode_num_mode_bits;$/;" m struct:s_pb_type -default_mode_num_reserved_conf_bits ../../libarchfpga/include/physical_types.h /^ int default_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type default_modelsim_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_modelsim_dir_name = "msim_projects\/";$/;" v default_msim_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_msim_dir_name = "MSIM\/";$/;" v default_output_name ./base/globals.c /^char *default_output_name = NULL;$/;" v @@ -2182,27 +1453,17 @@ default_spice_dir_path ./fpga_x2p/spice/spice_api.c /^static char* default_spice default_src_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_src_dir_name = "SRC\/";$/;" v default_submodule_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_submodule_dir_name = "sub_module\/";$/;" v default_tcl_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_tcl_dir_name = "SCRIPTS\/";$/;" v -default_val ../../libarchfpga/fpga_spice_include/spice_types.h /^ int default_val;$/;" m struct:s_spice_model_port default_verilog_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_verilog_dir_name = "syn_verilogs\/";$/;" v -define_idle_mode ../../libarchfpga/include/physical_types.h /^ int define_idle_mode; $/;" m struct:s_mode -define_physical_mode ../../libarchfpga/include/physical_types.h /^ int define_physical_mode; $/;" m struct:s_mode defines_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* defines_verilog_file_name = "fpga_defines.v";$/;" v defines_verilog_simulation_file_name ./fpga_x2p/verilog/verilog_global.c /^char* defines_verilog_simulation_file_name = "define_simulation.v";$/;" v delay ./base/vpr_types.h /^ float delay; \/* Delay through the I\/O in this constraint *\/$/;" m struct:s_io -delay_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_delay_info* delay_info;$/;" m struct:s_spice_model -delay_max ../../libarchfpga/include/physical_types.h /^ float delay_max;$/;" m struct:s_pb_graph_edge -delay_min ../../libarchfpga/include/physical_types.h /^ float delay_min;$/;" m struct:s_pb_graph_edge delayless_switch ./base/vpr_types.h /^ short delayless_switch;$/;" m struct:s_det_routing_arch delayless_switch_index ./fpga_x2p/base/fpga_x2p_types.h /^ int delayless_switch_index;$/;" m struct:fpga_spice_rr_graph -delete_in_vptr_list ../../libarchfpga/util.c /^delete_in_vptr_list(struct s_linked_vptr *head) {$/;" f delta_clb_to_clb ./place/timing_place_lookup.c /^float **delta_clb_to_clb;$/;" v delta_clb_to_io ./place/timing_place_lookup.c /^float **delta_clb_to_io;$/;" v delta_io_to_clb ./place/timing_place_lookup.c /^float **delta_io_to_clb;$/;" v delta_io_to_io ./place/timing_place_lookup.c /^float **delta_io_to_io;$/;" v -dens ../../libarchfpga/include/physical_types.h /^ float dens; \/* Switching density of net assigned to this clock *\/$/;" m struct:s_clock_network -density ../../libarchfpga/fpga_spice_include/spice_types.h /^ float density;$/;" m struct:s_spice_net_info density ./base/vpr_types.h /^ float density;$/;" m struct:s_net_power -depth ../../libarchfpga/include/physical_types.h /^ int depth; \/* depth of pb_type *\/$/;" m struct:s_pb_type description ./fpga_x2p/shell/read_opt_types.h /^ char* description;$/;" m struct:s_opt_info deselect_all ./base/draw.c /^static void deselect_all(void) {$/;" f file: design_param_header_file_name ./fpga_x2p/spice/spice_globals.c /^char* design_param_header_file_name = "design_params.sp";$/;" v @@ -2218,8 +1479,6 @@ design_param_postfix_rram_wprog_set_nmos ./fpga_x2p/spice/spice_globals.c /^char design_param_postfix_rram_wprog_set_pmos ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_rram_wprog_set_pmos = "_rram_wprog_set_pmos"; $/;" v design_param_postfix_wire_param_cap_val ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_wire_param_cap_val = "_wire_param_cap_val"; $/;" v design_param_postfix_wire_param_res_val ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_wire_param_res_val = "_wire_param_res_val"; $/;" v -design_tech ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_design_tech design_tech;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_design_tech -design_tech_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_design_tech_info design_tech_info;$/;" m struct:s_spice_model destroy_button ./base/graphics.c /^destroy_button (const char *button_text) $/;" f destroy_button ./base/graphics.c /^void destroy_button (const char *button_text) { }$/;" f determine_actual_pb_interc_type ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^enum e_interconnect determine_actual_pb_interc_type(t_interconnect* def_interc, $/;" f @@ -2235,14 +1494,11 @@ determine_sb_port_coordinator ./fpga_x2p/base/fpga_x2p_utils.c /^void determine_ determine_tree_mux_level ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int determine_tree_mux_level(int mux_size) {$/;" f determine_verilog_generic_port_split_sign ./fpga_x2p/verilog/verilog_utils.c /^char determine_verilog_generic_port_split_sign(enum e_dump_verilog_port_type dump_port_type) {$/;" f diff_sram_orgz_info ./fpga_x2p/base/fpga_x2p_utils.c /^t_sram_orgz_info* diff_sram_orgz_info(t_sram_orgz_info* des_sram_orgz_info, $/;" f -dir ../../libarchfpga/include/logic_types.h /^ enum PORTS dir; \/* port direction *\/$/;" m struct:s_model_ports typeref:enum:s_model_ports::PORTS direction ./base/vpr_types.h /^ enum e_direction direction; \/* UDSD by AY *\/$/;" m struct:s_rr_node typeref:enum:s_rr_node::e_direction direction ./base/vpr_types.h /^ enum e_direction direction; \/* UDSD by AY *\/$/;" m struct:s_seg_details typeref:enum:s_seg_details::e_direction -directionality ../../libarchfpga/include/physical_types.h /^ enum e_directionality directionality;$/;" m struct:s_segment_inf typeref:enum:s_segment_inf::e_directionality directionality ./base/vpr_types.h /^ enum e_directionality directionality; \/* UDSD by AY *\/$/;" m struct:s_det_routing_arch typeref:enum:s_det_routing_arch::e_directionality directionality ./base/vpr_types.h /^ enum e_directionality directionality; \/* UDSD by AY *\/$/;" m struct:s_cb typeref:enum:s_cb::e_directionality directionality ./base/vpr_types.h /^ enum e_directionality directionality; \/* UDSD by AY *\/$/;" m struct:s_sb typeref:enum:s_sb::e_directionality -disabled_in_packing ../../libarchfpga/include/physical_types.h /^ boolean disabled_in_packing;$/;" m struct:s_mode discover_all_forced_connections ./pack/cluster_feasibility_filter.c /^static void discover_all_forced_connections(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f file: discover_pattern_names_in_pb_graph_node ./pack/prepack.c /^static void discover_pattern_names_in_pb_graph_node($/;" f file: disp_type ./base/graphics.c /^ int disp_type;$/;" m struct:__anon5 file: @@ -2268,7 +1524,6 @@ do_timing_analysis_for_constraint ./timing/path_delay.c /^static float do_timing domain_constraint ./base/vpr_types.h /^ float ** domain_constraint; \/* [0..num_constrained_clocks - 1 (source)][0..num_constrained_clocks - 1 (destination)] *\/$/;" m struct:s_timing_constraints done_callibration ./power/PowerSpicedComponent.h /^ bool done_callibration;$/;" m class:PowerCallibInputs done_callibration ./power/PowerSpicedComponent.h /^ bool done_callibration;$/;" m class:PowerSpicedComponent -dptr ../../libarchfpga/fpga_spice_include/linkedlist.h /^ void* dptr;$/;" m struct:s_llist draw_chanx_to_chanx_edge ./base/draw.c /^static void draw_chanx_to_chanx_edge(int from_node, int from_track, int to_node,$/;" f file: draw_chanx_to_chany_edge ./base/draw.c /^static void draw_chanx_to_chany_edge(int chanx_node, int chanx_track,$/;" f file: draw_chany_to_chany_edge ./base/draw.c /^static void draw_chany_to_chany_edge(int from_node, int from_track, int to_node,$/;" f file: @@ -2313,9 +1568,7 @@ drawtoscreen ./base/graphics.c /^void drawtoscreen(void) {$/;" f drive_rr_nodes ./base/vpr_types.h /^ t_rr_node** drive_rr_nodes;$/;" m struct:s_rr_node drive_switches ./base/vpr_types.h /^ int* drive_switches;$/;" m struct:s_rr_node driver_pb ./base/verilog_writer.h /^ t_pb *driver_pb;$/;" m struct:found_connectivity -driver_pin ../../libarchfpga/include/physical_types.h /^ int driver_pin;$/;" m struct:s_pb_graph_edge driver_pin ./base/verilog_writer.h /^ t_pb_graph_pin *driver_pin;$/;" m struct:found_connectivity -driver_set ../../libarchfpga/include/physical_types.h /^ int driver_set;$/;" m struct:s_pb_graph_edge driver_switch ./base/vpr_types.h /^ short driver_switch; \/* Xifan TANG: Switch Segment Pattern Support*\/$/;" m struct:s_rr_node driver_switch_type ./power/power.h /^ short driver_switch_type; \/* Switch type that drives this resource *\/$/;" m struct:s_rr_node_power driver_to_load_delay ./base/verilog_writer.h /^ float driver_to_load_delay;$/;" m struct:found_connectivity @@ -2332,7 +1585,6 @@ dump_compact_verilog_logic_blocks ./fpga_x2p/verilog/verilog_compact_netlist.c / dump_compact_verilog_one_physical_block ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: dump_compact_verilog_top_netlist ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,$/;" f dump_conf_bits_to_bitstream_file ./fpga_x2p/bitstream/fpga_bitstream.c /^void dump_conf_bits_to_bitstream_file(FILE* fp, $/;" f file: -dump_explicit_port_map ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean dump_explicit_port_map;$/;" m struct:s_spice_model dump_fpga_spice_bitstream ./fpga_x2p/bitstream/fpga_bitstream.c /^void dump_fpga_spice_bitstream(char* bitstream_file_name, $/;" f dump_include_user_defined_verilog_netlists ./fpga_x2p/verilog/verilog_utils.c /^void dump_include_user_defined_verilog_netlists(FILE* fp,$/;" f dump_one_verilog_template_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_one_verilog_template_module(FILE* fp,$/;" f @@ -2347,7 +1599,6 @@ dump_sdc_physical_blocks ./fpga_x2p/verilog/verilog_sdc_pb_types.c /^void dump_s dump_sdc_rec_one_pb_muxes ./fpga_x2p/verilog/verilog_sdc.c /^void dump_sdc_rec_one_pb_muxes(FILE* fp,$/;" f dump_seg_details ./route/rr_graph2.c /^void dump_seg_details(t_seg_details * seg_details, int nodes_per_chan,$/;" f dump_simulation_preproc ./fpga_x2p/verilog/verilog_utils.c /^void dump_simulation_preproc(FILE* fp, $/;" f -dump_structural_verilog ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean dump_structural_verilog;$/;" m struct:s_spice_model dump_syn_verilog ./base/vpr_types.h /^ boolean dump_syn_verilog;$/;" m struct:s_syn_verilog_opts dump_verilog_autocheck_top_testbench ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,$/;" f dump_verilog_clb2clb_directs ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_clb2clb_directs(FILE* fp, $/;" f @@ -2527,9 +1778,6 @@ dump_verilog_top_testbench_wire_one_global_port_stimuli ./fpga_x2p/verilog/veril dump_verilog_toplevel_one_grid_side_pin_with_given_index ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_toplevel_one_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, $/;" f dump_verilog_wire_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_wire_module(FILE* fp,$/;" f dumped_num_conf_bits ./fpga_x2p/bitstream/fpga_bitstream.c /^static int dumped_num_conf_bits = 0;$/;" v file: -dynamic ../../libarchfpga/include/physical_types.h /^ float dynamic;$/;" m struct:s_power_usage -e ../../libarchfpga/include/ezxml.h /^ char *e; \/* end of work area *\/$/;" m struct:ezxml_root -e_Fc_type ../../libarchfpga/include/physical_types.h /^enum e_Fc_type {$/;" g e_OptionArgToken ./base/OptionTokens.h /^enum e_OptionArgToken {$/;" g e_OptionBaseToken ./base/OptionTokens.h /^enum e_OptionBaseToken {$/;" g e_base_cost_type ./base/vpr_types.h /^enum e_base_cost_type {$/;" g @@ -2540,7 +1788,6 @@ e_cost_indices ./base/vpr_types.h /^enum e_cost_indices {$/;" g e_detailed_routing_stages ./pack/cluster.c /^enum e_detailed_routing_stages {$/;" g file: e_dir_err ./fpga_x2p/base/fpga_x2p_utils.c /^enum e_dir_err {$/;" g file: e_direction ./base/vpr_types.h /^enum e_direction {$/;" g -e_directionality ../../libarchfpga/include/physical_types.h /^enum e_directionality {$/;" g e_draw_mode ./base/graphics.h /^enum e_draw_mode {DRAW_NORMAL = 0, DRAW_XOR};$/;" g e_draw_net_type ./base/draw.c /^enum e_draw_net_type {$/;" g file: e_draw_rr_toggle ./base/draw.c /^enum e_draw_rr_toggle {$/;" g file: @@ -2552,8 +1799,6 @@ e_feasibility ./pack/cluster.c /^enum e_feasibility {$/;" g file: e_gain_type ./pack/cluster.c /^enum e_gain_type {$/;" g file: e_gain_update ./pack/cluster.c /^enum e_gain_update {$/;" g file: e_graph_type ./route/rr_graph.h /^enum e_graph_type {$/;" g -e_grid_loc_type ../../libarchfpga/include/physical_types.h /^enum e_grid_loc_type {$/;" g -e_interconnect ../../libarchfpga/include/physical_types.h /^enum e_interconnect {$/;" g e_measure_type ./fpga_x2p/spice/spice_utils.h /^enum e_measure_type {$/;" g e_net_relation_to_clustered_block ./pack/cluster.c /^enum e_net_relation_to_clustered_block {$/;" g file: e_operation ./base/vpr_types.h /^enum e_operation {$/;" g @@ -2561,56 +1806,20 @@ e_output_files ./base/ReadOptions.h /^enum e_output_files {$/;" g e_pack_pattern_molecule_type ./base/vpr_types.h /^enum e_pack_pattern_molecule_type {$/;" g e_packer_algorithm ./base/vpr_types.h /^enum e_packer_algorithm {$/;" g e_pad_loc_type ./base/vpr_types.h /^enum e_pad_loc_type {$/;" g -e_pb_graph_pin_type ../../libarchfpga/include/physical_types.h /^enum e_pb_graph_pin_type {$/;" g -e_pb_type_class ../../libarchfpga/include/physical_types.h /^enum e_pb_type_class {$/;" g -e_pin_location_distr ../../libarchfpga/include/physical_types.h /^enum e_pin_location_distr {$/;" g -e_pin_to_pin_annotation_format ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_annotation_format {$/;" g -e_pin_to_pin_annotation_type ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_annotation_type {$/;" g -e_pin_to_pin_capacitance_annotations ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_capacitance_annotations {$/;" g -e_pin_to_pin_delay_annotations ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_delay_annotations {$/;" g -e_pin_to_pin_mode_select_annotations ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_mode_select_annotations {$/;" g -e_pin_to_pin_pack_pattern_annotations ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_pack_pattern_annotations {$/;" g -e_pin_type ../../libarchfpga/include/physical_types.h /^enum e_pin_type {$/;" g e_place_algorithm ./base/vpr_types.h /^enum e_place_algorithm {$/;" g e_power_breakdown_entry_type ./power/power.c /^} e_power_breakdown_entry_type;$/;" t typeref:enum:__anon8 file: -e_power_buffer_type ../../libarchfpga/include/physical_types.h /^} e_power_buffer_type;$/;" t typeref:enum:__anon21 e_power_callib_component ./power/power_callibrate.h /^} e_power_callib_component;$/;" t typeref:enum:__anon12 e_power_component_type ./power/power_components.h /^} e_power_component_type;$/;" t typeref:enum:__anon13 -e_power_estimation_method ../../libarchfpga/include/physical_types.h /^typedef enum e_power_estimation_method_ e_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ -e_power_estimation_method_ ../../libarchfpga/include/physical_types.h /^enum e_power_estimation_method_ {$/;" g e_power_log_type ./power/power.h /^} e_power_log_type;$/;" t typeref:enum:__anon10 e_power_ret_code ./power/power.h /^} e_power_ret_code;$/;" t typeref:enum:__anon9 -e_power_wire_type ../../libarchfpga/include/physical_types.h /^} e_power_wire_type;$/;" t typeref:enum:__anon20 -e_process_corner ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_process_corner {$/;" g e_removal_policy ./pack/cluster.c /^enum e_removal_policy {$/;" g file: e_route_type ./base/vpr_types.h /^enum e_route_type {$/;" g e_router_algorithm ./base/vpr_types.h /^enum e_router_algorithm {$/;" g e_rr_type ./base/vpr_types.h /^typedef enum e_rr_type {$/;" g -e_side ../../libarchfpga/include/physical_types.h /^enum e_side {$/;" g -e_spice_accuracy_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_accuracy_type {$/;" g -e_spice_ff_trigger_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_ff_trigger_type {$/;" g -e_spice_model_buffer_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_buffer_type {$/;" g -e_spice_model_design_tech ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_design_tech {$/;" g -e_spice_model_gate_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_gate_type {$/;" g -e_spice_model_pass_gate_logic_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_pass_gate_logic_type {$/;" g -e_spice_model_port_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_port_type {$/;" g -e_spice_model_structure ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_structure {$/;" g -e_spice_model_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_type {$/;" g -e_spice_pb_port_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_pb_port_type {$/;" g -e_spice_pin2pin_interc_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_pin2pin_interc_type {$/;" g -e_spice_tb_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_tb_type {$/;" g -e_spice_tech_lib_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_tech_lib_type {$/;" g -e_spice_trans_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_trans_type {$/;" g -e_sram_orgz ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_sram_orgz {$/;" g -e_stat ../../libarchfpga/include/physical_types.h /^enum e_stat {$/;" g -e_switch_block_type ../../libarchfpga/include/physical_types.h /^enum e_switch_block_type {$/;" g -e_swseg_pattern_type ../../libarchfpga/include/physical_types.h /^enum e_swseg_pattern_type {$/;" g -e_tech_comp ../../libarchfpga/include/arch_types_mrfpga.h /^enum e_tech_comp { $/;" g e_tnode_type ./base/vpr_types.h /^} e_tnode_type;$/;" t typeref:enum:__anon7 e_token_type ./util/token.h /^enum e_token_type {$/;" g e_tx_type ./power/power.h /^} e_tx_type;$/;" t typeref:enum:__anon11 e_verilog_tb_type ./fpga_x2p/verilog/verilog_global.h /^enum e_verilog_tb_type {$/;" g -e_wire_model_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_wire_model_type {$/;" g echoFileEnabled ./base/ReadOptions.c /^static boolean *echoFileEnabled = NULL;$/;" v file: echoFileNames ./base/ReadOptions.c /^static char **echoFileNames = NULL;$/;" v file: echo_input ./base/read_blif.c /^void echo_input(char *blif_file, char *echo_file, t_model *library_models) {$/;" f @@ -2628,35 +1837,22 @@ enable_or_disable_button ./base/graphics.c /^void enable_or_disable_button(int i enable_timing_computations ./base/vpr_types.h /^ boolean enable_timing_computations;$/;" m struct:s_placer_opts enabled ./base/graphics.c /^ bool enabled;$/;" m struct:__anon4 file: encode_decoder_addr ./fpga_x2p/bitstream/fpga_bitstream.c /^void encode_decoder_addr(int input,$/;" f -end_match_ptr ../../pcre/SRC/internal.h /^ const uschar *end_match_ptr; \/* Subject position at end match *\/$/;" m struct:match_data -end_offset_top ../../pcre/SRC/internal.h /^ int end_offset_top; \/* Highwater mark at end of match *\/$/;" m struct:match_data -end_subject ../../pcre/SRC/internal.h /^ const uschar *end_subject; \/* End of the subject string *\/$/;" m struct:match_data endlines ./base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: -endonly ../../pcre/SRC/internal.h /^ BOOL endonly; \/* Dollar not before final \\n *\/$/;" m struct:match_data -energy_per_toggle ../../libarchfpga/include/physical_types.h /^ float energy_per_toggle;$/;" m struct:s_port_power -ent ../../libarchfpga/include/ezxml.h /^ char **ent; \/* general entities (ampersand sequences) *\/$/;" m struct:ezxml_root entries ./power/PowerSpicedComponent.h /^ std::vector entries;$/;" m class:PowerSpicedComponent entries ./power/PowerSpicedComponent.h /^ std::vector entries;$/;" m class:PowerCallibInputs -eptrblock ../../pcre/SRC/pcre.c /^typedef struct eptrblock {$/;" s file: -eptrblock ../../pcre/SRC/pcre.c /^} eptrblock;$/;" t typeref:struct:eptrblock file: -equivalent ../../libarchfpga/include/physical_types.h /^ boolean equivalent;$/;" m struct:s_port -err ../../libarchfpga/include/ezxml.h /^ char err[EZXML_ERRL]; \/* error string *\/$/;" m struct:ezxml_root error_no_match ./timing/slre.c /^static const char *error_no_match = "No match";$/;" v file: error_string ./timing/slre.c /^ const char *error_string; \/\/ Error string$/;" m struct:slre file: -escapes ../../pcre/SRC/pcre.c /^static const short int escapes[] = {$/;" v file: essentials_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* essentials_verilog_file_name = "inv_buf_passgate.v";$/;" v esti_distance_num_seg_delay ./fpga_x2p/clb_pin_remap/post_place_timing.c /^float esti_distance_num_seg_delay(int distance,$/;" f esti_one_segment_net_delay ./fpga_x2p/clb_pin_remap/post_place_timing.c /^float esti_one_segment_net_delay(int distance, t_segment_inf segment_inf) {$/;" f esti_pin2pin_one_net_delay ./fpga_x2p/clb_pin_remap/post_place_timing.c /^float esti_pin2pin_one_net_delay(t_block src_blk,$/;" f esti_pin_chan_coordinate ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^void esti_pin_chan_coordinate(int* pin_x, int* pin_y,$/;" f estimate_post_place_one_net_sink_delay ./fpga_x2p/clb_pin_remap/post_place_timing.c /^float estimate_post_place_one_net_sink_delay(int net_index, $/;" f -estimation_method ../../libarchfpga/include/physical_types.h /^ e_power_estimation_method estimation_method;$/;" m struct:s_pb_type_power event_loop ./base/graphics.c /^event_loop (void (*act_on_mousebutton)(float x, float y), $/;" f event_loop ./base/graphics.c /^void event_loop (void (*act_on_mousebutton) (float x, float y),$/;" f exact ./timing/slre.c /^static void exact(struct slre *r, const char **re) {$/;" f file: exact_one_char ./timing/slre.c /^static void exact_one_char(struct slre *r, int ch) {$/;" f file: execute ./fpga_x2p/shell/shell_types.h /^ void (*execute)(t_shell_env*, t_opt_info*);$/;" m struct:s_shell_cmd -exist ../../libarchfpga/fpga_spice_include/spice_types.h /^ int exist;$/;" m struct:s_spice_model_buffer exists_free_primitive_for_logical_block ./pack/cluster_placement.c /^boolean exists_free_primitive_for_logical_block($/;" f exit_crit ./place/place.c /^static int exit_crit(float t, float cost,$/;" f file: exit_opts ./fpga_x2p/shell/cmd_exit.h /^t_opt_info exit_opts[] = {$/;" v @@ -2670,82 +1866,29 @@ expected_lowest_cost_primitive ./base/vpr_types.h /^ t_pb_graph_node *expected_l ext_clock_rr_node_index ./pack/cluster_legality.c /^ ext_clock_rr_node_index, max_ext_index;$/;" v file: ext_input_rr_node_index ./pack/cluster_legality.c /^static int ext_input_rr_node_index, ext_output_rr_node_index,$/;" v file: ext_output_rr_node_index ./pack/cluster_legality.c /^static int ext_input_rr_node_index, ext_output_rr_node_index,$/;" v file: -ezxml ../../libarchfpga/include/ezxml.h /^struct ezxml {$/;" s -ezxml_add_child ../../libarchfpga/ezxml.c /^ezxml_t ezxml_add_child(ezxml_t xml, char *name, size_t off) {$/;" f -ezxml_add_child_d ../../libarchfpga/include/ezxml.h 149;" d -ezxml_ampencode ../../libarchfpga/ezxml.c /^ezxml_ampencode(const char *s, size_t len, char **dst, size_t * dlen,$/;" f file: -ezxml_attr ../../libarchfpga/ezxml.c /^ezxml_attr(ezxml_t xml, const char *attr) {$/;" f -ezxml_char_content ../../libarchfpga/ezxml.c /^static void ezxml_char_content(ezxml_root_t root, char *s,$/;" f file: -ezxml_child ../../libarchfpga/ezxml.c /^ezxml_t ezxml_child(ezxml_t xml, const char *name) {$/;" f -ezxml_close_tag ../../libarchfpga/ezxml.c /^static ezxml_t ezxml_close_tag(ezxml_root_t root, char *name, char *s) {$/;" f file: -ezxml_cut ../../libarchfpga/ezxml.c /^ezxml_t ezxml_cut(ezxml_t xml) {$/;" f -ezxml_decode ../../libarchfpga/ezxml.c /^ezxml_decode(char *s, char **ent, char t) {$/;" f file: -ezxml_ent_ok ../../libarchfpga/ezxml.c /^static int ezxml_ent_ok(char *name, char *s, char **ent) {$/;" f file: -ezxml_err ../../libarchfpga/ezxml.c /^static ezxml_t ezxml_err(ezxml_root_t root, char *s, const char *err, ...) {$/;" f file: -ezxml_error ../../libarchfpga/ezxml.c /^ezxml_error(ezxml_t xml) {$/;" f -ezxml_free ../../libarchfpga/ezxml.c /^void ezxml_free(ezxml_t xml) {$/;" f -ezxml_free_attr ../../libarchfpga/ezxml.c /^static void ezxml_free_attr(char **attr) {$/;" f file: -ezxml_get ../../libarchfpga/ezxml.c /^ezxml_t ezxml_get(ezxml_t xml, ...) {$/;" f -ezxml_idx ../../libarchfpga/ezxml.c /^ezxml_t ezxml_idx(ezxml_t xml, int idx) {$/;" f -ezxml_insert ../../libarchfpga/ezxml.c /^ezxml_t ezxml_insert(ezxml_t xml, ezxml_t dest, size_t off) {$/;" f -ezxml_internal_dtd ../../libarchfpga/ezxml.c /^static short ezxml_internal_dtd(ezxml_root_t root, char *s,$/;" f file: -ezxml_move ../../libarchfpga/include/ezxml.h 178;" d -ezxml_name ../../libarchfpga/include/ezxml.h 108;" d -ezxml_new ../../libarchfpga/ezxml.c /^ezxml_t ezxml_new(char *name) {$/;" f -ezxml_new_d ../../libarchfpga/include/ezxml.h 142;" d -ezxml_next ../../libarchfpga/include/ezxml.h 101;" d -ezxml_open_tag ../../libarchfpga/ezxml.c /^static void ezxml_open_tag(ezxml_root_t root, int line, char *name, char **attr) {$/;" f file: -ezxml_parse_fd ../../libarchfpga/ezxml.c /^ezxml_t ezxml_parse_fd(int fd) {$/;" f -ezxml_parse_file ../../libarchfpga/ezxml.c /^ezxml_t ezxml_parse_file(const char *file) {$/;" f -ezxml_parse_fp ../../libarchfpga/ezxml.c /^ezxml_t ezxml_parse_fp(FILE * fp) {$/;" f -ezxml_parse_str ../../libarchfpga/ezxml.c /^ezxml_t ezxml_parse_str(char *s, size_t len) {$/;" f -ezxml_pi ../../libarchfpga/ezxml.c /^ezxml_pi(ezxml_t xml, const char *target) {$/;" f -ezxml_proc_inst ../../libarchfpga/ezxml.c /^static void ezxml_proc_inst(ezxml_root_t root, char *s, size_t len) {$/;" f file: -ezxml_remove ../../libarchfpga/include/ezxml.h 181;" d -ezxml_root ../../libarchfpga/include/ezxml.h /^struct ezxml_root { \/* additional data for the root tag *\/$/;" s -ezxml_root_t ../../libarchfpga/include/ezxml.h /^typedef struct ezxml_root *ezxml_root_t;$/;" t typeref:struct:ezxml_root -ezxml_set_attr ../../libarchfpga/ezxml.c /^ezxml_t ezxml_set_attr(ezxml_t xml, char *name, char *value) {$/;" f -ezxml_set_attr_d ../../libarchfpga/include/ezxml.h 164;" d -ezxml_set_flag ../../libarchfpga/ezxml.c /^ezxml_t ezxml_set_flag(ezxml_t xml, short flag) {$/;" f -ezxml_set_txt ../../libarchfpga/ezxml.c /^ezxml_t ezxml_set_txt(ezxml_t xml, char *txt) {$/;" f -ezxml_set_txt_d ../../libarchfpga/include/ezxml.h 156;" d -ezxml_str2utf8 ../../libarchfpga/ezxml.c /^ezxml_str2utf8(char **s, size_t * len) {$/;" f file: -ezxml_t ../../libarchfpga/include/ezxml.h /^typedef struct ezxml *ezxml_t;$/;" t typeref:struct:ezxml -ezxml_toxml ../../libarchfpga/ezxml.c /^ezxml_toxml(ezxml_t xml) {$/;" f -ezxml_toxml_r ../../libarchfpga/ezxml.c /^ezxml_toxml_r(ezxml_t xml, char **s, size_t * len, size_t * max, size_t start,$/;" f file: -ezxml_txt ../../libarchfpga/include/ezxml.h 111;" d -ezxml_vget ../../libarchfpga/ezxml.c /^ezxml_t ezxml_vget(ezxml_t xml, va_list ap) {$/;" f f_blk_pin_from_port_pin ./util/vpr_utils.c /^static int *** f_blk_pin_from_port_pin = NULL;$/;" v file: f_direct_type_from_blk_pin ./place/place_macro.c /^static int ** f_direct_type_from_blk_pin = NULL;$/;" v file: f_idirect_from_blk_pin ./place/place_macro.c /^static int ** f_idirect_from_blk_pin = NULL;$/;" v file: f_imacro_from_iblk ./place/place_macro.c /^static int * f_imacro_from_iblk = NULL;$/;" v file: f_net_to_driver_tnode ./timing/path_delay.c /^static int * f_net_to_driver_tnode; $/;" v file: -f_per_stage ../../libarchfpga/fpga_spice_include/spice_types.h /^ int f_per_stage;$/;" m struct:s_spice_model_buffer f_port_from_blk_pin ./util/vpr_utils.c /^static int ** f_port_from_blk_pin = NULL;$/;" v file: f_port_pin_from_blk_pin ./util/vpr_utils.c /^static int ** f_port_pin_from_blk_pin = NULL;$/;" v file: f_timing_stats ./timing/path_delay.c /^static t_timing_stats * f_timing_stats = NULL; \/* Critical path delay and worst-case slack per constraint. *\/$/;" v file: factor ./power/PowerSpicedComponent.h /^ float factor;$/;" m class:PowerCallibSize falling_edge ./timing/read_sdc.c /^ float falling_edge;$/;" m struct:s_sdc_clock file: -fan_in ../../libarchfpga/include/physical_types.h /^ int fan_in;$/;" m struct:s_interconnect fan_in ./base/vpr_types.h /^ short fan_in;$/;" m struct:s_rr_node -fan_out ../../libarchfpga/include/physical_types.h /^ int fan_out;$/;" m struct:s_interconnect fanout ./base/vpr_types.h /^ int fanout;$/;" m struct:s_clock -fast ../../libarchfpga/fpga_spice_include/spice_types.h /^ int fast;$/;" m struct:s_spice_params fc ./base/place_and_route.h /^ int fc; \/* at this fc *\/$/;" m struct:s_fmap_cell fc_constraints ./base/vpr_types.h /^ t_override_constraint * fc_constraints; \/* [0..num_fc_constraints - 1] *\/$/;" m struct:s_timing_constraints fc_in ./base/vpr_types.h /^ int fc_in;$/;" m struct:s_cb fc_out ./base/vpr_types.h /^ int fc_out;$/;" m struct:s_sb -fcc ../../pcre/SRC/internal.h /^ const uschar *fcc; \/* Points to case-flipping table *\/$/;" m struct:compile_data -fcc_offset ../../pcre/SRC/internal.h 654;" d fclose_wire_L_file_handler_in_llist ./fpga_x2p/verilog/verilog_report_timing.c /^void fclose_wire_L_file_handler_in_llist(t_llist* rr_path_cnt) {$/;" f fcn ./base/graphics.c /^ void (*fcn) (void (*drawscreen) (void));$/;" m struct:__anon4 file: feasible_blocks ./base/vpr_types.h /^ struct s_pack_molecule **feasible_blocks;$/;" m struct:s_pb_stats typeref:struct:s_pb_stats::s_pack_molecule feasible_routing ./route/route_common.c /^boolean feasible_routing(void) {$/;" f feasible_routing_rr_graph ./fpga_x2p/router/fpga_x2p_router.c /^boolean feasible_routing_rr_graph(t_rr_graph* local_rr_graph, $/;" f ff_constraints ./base/vpr_types.h /^ t_override_constraint * ff_constraints; \/* [0..num_ff_constraints - 1] array of such constraints *\/$/;" m struct:s_timing_constraints -file_exists ../../libarchfpga/util.c /^boolean file_exists(const char * filename) {$/;" f file_handler ./fpga_x2p/verilog/verilog_report_timing.c /^ FILE* file_handler;$/;" m struct:s_wireL_cnt file: -file_line_number ../../libarchfpga/util.c /^int file_line_number; \/* file in line number being parsed *\/$/;" v file_line_number ./base/vpr_types.h /^ int file_line_number; \/* line in the SDC file I\/O was constrained on - used for error reporting *\/$/;" m struct:s_io file_line_number ./base/vpr_types.h /^ int file_line_number; \/* line in the SDC file clock was constrained on - used for error reporting *\/$/;" m struct:s_override_constraint fillarc ./base/graphics.c /^fillarc (float xc, float yc, float rad, float startang, float angextent) {$/;" f @@ -2758,7 +1901,6 @@ fillpoly ./base/graphics.c /^fillpoly (t_point *points, int npoints) $/;" f fillpoly ./base/graphics.c /^void fillpoly (t_point *points, int npoints) { }$/;" f fillrect ./base/graphics.c /^fillrect (float x1, float y1, float x2, float y2) $/;" f fillrect ./base/graphics.c /^void fillrect (float x1, float y1, float x2, float y2) { }$/;" f -findPortByName ../../libarchfpga/read_xml_arch_file.c /^static t_port * findPortByName(const char * name, t_pb_type * pb_type,$/;" f file: find_affected_blocks ./place/place.c /^static int find_affected_blocks(int b_from, int x_to, int y_to, int z_to) {$/;" f file: find_affected_nets ./place/place.c /^static int find_affected_nets(int *nets_to_update) {$/;" f file: find_all_the_macro ./place/place_macro.c /^static void find_all_the_macro (int * num_of_macro, int * pl_macro_member_blk_num_of_this_blk, $/;" f file: @@ -2767,7 +1909,6 @@ find_blb_wlb_ports_spice_model ./fpga_x2p/base/fpga_x2p_utils.c /^void find_blb_ find_blk_net_pin_side ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int find_blk_net_pin_side(t_block target_blk,$/;" f find_blk_net_pin_sides ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^void find_blk_net_pin_sides(t_block target_blk,$/;" f find_blk_net_type_pins ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^void find_blk_net_type_pins(int n_blks, t_block* blk,$/;" f -find_bracket ../../pcre/SRC/pcre.c /^find_bracket(const uschar *code, BOOL utf8, int number)$/;" f file: find_cc_constraint ./timing/read_sdc.c /^static int find_cc_constraint(char * source_clock_name, char * sink_clock_name) {$/;" f file: find_cf_constraint ./timing/path_delay.c /^static int find_cf_constraint(char * source_clock_name, char * sink_ff_name) {$/;" f file: find_clock ./timing/path_delay.c /^static int find_clock(char * net_name) {$/;" f file: @@ -2778,8 +1919,6 @@ find_drive_rr_nodes_switch_box ./fpga_x2p/base/fpga_x2p_utils.c /^void find_driv find_expansion_edge_of_pattern ./pack/prepack.c /^static t_pb_graph_edge * find_expansion_edge_of_pattern(INP int pattern_index,$/;" f file: find_fanin_rr_node ./pack/output_blif.c /^static int find_fanin_rr_node(t_pb *cur_pb, enum PORTS type, int rr_node_index) {$/;" f file: find_ff_clock_tnode ./timing/path_delay.c /^static t_tnode * find_ff_clock_tnode(int inode, boolean is_prepacked) {$/;" f file: -find_firstassertedchar ../../pcre/SRC/pcre.c /^find_firstassertedchar(const uschar *code, int *options, BOOL inassert)$/;" f file: -find_fixedlength ../../pcre/SRC/pcre.c /^find_fixedlength(uschar *code, int options)$/;" f file: find_grid_mapped_logical_block ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int find_grid_mapped_logical_block(int x, int y,$/;" f find_index ./base/verilog_writer.c /^int find_index(char *row,int inputs)\/*returns the index of the 64bit truth table that this temporary truth table row corresponds to*\/$/;" f find_input ./timing/path_delay.c /^static int find_input(char * net_name) {$/;" f file: @@ -2787,7 +1926,6 @@ find_interc_des_pb_graph_pin ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void fin find_interc_fan_in_des_pb_graph_pin ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin,$/;" f find_iopad_spice_model ./fpga_x2p/base/fpga_x2p_utils.c /^t_spice_model* find_iopad_spice_model(int num_spice_model,$/;" f find_label_of_track ./route/rr_graph2.c /^static int find_label_of_track(int *wire_mux_on_track, int num_wire_muxes,$/;" f file: -find_length_llist ../../libarchfpga/linkedlist.c /^int find_length_llist(t_llist* head) {$/;" f find_matched_block_id_for_one_grid ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^int find_matched_block_id_for_one_grid(int x, int y) {$/;" f find_mosfet_tech_lib ./fpga_x2p/base/fpga_x2p_utils.c /^t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib,$/;" f find_name_matched_spice_model ./fpga_x2p/base/fpga_x2p_utils.c /^t_spice_model* find_name_matched_spice_model(char* spice_model_name,$/;" f @@ -2819,16 +1957,12 @@ find_to ./place/place.c /^static boolean find_to(int x_from, int y_from, t_type_ find_type_col ./base/SetupGrid.c /^static t_type_ptr find_type_col(INP int x) {$/;" f file: findfontsize ./base/graphics.c /^int findfontsize(float ymax) { }$/;" f findfontsize ./base/graphics.c /^int findfontsize(float ymax) {$/;" f -first_byte ../../pcre/SRC/internal.h /^ unsigned short int first_byte;$/;" m struct:real_pcre first_iter_pres_fac ./base/ReadOptions.h /^ float first_iter_pres_fac;$/;" m struct:s_options first_iter_pres_fac ./base/vpr_types.h /^ float first_iter_pres_fac;$/;" m struct:s_router_opts -first_significant_code ../../pcre/SRC/pcre.c /^first_significant_code(const uschar *code, int *options, int optbit)$/;" f file: fix_name ./base/verilog_writer.c /^char *fix_name(char *name)$/;" f fixed_channel_width ./base/vpr_types.h /^ int fixed_channel_width;$/;" m struct:s_router_opts fixup_branch ./timing/slre.c /^static void fixup_branch(struct slre *r, int fixup) {$/;" f file: flag_postfix ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^static char* flag_postfix = "_flag";$/;" v file: -flags ../../libarchfpga/include/ezxml.h /^ short flags; \/* additional information *\/$/;" m struct:ezxml -flags ../../pcre/SRC/pcre.h /^ unsigned long int flags; \/* Bits for which fields are set *\/$/;" m struct:pcre_extra flush_intermediate_queues ./pack/cluster_placement.c /^static void flush_intermediate_queues($/;" f file: flushinput ./base/graphics.c /^flushinput (void) $/;" f flushinput ./base/graphics.c /^void flushinput (void) { }$/;" f @@ -2849,7 +1983,6 @@ formal_verification_top_postfix ./fpga_x2p/verilog/verilog_global.c /^char* form formal_verification_verilog_file_postfix ./fpga_x2p/verilog/verilog_global.c /^char* formal_verification_verilog_file_postfix = "_top_formal_verification.v"; $/;" v formality_include_user_defined_verilog_netlists ./fpga_x2p/verilog/verilog_formality_autodeck.c /^void formality_include_user_defined_verilog_netlists(FILE* fp,$/;" f file: formality_script_name_postfix ./fpga_x2p/verilog/verilog_global.c /^char* formality_script_name_postfix = "_formality_script.tcl";$/;" v -format ../../libarchfpga/include/physical_types.h /^ enum e_pin_to_pin_annotation_format format;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_format format_dir_path ./fpga_x2p/base/fpga_x2p_utils.c /^char* format_dir_path(char* dir_path) {$/;" f format_spice_node_prefix ./fpga_x2p/base/fpga_x2p_utils.c /^char* format_spice_node_prefix(char* spice_node_prefix) {$/;" f format_verilog_node_prefix ./fpga_x2p/verilog/verilog_utils.c /^char* format_verilog_node_prefix(char* verilog_node_prefix) {$/;" f @@ -3080,9 +2213,6 @@ fprintf_spice_pb_graph_pin_interc ./fpga_x2p/spice/spice_pbtypes.c /^void fprint fprintf_spice_pb_graph_port_interc ./fpga_x2p/spice/spice_pbtypes.c /^void fprintf_spice_pb_graph_port_interc(FILE* fp,$/;" f fprintf_spice_routing_testbench_generic_stimuli ./fpga_x2p/spice/spice_routing_testbench.c /^void fprintf_spice_routing_testbench_generic_stimuli(FILE* fp,$/;" f file: fptr ./base/vpr_types.h /^ float *fptr;$/;" m struct:s_linked_f_pointer -frac_cb ../../libarchfpga/include/physical_types.h /^ float frac_cb;$/;" m struct:s_segment_inf -frac_lut ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean frac_lut;$/;" m struct:s_spice_model_lut -frac_sb ../../libarchfpga/include/physical_types.h /^ float frac_sb;$/;" m struct:s_segment_inf freeGrid ./base/SetupGrid.c /^void freeGrid() {$/;" f freeTokens ./util/token.c /^void freeTokens(INP t_token *tokens, INP int num_tokens) {$/;" f free_2D_matrix ./fpga_x2p/base/fpga_x2p_timing_utils.c /^void free_2D_matrix(void** delay_matrix,$/;" f @@ -3095,7 +2225,6 @@ free_blk_pin_from_port_pin ./util/vpr_utils.c /^void free_blk_pin_from_port_pin( free_buffer_list ./mrfpga/buffer_insertion.c /^static void free_buffer_list( t_buffer_plan_list list )$/;" f file: free_cb ./util/vpr_utils.c /^void free_cb(t_pb *pb) {$/;" f free_cb_info_array ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void free_cb_info_array(t_cb*** LL_cb_info, int LL_nx, int LL_ny) {$/;" f -free_chunk_memory ../../libarchfpga/util.c /^void free_chunk_memory(t_chunk *chunk_info) {$/;" f free_chunk_memory_trace ./route/route_common.c /^void free_chunk_memory_trace(void) {$/;" f free_circuit ./base/vpr_api.c /^void free_circuit() {$/;" f free_clb_nets_spice_net_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void free_clb_nets_spice_net_info() {$/;" f @@ -3115,11 +2244,7 @@ free_global_routing_conf_bits ./fpga_x2p/verilog/verilog_api.c /^void free_globa free_hash_table ./util/hash.c /^void free_hash_table(struct s_hash **hash_table) {$/;" f free_heap_data ./route/route_common.c /^void free_heap_data(struct s_heap *hptr) {$/;" f free_imacro_from_iblk ./place/place_macro.c /^static void free_imacro_from_iblk(void) {$/;" f file: -free_int_list ../../libarchfpga/util.c /^void free_int_list(t_linked_int ** int_list_head_ptr) {$/;" f free_io_constraint ./timing/read_sdc.c /^static void free_io_constraint(t_io *& io_array, int num_ios) {$/;" f file: -free_ivec_matrix ../../libarchfpga/util.c /^void free_ivec_matrix(struct s_ivec **ivec_matrix, int nrmin, int nrmax,$/;" f -free_ivec_matrix3 ../../libarchfpga/util.c /^void free_ivec_matrix3(struct s_ivec ***ivec_matrix3, int nrmin, int nrmax,$/;" f -free_ivec_vector ../../libarchfpga/util.c /^void free_ivec_vector(struct s_ivec *ivec_vector, int nrmin, int nrmax) {$/;" f free_legal_placements ./place/place.c /^static void free_legal_placements() {$/;" f file: free_legalizer_for_cluster ./pack/cluster_legality.c /^void free_legalizer_for_cluster(INP t_block* clb, boolean free_local_rr_graph) {$/;" f free_linked_list ./base/verilog_writer.c /^pb_list *free_linked_list(pb_list *list)$/;" f @@ -3127,13 +2252,9 @@ free_linked_list_conn ./base/verilog_writer.c /^conn_list *free_linked_list_conn free_linked_rc_edge ./timing/net_delay.c /^void free_linked_rc_edge(t_linked_rc_edge * rc_edge,$/;" f free_linked_rt_edge ./route/route_tree_timing.c /^static void free_linked_rt_edge(t_linked_rt_edge * rt_edge) {$/;" f file: free_list_of_pack_patterns ./pack/prepack.c /^void free_list_of_pack_patterns(INP t_pack_patterns *list_of_pack_patterns, INP int num_packing_patterns) {$/;" f -free_llist ../../libarchfpga/linkedlist.c /^void free_llist(t_llist* head) {$/;" f free_logical_blocks ./base/read_netlist.c /^void free_logical_blocks(void) {$/;" f free_logical_nets ./base/read_netlist.c /^void free_logical_nets(void) {$/;" f free_lookups_and_criticalities ./place/timing_place.c /^void free_lookups_and_criticalities(float ***net_delay, t_slack * slacks) {$/;" f -free_matrix ../../libarchfpga/util.c /^void free_matrix(void *vptr, int nrmin, int nrmax, int ncmin, size_t elsize) {$/;" f -free_matrix3 ../../libarchfpga/util.c /^void free_matrix3(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f -free_matrix4 ../../libarchfpga/util.c /^void free_matrix4(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f free_muxes_llist ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void free_muxes_llist(t_llist* muxes_head) {$/;" f free_net_delay ./timing/net_delay.c /^void free_net_delay(float **net_delay,$/;" f free_one_cb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void free_one_cb_info(t_cb* cur_cb) {$/;" f @@ -3197,16 +2318,9 @@ free_try_swap_arrays ./place/place.c /^static void free_try_swap_arrays(void) {$ free_type_pin_to_track_map ./route/rr_graph.c /^static void free_type_pin_to_track_map(int***** ipin_to_track_map,$/;" f file: free_type_track_to_ipin_map ./route/rr_graph.c /^static void free_type_track_to_ipin_map(struct s_ivec**** track_to_pin_map,$/;" f file: free_wire_L_llist ./fpga_x2p/verilog/verilog_report_timing.c /^void free_wire_L_llist(t_llist* rr_path_cnt) {$/;" f -freq ../../libarchfpga/fpga_spice_include/spice_types.h /^ float freq; $/;" m struct:s_spice_net_info -frequency ../../libarchfpga/include/physical_types.h /^ int frequency;$/;" m struct:s_segment_inf -from_block ../../libarchfpga/include/cad_types.h /^ t_pack_pattern_block *from_block;$/;" m struct:s_pack_pattern_connections from_clb_pin_end_index ./base/vpr_types.h /^ int from_clb_pin_end_index;$/;" m struct:s_clb_to_clb_directs from_clb_pin_start_index ./base/vpr_types.h /^ int from_clb_pin_start_index;$/;" m struct:s_clb_to_clb_directs from_clb_type ./base/vpr_types.h /^ t_type_descriptor *from_clb_type;$/;" m struct:s_clb_to_clb_directs -from_pin ../../libarchfpga/include/cad_types.h /^ t_pb_graph_pin *from_pin;$/;" m struct:s_pack_pattern_connections -from_pin ../../libarchfpga/include/physical_types.h /^ char *from_pin;$/;" m struct:s_direct_inf -from_port ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_port* from_port;$/;" m struct:s_spice_model_tedge -from_port_pin_number ../../libarchfpga/fpga_spice_include/spice_types.h /^ int from_port_pin_number;$/;" m struct:s_spice_model_tedge front ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_list { t_buffer_plan_node* front; } t_buffer_plan_list;$/;" m struct:s_buffer_plan_list file: fs ./base/place_and_route.h /^ int fs; \/* at this fs *\/$/;" m struct:s_fmap_cell fs ./base/vpr_types.h /^ int fs;$/;" m struct:s_sb @@ -3225,7 +2339,6 @@ g_sdc ./timing/read_sdc.c /^t_timing_constraints * g_sdc = NULL;$/;" v g_solution_inf ./power/power.c /^t_solution_inf g_solution_inf;$/;" v g_transistor_last_searched ./power/power_cmos_tech.c /^static t_transistor_inf * g_transistor_last_searched;$/;" v file: gain ./base/vpr_types.h /^ std::map gain; \/* Attraction (inverse of cost) function *\/$/;" m struct:s_pb_stats -gate_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_gate* gate_info;$/;" m struct:s_spice_model_design_tech_info gc ./base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: gc_menus ./base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: gcxor ./base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: @@ -3242,6 +2355,7 @@ gen_verilog_one_cb_module_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_ve gen_verilog_one_grid_instance_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_grid_instance_name(int grid_x, int grid_y) {$/;" f gen_verilog_one_grid_module_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_grid_module_name(int grid_x, int grid_y) {$/;" f gen_verilog_one_mux_module_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_mux_module_name(t_spice_model* spice_model, $/;" f +gen_verilog_one_pb_graph_node_full_name_in_hierarchy ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_pb_graph_node_full_name_in_hierarchy(t_pb_graph_node* cur_pb_graph_node) {$/;" f gen_verilog_one_pb_graph_node_instance_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_pb_graph_node_instance_name(t_pb_graph_node* cur_pb_graph_node) {$/;" f gen_verilog_one_pb_graph_pin_full_name_in_hierarchy ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy(t_pb_graph_pin* cur_pb_graph_pin) {$/;" f gen_verilog_one_pb_graph_pin_full_name_in_hierarchy_grand_parent_node ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy_grand_parent_node(t_pb_graph_pin* cur_pb_graph_pin) {$/;" f @@ -3315,6 +2429,7 @@ get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node ./pack/pre get_expected_segs_to_target ./route/route_timing.c /^static int get_expected_segs_to_target(int inode, int target_node,$/;" f file: get_ff_output_init_val ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^int get_ff_output_init_val(t_logical_block* ff_logical_block) {$/;" f get_first_pin ./place/timing_place_lookup.c /^static int get_first_pin(enum e_pin_type pintype, t_type_ptr type) {$/;" f file: +get_fpga_x2p_global_all_clock_ports ./fpga_x2p/base/fpga_x2p_utils.c /^void get_fpga_x2p_global_all_clock_ports(t_llist* head,$/;" f get_fpga_x2p_global_op_clock_ports ./fpga_x2p/base/fpga_x2p_utils.c /^void get_fpga_x2p_global_op_clock_ports(t_llist* head,$/;" f get_free_molecule_with_most_ext_inputs_for_cluster ./pack/cluster.c /^static t_pack_molecule *get_free_molecule_with_most_ext_inputs_for_cluster($/;" f file: get_grid_block_subckt_name ./fpga_x2p/spice/spice_pbtypes.c /^char* get_grid_block_subckt_name(int x,$/;" f @@ -3451,22 +2566,11 @@ gr_automode ./base/draw.c /^static int gr_automode; \/* Need user input after: 0 grid ./base/globals.c /^struct s_grid_tile **grid = NULL; \/* [0..(nx+1)][0..(ny+1)] Physical block list *\/$/;" v typeref:struct:s_grid_tile grid ./base/globals_declare.h /^struct s_grid_tile **grid;$/;" v typeref:struct:s_grid_tile grid_backup ./place/timing_place_lookup.c /^static struct s_grid_tile **grid_backup;$/;" v typeref:struct:s_grid_tile file: -grid_conf_bits_lsb ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** grid_conf_bits_lsb;$/;" m struct:s_sram_orgz_info -grid_conf_bits_msb ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** grid_conf_bits_msb;$/;" m struct:s_sram_orgz_info -grid_index_high ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** grid_index_high;$/;" m struct:s_spice_model -grid_index_low ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** grid_index_low;$/;" m struct:s_spice_model -grid_loc_def ../../libarchfpga/include/physical_types.h /^ struct s_grid_loc_def *grid_loc_def; \/* [0..num_def-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_grid_loc_def -grid_loc_type ../../libarchfpga/include/physical_types.h /^ enum e_grid_loc_type grid_loc_type;$/;" m struct:s_grid_loc_def typeref:enum:s_grid_loc_def::e_grid_loc_type -grid_logic_tile_area ../../libarchfpga/include/physical_types.h /^ float grid_logic_tile_area;$/;" m struct:s_arch grid_logic_tile_area ./base/globals.c /^float grid_logic_tile_area = 0;$/;" v -grid_nx ../../libarchfpga/fpga_spice_include/spice_types.h /^ int grid_nx; \/* grid size *\/ $/;" m struct:s_sram_orgz_info -grid_ny ../../libarchfpga/fpga_spice_include/spice_types.h /^ int grid_ny;$/;" m struct:s_sram_orgz_info -grid_reserved_conf_bits ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** grid_reserved_conf_bits;$/;" m struct:s_sram_orgz_info grid_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* grid_spice_file_name_prefix = "grid_";$/;" v grid_spice_subckt_file_path_head ./fpga_x2p/spice/spice_globals.c /^t_llist* grid_spice_subckt_file_path_head = NULL;$/;" v grid_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* grid_verilog_file_name_prefix = "grid_";$/;" v grid_verilog_subckt_file_path_head ./fpga_x2p/verilog/verilog_global.c /^t_llist* grid_verilog_subckt_file_path_head = NULL;$/;" v -group_num ../../pcre/SRC/internal.h /^ int group_num; \/* Number of group that was called *\/$/;" m struct:recursion_info group_size ./base/vpr_types.h /^ int group_size;$/;" m struct:s_seg_details group_start ./base/vpr_types.h /^ int group_start;$/;" m struct:s_seg_details hAllObjtestDC ./base/graphics.c /^hObjtestDC, hAllObjtestDC; \/* object test *\/$/;" v file: @@ -3501,7 +2605,6 @@ heap_size ./route/route_common.c /^static int heap_size; \/* Number of slots in heap_tail ./fpga_x2p/base/fpga_x2p_types.h /^ int heap_tail; \/* Index of first unused slot in the heap array *\/$/;" m struct:fpga_spice_rr_graph heap_tail ./route/route_common.c /^static int heap_tail; \/* Index of first unused slot in the heap array *\/$/;" v file: heapsort ./util/heapsort.c /^void heapsort(int *sort_index, float *sort_values, int nelem, int start_index) {$/;" f -height ../../libarchfpga/include/physical_types.h /^ int height;$/;" m struct:s_type_descriptor height ./base/graphics.c /^ int height; $/;" m struct:__anon4 file: help_opts ./fpga_x2p/shell/cmd_help.h /^t_opt_info help_opts[] = {$/;" v highlight_blocks ./base/draw.c /^static void highlight_blocks(float x, float y) {$/;" f file: @@ -3517,41 +2620,25 @@ i_ds ./power/power.h /^ float i_ds;$/;" m struct:s_power_nmos_leakage_pair iblock ./base/vpr_types.h /^ int iblock;$/;" m struct:s_trace icarus_simulator_flag ./fpga_x2p/verilog/verilog_global.c /^char* icarus_simulator_flag = "ICARUS_SIMULATOR"; \/\/ the flag to enable specific Verilog code in testbenches$/;" v id_path ./base/vpr_types.h /^ int id_path;$/;" m struct:s_rr_node +identify_mirror_connection_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void identify_mirror_connection_blocks() {$/;" f +identify_mirror_switch_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void identify_mirror_switch_blocks() {$/;" f identify_rr_node_driver_switch ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void identify_rr_node_driver_switch(t_det_routing_arch RoutingArch,$/;" f file: -idle_mode_name ../../libarchfpga/include/physical_types.h /^ char* idle_mode_name;$/;" m struct:s_pb_type ilines ./base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: in_dens ./power/power.h /^ float * in_dens; \/* Switching density of inputs *\/$/;" m struct:s_rr_node_power in_flight ./base/vpr_types.h /^ t_cluster_placement_primitive *in_flight; \/* ptrs to primitives currently being considered *\/$/;" m struct:s_cluster_placement_stats -in_port_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* in_port_name;$/;" m struct:s_spice_model_delay_info in_prob ./power/power.h /^ float * in_prob; \/* Static probability of inputs *\/$/;" m struct:s_rr_node_power include_dir ./base/vpr_types.h /^ char* include_dir;$/;" m struct:s_spice_opts include_icarus_simulator ./base/vpr_types.h /^ boolean include_icarus_simulator;$/;" m struct:s_syn_verilog_opts -include_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlist;$/;" m struct:s_spice_model -include_netlists ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlists; $/;" m struct:s_spice include_netlists_include_user_defined_verilog_netlists ./fpga_x2p/verilog/verilog_include_netlists.c /^void include_netlists_include_user_defined_verilog_netlists(FILE* fp,$/;" f file: include_signal_init ./base/vpr_types.h /^ boolean include_signal_init;$/;" m struct:s_syn_verilog_opts include_timing ./base/vpr_types.h /^ boolean include_timing;$/;" m struct:s_syn_verilog_opts -included ../../libarchfpga/fpga_spice_include/spice_types.h /^ int included;$/;" m struct:s_spice_model_netlist -incremental_cost ../../libarchfpga/include/cad_types.h /^ float incremental_cost; \/* cost dependant on current status of packing *\/$/;" m struct:s_cluster_placement_primitive -index ../../libarchfpga/fpga_spice_include/spice_types.h /^ int index;$/;" m struct:s_conf_bit_info -index ../../libarchfpga/include/cad_types.h /^ int index; \/* array index for pattern*\/$/;" m struct:s_pack_patterns -index ../../libarchfpga/include/logic_types.h /^ int index; \/* indexing for array look-up *\/$/;" m struct:s_model_ports -index ../../libarchfpga/include/logic_types.h /^ int index;$/;" m struct:s_model -index ../../libarchfpga/include/physical_types.h /^ int index; \/* index of type descriptor in array (allows for index referencing) *\/$/;" m struct:s_type_descriptor -index ../../libarchfpga/include/physical_types.h /^ int index;$/;" m struct:s_mode -index ../../libarchfpga/include/physical_types.h /^ int index;$/;" m struct:s_port index ./base/vpr_types.h /^ int index; \/* Index in array that this block can be found *\/$/;" m struct:s_logical_block index ./base/vpr_types.h /^ int index;$/;" m struct:s_seg_details index ./base/vpr_types.h /^ int index;$/;" m struct:s_trace index ./route/route_common.h /^ int index;$/;" m struct:s_heap index ./util/hash.h /^ int index;$/;" m struct:s_hash -index_in_top_tb ../../libarchfpga/fpga_spice_include/spice_types.h /^ int index_in_top_tb;$/;" m struct:s_conf_bit_info -infer_annotations ../../libarchfpga/include/physical_types.h /^ boolean infer_annotations;$/;" m struct:s_interconnect -infer_pattern ../../libarchfpga/include/physical_types.h /^ boolean infer_pattern; \/*If TRUE, infer pattern based on patterns connected to it*\/$/;" m struct:s_pb_graph_edge init_and_check_one_sram_inf_orgz ./fpga_x2p/base/fpga_x2p_setup.c /^void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz,$/;" f file: init_and_check_sram_inf ./fpga_x2p/base/fpga_x2p_setup.c /^void init_and_check_sram_inf(t_arch* arch,$/;" f file: -init_arch_mrfpga ../../libarchfpga/read_xml_mrfpga.c /^void init_arch_mrfpga(t_arch_mrfpga* arch_mrfpga) {$/;" f -init_buffer_inf ../../libarchfpga/read_xml_mrfpga.c /^void init_buffer_inf(t_buffer_inf* buffer_inf) {$/;" f init_chan ./base/place_and_route.c /^void init_chan(int cfactor, t_chan_width_dist chan_width_dist) {$/;" f init_chan_seg_detail_params ./route/rr_graph_swseg.c /^static int init_chan_seg_detail_params(INP char* chan_type,$/;" f file: init_check_arch_pb_type_idle_and_phy_mode ./fpga_x2p/base/fpga_x2p_setup.c /^void init_check_arch_pb_type_idle_and_phy_mode(t_arch* Arch) {$/;" f file: @@ -3571,7 +2658,6 @@ init_llist_verilog_and_spice_syntax_char ./fpga_x2p/base/fpga_x2p_setup.c /^t_ll init_logical_block_spice_model_temp_used ./fpga_x2p/spice/spice_utils.c /^void init_logical_block_spice_model_temp_used(t_spice_model* spice_model) {$/;" f init_logical_block_spice_model_type_temp_used ./fpga_x2p/spice/spice_utils.c /^void init_logical_block_spice_model_type_temp_used(int num_spice_models, t_spice_model* spice_model,$/;" f init_mem_bank_info ./fpga_x2p/base/fpga_x2p_utils.c /^void init_mem_bank_info(t_mem_bank_info* cur_mem_bank_info,$/;" f -init_memristor_inf ../../libarchfpga/read_xml_mrfpga.c /^void init_memristor_inf(t_memristor_inf* memristor_inf) {$/;" f init_mux_arch_default ./power/power_util.c /^static void init_mux_arch_default(t_mux_arch * mux_arch, int levels,$/;" f file: init_one_cb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void init_one_cb_info(t_cb* cur_cb) { $/;" f init_one_grid_num_conf_bits ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void init_one_grid_num_conf_bits(int ix, int iy, $/;" f @@ -3603,7 +2689,6 @@ init_sram_orgz_info ./fpga_x2p/base/fpga_x2p_utils.c /^void init_sram_orgz_info( init_sram_orgz_info_reserved_blwl ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^void init_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f init_standalone_sram_info ./fpga_x2p/base/fpga_x2p_utils.c /^void init_standalone_sram_info(t_standalone_sram_info* cur_standalone_sram_info,$/;" f init_t ./base/vpr_types.h /^ float init_t;$/;" m struct:s_annealing_sched -init_val ../../libarchfpga/fpga_spice_include/spice_types.h /^ int init_val;$/;" m struct:s_spice_net_info init_val ./base/vpr_types.h /^ int init_val;$/;" m struct:s_logical_block init_world ./base/graphics.c /^init_world (float x1, float y1, float x2, float y2) $/;" f init_world ./base/graphics.c /^void init_world (float xl, float yt, float xr, float yb) { }$/;" f @@ -3620,47 +2705,21 @@ inner_num ./base/vpr_types.h /^ float inner_num;$/;" m struct:s_annealing_sched inode ./route/route_tree_timing.h /^ int inode;$/;" m struct:s_rt_node inode ./timing/net_delay_types.h /^ int inode;$/;" m struct:s_rc_node inode_head ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: -inport_link_pin ../../libarchfpga/include/cad_types.h /^ int inport_link_pin; \/* applicable pin of chain input port *\/$/;" m struct:s_model_chain_pattern -input_buffer ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* input_buffer;$/;" m struct:s_spice_model -input_edges ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_edge** input_edges; \/* [0..num_input_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge -input_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int* input_level; \/* [0...num_input] *\/$/;" m struct:s_spice_mux_arch -input_link_port ../../libarchfpga/include/cad_types.h /^ t_model_ports *input_link_port; \/* pointer to port of chain input *\/$/;" m struct:s_model_chain_pattern input_net_tnodes ./base/vpr_types.h /^ struct s_tnode ***input_net_tnodes; \/* [0..num_input_ports-1][0..num_pins -1] correspnding input net tnode *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_tnode input_nets ./base/vpr_types.h /^ int **input_nets; \/* [0..num_input_ports-1][0..num_port_pins-1] List of input nets connected to this logical_block. *\/$/;" m struct:s_logical_block -input_offset ../../libarchfpga/fpga_spice_include/spice_types.h /^ int* input_offset; \/* [0...num_input] *\/ $/;" m struct:s_spice_mux_arch -input_pin_class_size ../../libarchfpga/include/physical_types.h /^ int *input_pin_class_size; \/* Stores the number of pins that belong to a particular input pin class *\/$/;" m struct:s_pb_graph_node -input_pins ../../libarchfpga/include/physical_types.h /^ char * input_pins;$/;" m struct:s_pin_to_pin_annotation -input_pins ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_pin *** input_pins; \/\/ [0..num_input_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin -input_pins ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin **input_pins; \/* [0..num_input_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node -input_pins ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin **input_pins;$/;" m struct:s_pb_graph_edge input_pins_used ./base/vpr_types.h /^ int **input_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of input pins of this class that are used *\/$/;" m struct:s_pb_stats -input_ports_eq_auto_detect ../../libarchfpga/include/physical_types.h /^ boolean input_ports_eq_auto_detect;$/;" m struct:s_type_descriptor -input_slew_fall_time ../../libarchfpga/fpga_spice_include/spice_types.h /^ float input_slew_fall_time; $/;" m struct:s_spice_stimulate_params -input_slew_fall_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -input_slew_rise_time ../../libarchfpga/fpga_spice_include/spice_types.h /^ float input_slew_rise_time; $/;" m struct:s_spice_stimulate_params -input_slew_rise_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -input_string ../../libarchfpga/include/physical_types.h /^ char *input_string;$/;" m struct:s_interconnect -input_thres_pct_fall ../../libarchfpga/fpga_spice_include/spice_types.h /^ float input_thres_pct_fall;$/;" m struct:s_spice_meas_params -input_thres_pct_rise ../../libarchfpga/fpga_spice_include/spice_types.h /^ float input_thres_pct_rise;$/;" m struct:s_spice_meas_params -inputs ../../libarchfpga/include/logic_types.h /^ t_model_ports *inputs; \/* linked list of input\/clock ports *\/$/;" m struct:s_model inputs_per_cluster ./base/ReadOptions.h /^ int inputs_per_cluster;$/;" m struct:s_options insert_buffer ./mrfpga/buffer_insertion.c /^static t_buffer_plan_list insert_buffer( t_buffer_plan_list list, int inode, float C, float R, float Tdel, int num_pins )$/;" f file: insert_buffer_plan_to_list ./mrfpga/buffer_insertion.c /^static t_buffer_plan_list insert_buffer_plan_to_list( t_buffer_plan plan, t_buffer_plan_list list ) {$/;" f file: insert_in_edge_list ./route/rr_graph_util.c /^insert_in_edge_list(INP t_linked_edge * head, INP int edge, INP short iswitch) {$/;" f insert_in_hash_table ./util/hash.c /^insert_in_hash_table(struct s_hash **hash_table, char *name,$/;" f -insert_in_int_list ../../libarchfpga/util.c /^insert_in_int_list(t_linked_int * head, int data,$/;" f insert_in_int_list2 ./mrfpga/mrfpga_util.c /^t_linked_int* insert_in_int_list2 (t_linked_int *head, int data )$/;" f -insert_in_vptr_list ../../libarchfpga/util.c /^insert_in_vptr_list(struct s_linked_vptr *head, void *vptr_to_add) {$/;" f -insert_llist_node ../../libarchfpga/linkedlist.c /^t_llist* insert_llist_node(t_llist* cur) {$/;" f -insert_llist_node_before_head ../../libarchfpga/linkedlist.c /^t_llist* insert_llist_node_before_head(t_llist* old_head) {$/;" f -insert_node_to_int_list ../../libarchfpga/util.c /^insert_node_to_int_list(struct s_linked_int *head, int int_to_add) {$/;" f insert_switch_to_buffer_list ./mrfpga/buffer_insertion.c /^static void insert_switch_to_buffer_list( t_buffer_plan_list list, struct s_switch_inf switch_inf_local)$/;" f file: insert_switch_to_buffer_plan ./mrfpga/buffer_insertion.c /^static t_buffer_plan insert_switch_to_buffer_plan( t_buffer_plan plan, struct s_switch_inf switch_inf_local)$/;" f file: insert_to_linked_list ./base/verilog_writer.c /^pb_list *insert_to_linked_list(t_pb *pb_new , pb_list *list)$/;" f insert_to_linked_list_conn ./base/verilog_writer.c /^conn_list *insert_to_linked_list_conn(t_pb *driver_new , t_pb *load_new , t_pb_graph_pin *driver_pin_ , t_pb_graph_pin *load_pin_ , float path_delay , conn_list *list)$/;" f insert_wire_to_buffer_list ./mrfpga/buffer_insertion.c /^static void insert_wire_to_buffer_list( t_buffer_plan_list list, float C,float R )$/;" f file: insert_wire_to_buffer_plan ./mrfpga/buffer_insertion.c /^static t_buffer_plan insert_wire_to_buffer_plan( t_buffer_plan plan, float C, float R )$/;" f file: -instances ../../libarchfpga/include/logic_types.h /^ void *instances;$/;" m struct:s_model instantiate_SDF_header ./base/verilog_writer.c /^void instantiate_SDF_header(FILE *SDF)$/;" f instantiate_input_interconnect ./base/verilog_writer.c /^void instantiate_input_interconnect(FILE *verilog , FILE *SDF , char *clock_name)$/;" f instantiate_interconnect ./base/verilog_writer.c /^void instantiate_interconnect(FILE *verilog , int block_num , t_pb *pb , FILE *SDF)$/;" f @@ -3670,20 +2729,12 @@ instantiate_wires ./base/verilog_writer.c /^void instantiate_wires(FILE *verilog int_2_binary_str ./power/power_util.c /^static void int_2_binary_str(char * binary_str, int value, int str_length) {$/;" f file: inter_cluster_net_delay ./base/ReadOptions.h /^ float inter_cluster_net_delay;$/;" m struct:s_options inter_cluster_net_delay ./base/vpr_types.h /^ float inter_cluster_net_delay;$/;" m struct:s_packer_opts -interconnect ../../libarchfpga/include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_interconnect_pins -interconnect ../../libarchfpga/include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_pb_graph_edge -interconnect ../../libarchfpga/include/physical_types.h /^ t_interconnect *interconnect;$/;" m struct:s_mode -interconnect_pins ../../libarchfpga/include/physical_types.h /^ t_interconnect_pins ** interconnect_pins; \/* [0..num_modes-1][0..num_interconnect_in_mode] *\/$/;" m struct:s_pb_graph_node -interconnect_power ../../libarchfpga/include/physical_types.h /^ t_interconnect_power * interconnect_power;$/;" m struct:s_interconnect interconnect_printing ./base/verilog_writer.c /^void interconnect_printing(FILE *fp , conn_list *downhill)$/;" f interconnect_type_name ./power/power_util.c /^char * interconnect_type_name(enum e_interconnect type) {$/;" f intra_cluster_net_delay ./base/ReadOptions.h /^ float intra_cluster_net_delay;$/;" m struct:s_options intra_cluster_net_delay ./base/vpr_types.h /^ float intra_cluster_net_delay;$/;" m struct:s_packer_opts inv_capacity ./base/vpr_types.h /^ float inv_capacity;$/;" m struct:s_place_region inv_length ./base/vpr_types.h /^ float inv_length;$/;" m struct:s_rr_indexed_data -inv_prefix ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* inv_prefix; $/;" m struct:s_spice_model_port -inv_spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* inv_spice_model;$/;" m struct:s_spice_model_port -inv_spice_model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* inv_spice_model_name;$/;" m struct:s_spice_model_port invalid ./base/vpr_types.h /^ t_cluster_placement_primitive *invalid; \/* ptrs to primitives that are invalid *\/$/;" m struct:s_cluster_placement_stats invalidate_heap_entries ./route/route_common.c /^void invalidate_heap_entries(int sink_node, int ipin_node) {$/;" f invalidate_rr_graph_heap_entries ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void invalidate_rr_graph_heap_entries(t_rr_graph* local_rr_graph, $/;" f @@ -3691,62 +2742,39 @@ invalidate_screen ./base/graphics.c /^static void invalidate_screen(void)$/;" f io_line ./base/read_blif.c /^static void io_line(int in_or_out, int doall, t_model *io_model) {$/;" f file: io_nmos_subckt_name ./fpga_x2p/spice/spice_globals.c /^char* io_nmos_subckt_name = "vpr_io_nmos";$/;" v io_pmos_subckt_name ./fpga_x2p/spice/spice_globals.c /^char* io_pmos_subckt_name = "vpr_io_pmos";$/;" v -io_vdd ../../libarchfpga/fpga_spice_include/spice_types.h /^ float io_vdd;$/;" m struct:s_spice_tech_lib iopad_spice_model ./fpga_x2p/spice/spice_globals.c /^t_spice_model* iopad_spice_model = NULL;$/;" v iopad_verilog_model ./fpga_x2p/verilog/verilog_global.c /^t_spice_model* iopad_verilog_model = NULL;$/;" v -ipin_mux_trans_size ../../libarchfpga/include/physical_types.h /^ float ipin_mux_trans_size;$/;" m struct:s_arch ipin_mux_trans_size ./base/globals.c /^float ipin_mux_trans_size = 0;$/;" v ipin_rr_node ./base/vpr_types.h /^ t_rr_node*** ipin_rr_node;$/;" m struct:s_cb ipin_rr_node ./base/vpr_types.h /^ t_rr_node*** ipin_rr_node;$/;" m struct:s_sb ipin_rr_node_grid_side ./base/vpr_types.h /^ int** ipin_rr_node_grid_side; \/* We need to record the side of a IPIN, because a IPIN may locate on more than one sides *\/$/;" m struct:s_cb ipin_rr_node_grid_side ./base/vpr_types.h /^ int** ipin_rr_node_grid_side; \/* We need to record the side of a IPIN, because a IPIN may locate on more than one sides *\/$/;" m struct:s_sb ipin_rr_nodes_vpack_net_num_changed ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^boolean ipin_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes,$/;" f file: -ipow ../../libarchfpga/util.c /^int ipow(int base, int exp) {$/;" f isEchoFileEnabled ./base/ReadOptions.c /^boolean isEchoFileEnabled(enum e_echo_files echo_option) {$/;" f isFixed ./base/vpr_types.h /^ boolean isFixed;$/;" m struct:s_block -is_Fc_frac ../../libarchfpga/include/physical_types.h /^ boolean *is_Fc_frac; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -is_Fc_full_flex ../../libarchfpga/include/physical_types.h /^ boolean *is_Fc_full_flex; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -is_accurate ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_accurate;$/;" m struct:s_arch_mrfpga -is_anchored ../../pcre/SRC/pcre.c /^is_anchored(register const uschar *code, int *options, unsigned int bracket_map,$/;" f file: is_any_but ./timing/slre.c /^static int is_any_but(const unsigned char *p, int len, const char *s,$/;" f file: is_any_of ./timing/slre.c /^static int is_any_of(const unsigned char *p, int len, const char *s, int *ofs) {$/;" f file: -is_block_optional ../../libarchfpga/include/cad_types.h /^ boolean *is_block_optional; \/* [0..num_blocks-1] is the block_id in this pattern mandatory or optional to form a molecule *\/$/;" m struct:s_pack_patterns is_cb_exist ./fpga_x2p/base/fpga_x2p_utils.c /^boolean is_cb_exist(t_rr_type cb_type,$/;" f is_cbox ./route/rr_graph2.c /^boolean is_cbox(INP int chan, INP int seg, INP int track,$/;" f -is_chain ../../libarchfpga/include/cad_types.h /^ boolean is_chain; \/* Does this pattern chain across logic blocks *\/$/;" m struct:s_pack_patterns -is_clock ../../libarchfpga/include/logic_types.h /^ boolean is_clock; \/* clock? *\/$/;" m struct:s_model_ports -is_clock ../../libarchfpga/include/physical_types.h /^ boolean is_clock;$/;" m struct:s_port is_clock ./base/vpr_types.h /^ boolean is_clock;$/;" m struct:s_logical_block -is_config_enable ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean is_config_enable;$/;" m struct:s_spice_model_port is_const_gen ./base/vpr_types.h /^ boolean is_const_gen;$/;" m struct:s_net -is_counted_repeat ../../pcre/SRC/pcre.c /^is_counted_repeat(const uschar *p, compile_data *cd)$/;" f file: -is_default ../../libarchfpga/fpga_spice_include/spice_types.h /^ int is_default;$/;" m struct:s_spice_model is_des_rr_node_in_src_rr_node_edges ./route/pb_pin_eq_auto_detect.c /^boolean is_des_rr_node_in_src_rr_node_edges(t_rr_node* src_rr_node,$/;" f is_done_callibration ./power/PowerSpicedComponent.c /^bool PowerSpicedComponent::is_done_callibration(void) {$/;" f class:PowerSpicedComponent is_empty_heap ./route/route_common.c /^boolean is_empty_heap(void) {$/;" f -is_forced_connection ../../libarchfpga/include/physical_types.h /^ boolean is_forced_connection; \/* This output pin connects to one and only one input pin *\/$/;" m struct:s_pb_graph_pin is_forced_connection ./pack/cluster_feasibility_filter.c /^static boolean is_forced_connection(INP t_pb_graph_pin *pb_graph_pin) {$/;" f file: -is_global ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean is_global;$/;" m struct:s_spice_model_port is_global ./base/globals_declare.h /^boolean *is_global;$/;" v is_global ./base/vpr_types.h /^ boolean is_global;$/;" m struct:s_net -is_global_pin ../../libarchfpga/include/physical_types.h /^ boolean *is_global_pin; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor is_grid_coordinate_in_range ./fpga_x2p/base/fpga_x2p_utils.c /^boolean is_grid_coordinate_in_range(int x_min, $/;" f is_in_heap ./base/vpr_types.h /^ boolean is_in_heap;$/;" m struct:s_rr_node -is_isolation ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_isolation;$/;" m struct:s_arch_mrfpga is_isolation ./mrfpga/mrfpga_globals.c /^boolean is_isolation = FALSE;$/;" v -is_junction ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_junction;$/;" m struct:s_arch_mrfpga is_junction ./mrfpga/mrfpga_globals.c /^boolean is_junction = FALSE;$/;" v is_logical_blk_in_pb ./pack/cluster.c /^static boolean is_logical_blk_in_pb(int iblk, t_pb *pb) {$/;" f file: -is_mrFPGA ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_mrFPGA;$/;" m struct:s_arch_mrfpga is_mrFPGA ./mrfpga/mrfpga_globals.c /^boolean is_mrFPGA = FALSE;$/;" v is_net_in_cluster ./pack/cluster_legality.c /^static boolean is_net_in_cluster(INP int inet) {$/;" f file: is_net_pi ./fpga_x2p/base/fpga_x2p_utils.c /^boolean is_net_pi(t_net* cur_net) {$/;" f is_netlist_clock ./base/vpr_types.h /^ boolean is_netlist_clock; \/* Is this a netlist or virtual (external) clock? *\/$/;" m struct:s_clock -is_non_clock_global ../../libarchfpga/include/logic_types.h /^ boolean is_non_clock_global; \/* not a clock but is a special, global, control signal (eg global asynchronous reset, etc) *\/$/;" m struct:s_model_ports -is_non_clock_global ../../libarchfpga/include/physical_types.h /^ boolean is_non_clock_global;$/;" m struct:s_port is_number ./timing/read_sdc.c /^static boolean is_number(char * ptr) {$/;" f file: is_opin ./util/vpr_utils.c /^boolean is_opin(int ipin, t_type_ptr type) {$/;" f -is_opin_cblock_defined ../../libarchfpga/include/arch_types_mrfpga.h /^ int is_opin_cblock_defined;$/;" m struct:s_arch_mrfpga is_opin_in_direct_list ./route/pb_pin_eq_auto_detect.c /^boolean is_opin_in_direct_list(t_type_ptr cur_type_descriptor,$/;" f is_opt_set ./fpga_x2p/shell/read_opt.c /^boolean is_opt_set(t_opt_info* opts, char* opt_name, boolean default_val) {$/;" f is_parasitic_net ./base/vpr_types.h /^ boolean is_parasitic_net;$/;" m struct:s_rr_node @@ -3754,23 +2782,19 @@ is_pb_used_for_wiring ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^boolean is_pb_u is_pb_wired_lut ./fpga_x2p/base/fpga_x2p_lut_utils.c /^boolean is_pb_wired_lut(t_pb_graph_node* cur_pb_graph_node,$/;" f is_pin_open ./pack/cluster_legality.c /^boolean is_pin_open(int i) {$/;" f is_primitive_pb_type ./fpga_x2p/base/fpga_x2p_utils.c /^boolean is_primitive_pb_type(t_pb_type* cur_pb_type) {$/;" f -is_prog ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean is_prog;$/;" m struct:s_spice_model_port -is_reset ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean is_reset;$/;" m struct:s_spice_model_port is_rr_node_exist_opposite_side_in_sb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^int is_rr_node_exist_opposite_side_in_sb_info(t_sb cur_sb_info,$/;" f is_rr_node_to_be_disable_for_analysis ./fpga_x2p/verilog/verilog_sdc.c /^boolean is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node) {$/;" f is_sbox ./route/rr_graph2.c /^boolean is_sbox(INP int chan, INP int wire_seg, INP int sb_seg, INP int track,$/;" f -is_set ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean is_set;$/;" m struct:s_spice_model_port -is_show_pass_trans ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_show_pass_trans;$/;" m struct:s_arch_mrfpga is_show_pass_trans ./mrfpga/mrfpga_globals.c /^boolean is_show_sram = FALSE, is_show_pass_trans = FALSE;$/;" v -is_show_sram ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_show_sram;$/;" m struct:s_arch_mrfpga is_show_sram ./mrfpga/mrfpga_globals.c /^boolean is_show_sram = FALSE, is_show_pass_trans = FALSE;$/;" v -is_stack ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_stack;$/;" m struct:s_arch_mrfpga is_stack ./mrfpga/mrfpga_globals.c /^boolean is_stack = FALSE;$/;" v -is_startline ../../pcre/SRC/pcre.c /^is_startline(const uschar *code, unsigned int bracket_map,$/;" f file: is_swap2pins_match_prefer_side ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int is_swap2pins_match_prefer_side(int pin0_cur_side, int* pin0_prefer_side,$/;" f +is_two_cb_rr_nodes_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean is_two_cb_rr_nodes_mirror(t_cb* src_cb, t_cb* des_cb, $/;" f +is_two_connection_blocks_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean is_two_connection_blocks_mirror(t_cb* src, t_cb* des) {$/;" f +is_two_sb_rr_nodes_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean is_two_sb_rr_nodes_mirror(t_sb* src_sb, t_sb* des_sb, int side, $/;" f +is_two_switch_blocks_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean is_two_switch_blocks_mirror(t_sb* src, t_sb* des) {$/;" f is_type_pin_in_class ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int is_type_pin_in_class(t_type_ptr type,$/;" f is_verilog_and_spice_syntax_conflict_char ./fpga_x2p/base/fpga_x2p_setup.c /^boolean is_verilog_and_spice_syntax_conflict_char(t_llist* LL_reserved_syntax_char_head, $/;" f file: -is_wire_buffer ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_wire_buffer;$/;" m struct:s_arch_mrfpga is_wire_buffer ./mrfpga/mrfpga_globals.c /^boolean is_wire_buffer = FALSE;$/;" v is_wired_lut ./fpga_x2p/base/fpga_x2p_types.h /^ boolean* is_wired_lut; \/* Specify if this is a wired LUT (used as buffer) *\/$/;" m struct:fpga_spice_phy_pb ispressed ./base/graphics.c /^ bool ispressed;$/;" m struct:__anon4 file: @@ -3784,32 +2808,18 @@ label ./fpga_x2p/shell/shell_types.h /^ char* label; $/;" m struct:s_cmd_catego label_incoming_wires ./route/rr_graph2.c /^label_incoming_wires(INP int chan_num, INP int seg_num, INP int sb_seg,$/;" f file: label_wire_muxes ./route/rr_graph2.c /^label_wire_muxes(INP int chan_num, INP int seg_num,$/;" f file: label_wire_muxes_for_balance ./route/rr_graph2.c /^label_wire_muxes_for_balance(INP int chan_num, INP int seg_num,$/;" f file: -lcc ../../pcre/SRC/internal.h /^ const uschar *lcc; \/* Points to lower casing table *\/$/;" m struct:compile_data -lcc ../../pcre/SRC/internal.h /^ const uschar *lcc; \/* Points to lower casing table *\/$/;" m struct:match_data -lcc_offset ../../pcre/SRC/internal.h 653;" d -leakage ../../libarchfpga/include/physical_types.h /^ float leakage;$/;" m struct:s_power_usage -leakage_default_mode ../../libarchfpga/include/physical_types.h /^ int leakage_default_mode; \/* Default mode for leakage analysis, if block has no set mode *\/$/;" m struct:s_pb_type_power leakage_gate ./power/power.h /^ float leakage_gate;$/;" m struct:s_transistor_size_inf leakage_pairs ./power/power.h /^ t_power_nmos_leakage_pair * leakage_pairs;$/;" m struct:s_power_nmos_leakage_inf leakage_subthreshold ./power/power.h /^ float leakage_subthreshold;$/;" m struct:s_transistor_size_inf least_slack ./base/vpr_types.h /^ float ** least_slack;$/;" m struct:s_timing_stats legal_pos ./place/place.c /^static t_legal_pos **legal_pos = NULL; \/* [0..num_types-1][0..type_tsize - 1] *\/$/;" v file: -len ../../libarchfpga/include/ezxml.h /^ size_t len; \/* length of allocated memory for mmap, -1 for malloc *\/$/;" m struct:ezxml_root len ./timing/slre.c /^ int len; \/\/ Substring length$/;" m struct:cap file: -length ../../libarchfpga/include/physical_types.h /^ int length;$/;" m struct:s_segment_inf length ./base/vpr_types.h /^ int length;$/;" m struct:s_seg_details -level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int level;$/;" m struct:s_spice_model_wire_param level ./power/power.h /^ int level; \/* Level in the full multilevel mux - 0 = primary inputs to mux *\/$/;" m struct:s_mux_node level_restorer ./power/power.h /^ boolean level_restorer; \/* Whether the output of this mux is level restored *\/$/;" m struct:s_mux_node levels ./power/power.h /^ int levels;$/;" m struct:s_mux_arch -lib_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* lib_name; $/;" m struct:s_spice_model_port library_models ./base/vpr_types.h /^ t_model * library_models; \/* blif models in VPR *\/$/;" m struct:s_vpr_setup -limit_value ../../libarchfpga/util.c /^int limit_value(int cur, int max, const char *name) {$/;" f -line ../../libarchfpga/include/ezxml.h /^ int line;$/;" m struct:ezxml -line ../../libarchfpga/include/physical_types.h /^ int line;$/;" m struct:s_direct_inf line_fuz ./base/draw.c /^static float line_fuz = 0.3;$/;" v file: -line_num ../../libarchfpga/include/physical_types.h /^ int line_num; \/* Interconnect is processed later, need to know what line number it messed up on to give proper error message *\/$/;" m struct:s_interconnect -line_num ../../libarchfpga/include/physical_types.h /^ int line_num; \/* used to report what line number this annotation is found in architecture file *\/$/;" m struct:s_pin_to_pin_annotation line_types ./base/easygl_constants.h /^enum line_types {SOLID, DASHED};$/;" g link_one_pb_graph_node_pin_to_phy_pb_graph_pin ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void link_one_pb_graph_node_pin_to_phy_pb_graph_pin(t_pb_graph_pin* cur_pb_graph_pin, $/;" f link_pb_graph_node_pins_to_phy_pb_graph_pins ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void link_pb_graph_node_pins_to_phy_pb_graph_pins(t_pb_graph_node* cur_pb_graph_node, $/;" f @@ -3817,8 +2827,6 @@ linked_f_pointer_ch ./fpga_x2p/base/fpga_x2p_types.h /^ t_chunk linked_f_pointe linked_f_pointer_ch ./route/route_common.c /^static t_chunk linked_f_pointer_ch = {NULL, 0, NULL};$/;" v file: linked_f_pointer_free_head ./fpga_x2p/base/fpga_x2p_types.h /^ t_linked_f_pointer *linked_f_pointer_free_head;$/;" m struct:fpga_spice_rr_graph linked_f_pointer_free_head ./route/route_common.c /^static struct s_linked_f_pointer *linked_f_pointer_free_head = NULL;$/;" v typeref:struct:s_linked_f_pointer file: -list ../../libarchfpga/include/util.h /^ int *list;$/;" m struct:s_ivec -list_of_connectable_input_pin_ptrs ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_pin ***list_of_connectable_input_pin_ptrs; \/* [0..depth-1][0..num_connectable_primtive_input_pins-1] what input pins this output can connect to without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin load_best_buffer_list ./mrfpga/buffer_insertion.c /^void load_best_buffer_list( )$/;" f load_chan_rr_indices ./route/rr_graph2.c /^static void load_chan_rr_indices(INP int nodes_per_chan, INP int chan_len,$/;" f file: load_channel_occupancies ./base/stats.c /^static void load_channel_occupancies(int **chanx_occ, int **chany_occ) {$/;" f file: @@ -3866,9 +2874,7 @@ load_truth_table ./base/verilog_writer.c /^char *load_truth_table(int inputs , t load_uniform_switch_pattern ./route/rr_graph.c /^static void load_uniform_switch_pattern(INP t_type_ptr type,$/;" f file: load_wired_lut_pbs ./fpga_x2p/base/fpga_x2p_lut_utils.c /^void load_wired_lut_pbs(t_pb* lut_pb,$/;" f local_cross_count ./fpga_x2p/clb_pin_remap/post_place_timing.c /^static const float local_cross_count[50] = { \/* [0..49] *\/1.0, 1.0, 1.0, 1.0828, 1.1536, 1.2206, 1.2823, 1.3385, 1.3991, 1.4493, 1.4974,$/;" v file: -local_interc_factor ../../libarchfpga/include/physical_types.h /^ float local_interc_factor;$/;" m struct:s_power_arch local_nets ./base/vpr_types.h /^ struct s_net *local_nets; \/* Records post-packing connections, valid only for top-level *\/$/;" m struct:s_pb typeref:struct:s_pb::s_net -location_map ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* location_map;$/;" m struct:s_spice_model_buffer log_msg ./power/power_util.c /^static void log_msg(t_log * log_ptr, char * msg) {$/;" f file: logic_block_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* logic_block_spice_file_name = "grid_header.sp";$/;" v logic_block_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* logic_block_verilog_file_name = "logic_blocks.v";$/;" v @@ -3879,11 +2885,9 @@ logical_block_input_count ./base/read_blif.c /^static int *logical_block_input_c logical_block_output_count ./base/read_blif.c /^static int *logical_block_input_count, *logical_block_output_count;$/;" v file: logical_block_ptrs ./base/vpr_types.h /^ t_logical_block **logical_block_ptrs; \/* [0..num_blocks-1] ptrs to logical blocks that implements this molecule, index on pack_pattern_block->index of pack pattern *\/$/;" m struct:s_pack_molecule logical_block_types ./base/vpr_types.h /^enum logical_block_types {$/;" g -logical_effort_factor ../../libarchfpga/include/physical_types.h /^ float logical_effort_factor;$/;" m struct:s_power_arch logs ./power/power.h /^ t_log * logs;$/;" m struct:s_power_output long_trans_inf ./power/power.h /^ t_transistor_size_inf * long_trans_inf; \/* Long transistor (W=1,L=2) *\/$/;" m struct:s_transistor_inf longest_path_only ./fpga_x2p/verilog/verilog_report_timing.c /^ boolean longest_path_only;$/;" m struct:s_trpt_opts file: -longline ../../libarchfpga/include/physical_types.h /^ boolean longline;$/;" m struct:s_segment_inf longline ./base/vpr_types.h /^ boolean longline;$/;" m struct:s_seg_details lookahead_input_pins_used ./base/vpr_types.h /^ int **lookahead_input_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of input pins of this class that are speculatively used *\/$/;" m struct:s_pb_stats lookahead_output_pins_used ./base/vpr_types.h /^ int **lookahead_output_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of output pins of this class that are speculatively used *\/$/;" m struct:s_pb_stats @@ -3891,12 +2895,6 @@ lookup_dump ./place/timing_place_lookup.c /^static FILE *lookup_dump; \/* If deb loop_greedy ./timing/slre.c /^static void loop_greedy(const struct slre *r, int pc, const char *s, int len,$/;" f file: loop_non_greedy ./timing/slre.c /^static void loop_non_greedy(const struct slre *r, int pc, const char *s,$/;" f file: lowercase ./timing/slre.c /^static int lowercase(const char *s) {$/;" f file: -lut_frac_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int lut_frac_level;$/;" m struct:s_spice_model_port -lut_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_lut* lut_info;$/;" m struct:s_spice_model_design_tech_info -lut_input_buffer ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_input_buffer;$/;" m struct:s_spice_model -lut_input_inverter ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_input_inverter;$/;" m struct:s_spice_model -lut_intermediate_buffer ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_intermediate_buffer;$/;" m struct:s_spice_model -lut_output_mask ../../libarchfpga/fpga_spice_include/spice_types.h /^ int* lut_output_mask;$/;" m struct:s_spice_model_port lut_output_pb_graph_pin ./fpga_x2p/base/fpga_x2p_types.h /^ t_pb_graph_pin** lut_output_pb_graph_pin;$/;" m struct:fpga_spice_phy_pb lut_pin_remap ./base/vpr_types.h /^ int *lut_pin_remap; \/* [0..num_lut_inputs-1] applies only to LUT primitives, stores how LUT inputs were swapped during CAD flow, $/;" m struct:s_pb lut_pin_remap ./fpga_x2p/base/fpga_x2p_types.h /^ int *lut_pin_remap; \/* [0..num_lut_inputs-1] applies only to LUT primitives, stores how LUT inputs were swapped during CAD flow, $/;" m struct:fpga_spice_phy_pb @@ -3904,19 +2902,14 @@ lut_size ./base/ReadOptions.h /^ int lut_size;$/;" m struct:s_options lut_size ./fpga_x2p/base/fpga_x2p_types.h /^ int* lut_size;$/;" m struct:fpga_spice_phy_pb luts_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* luts_spice_file_name = "luts.sp";$/;" v luts_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* luts_verilog_file_name = "luts.v";$/;" v -m ../../libarchfpga/include/ezxml.h /^ char *m; \/* original xml string *\/$/;" m struct:ezxml_root -magic_number ../../pcre/SRC/internal.h /^ unsigned long int magic_number;$/;" m struct:real_pcre -main ../../libarchfpga/ezxml.c /^main(int argc,$/;" f -main ../../libarchfpga/main.c /^int main(int argc, char **argv) {$/;" f -main ../../pcre/SRC/main.c /^int main(int argc, char **argv)$/;" f main ./main.c /^int main(int argc, char **argv) {$/;" f main ./shell_main.c /^int main(int argc, char ** argv) {$/;" f main main.c /^int main(int argc, char **argv) {$/;" f main shell_main.c /^int main(int argc, char ** argv) {$/;" f -main_best_buffer_list ../../libarchfpga/include/arch_types_mrfpga.h /^ t_linked_int* main_best_buffer_list;$/;" m struct:s_arch_mrfpga main_best_buffer_list ./mrfpga/mrfpga_globals.c /^t_linked_int* main_best_buffer_list;$/;" v mandatory ./fpga_x2p/shell/read_opt_types.h /^ enum opt_manda mandatory;$/;" m struct:s_opt_info typeref:enum:s_opt_info::opt_manda map_button ./base/graphics.c /^static void map_button (int bnum) $/;" f file: +map_loop_breaker_onto_edges ./pack/pb_type_graph.c /^static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num,$/;" f file: map_pb_type_port_to_spice_model_ports ./fpga_x2p/base/fpga_x2p_setup.c /^int map_pb_type_port_to_spice_model_ports(t_pb_type* cur_pb_type,$/;" f file: mapped_spice_model ./base/vpr_types.h /^ t_spice_model* mapped_spice_model;$/;" m struct:s_logical_block mapped_spice_model_index ./base/vpr_types.h /^ int mapped_spice_model_index; \/* index of spice_model in completed FPGA netlist *\/$/;" m struct:s_logical_block @@ -3940,20 +2933,11 @@ mark_vpack_net_used_in_pb ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void mark_v mark_vpack_net_used_in_pb_pin ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void mark_vpack_net_used_in_pb_pin(t_pb* cur_op_pb, t_pb_graph_pin* cur_pb_graph_pin,$/;" f marked_blocks ./base/vpr_types.h /^ int *marked_nets, *marked_blocks;$/;" m struct:s_pb_stats marked_nets ./base/vpr_types.h /^ int *marked_nets, *marked_blocks;$/;" m struct:s_pb_stats -match ../../pcre/SRC/pcre.c /^match(register const uschar *eptr, register const uschar *ecode,$/;" f file: match ./timing/slre.c /^static const char *match(const struct slre *r, int pc, const char *s, int len,$/;" f file: match2 ./timing/slre.c /^static const char *match2(const struct slre *r, const char *buf, int len,$/;" f file: -match_call_count ../../pcre/SRC/internal.h /^ unsigned long int match_call_count; \/* As it says *\/$/;" m struct:match_data -match_condassert ../../pcre/SRC/pcre.c 172;" d file: -match_data ../../pcre/SRC/internal.h /^typedef struct match_data {$/;" s -match_data ../../pcre/SRC/internal.h /^} match_data;$/;" t typeref:struct:match_data -match_isgroup ../../pcre/SRC/pcre.c 173;" d file: -match_limit ../../pcre/SRC/internal.h /^ unsigned long int match_limit;\/* As it says *\/$/;" m struct:match_data -match_limit ../../pcre/SRC/pcre.h /^ unsigned long int match_limit; \/* Maximum number of calls to match() *\/$/;" m struct:pcre_extra match_pb_types_spice_model_rec ./fpga_x2p/base/fpga_x2p_setup.c /^void match_pb_types_spice_model_rec(t_pb_type* cur_pb_type,$/;" f file: match_pb_types_verilog_model_rec ./fpga_x2p/verilog/verilog_pbtypes.c /^void match_pb_types_verilog_model_rec(t_pb_type* cur_pb_type,$/;" f -match_ref ../../pcre/SRC/pcre.c /^match_ref(int offset, register const uschar *eptr, int length, match_data *md,$/;" f file: -match_xclass ../../pcre/SRC/pcre.c /^match_xclass(int c, const uschar *data)$/;" f file: +match_registers ./fpga_x2p/verilog/verilog_formality_autodeck.c /^static void match_registers(FILE *fp, char* chomped_circuit_name) {$/;" f file: max ./base/graphics.c 171;" d file: max ./mrfpga/mrfpga_util.h 6;" d max_IPIN_fanin ./power/power.h /^ int max_IPIN_fanin;$/;" m struct:s_power_commonly_used @@ -3962,10 +2946,8 @@ max_criticality ./base/ReadOptions.h /^ float max_criticality;$/;" m struct:s_op max_criticality ./base/vpr_types.h /^ float max_criticality;$/;" m struct:s_router_opts max_ext_index ./pack/cluster_legality.c /^ ext_clock_rr_node_index, max_ext_index;$/;" v file: max_index ./route/rr_graph.c /^ int max_index;$/;" m struct:s_mux_size_distribution file: -max_internal_delay ../../libarchfpga/include/physical_types.h /^ float max_internal_delay;$/;" m struct:s_pb_type max_len_pl_macros ./place/place_macro.c /^int max_len_pl_macros(int num_pl_macros, $/;" f max_mux_sl_size ./power/power.h /^ int max_mux_sl_size;$/;" m struct:s_power_nmos_mux_inf -max_pins_per_side ../../libarchfpga/include/arch_types_mrfpga.h /^ int max_pins_per_side;$/;" m struct:s_arch_mrfpga max_pins_per_side ./mrfpga/mrfpga_globals.c /^int max_pins_per_side;$/;" v max_router_iterations ./base/ReadOptions.h /^ int max_router_iterations;$/;" m struct:s_options max_router_iterations ./base/vpr_types.h /^ int max_router_iterations;$/;" m struct:s_router_opts @@ -3978,57 +2960,30 @@ max_sim_num_clock_cycles ./fpga_x2p/spice/spice_mux_testbench.c /^static int max max_sim_num_clock_cycles ./fpga_x2p/spice/spice_primitive_testbench.c /^static int max_sim_num_clock_cycles = 2;$/;" v file: max_sim_num_clock_cycles ./fpga_x2p/spice/spice_routing_testbench.c /^static int max_sim_num_clock_cycles = 2;$/;" v file: max_width_per_trans ./fpga_x2p/spice/spice_globals.c /^float max_width_per_trans = 5.;$/;" v -mc_params ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_mc_params mc_params;$/;" m struct:s_spice_params -mc_sim ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean mc_sim;$/;" m struct:s_spice_mc_params meas_header_file_name ./fpga_x2p/spice/spice_globals.c /^char* meas_header_file_name = "meas_params.sp";$/;" v -meas_params ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_meas_params meas_params;$/;" m struct:s_spice_params -mem_avail ../../libarchfpga/include/util.h /^ int mem_avail; \/* number of bytes left in the current chunk *\/$/;" m struct:s_chunk -mem_bank_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_mem_bank_info* mem_bank_info; \/* Only be allocated when orgz type is memory bank *\/$/;" m struct:s_sram_orgz_info -mem_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_mem_bank_info -mem_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_scff_info -mem_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_standalone_sram_info members ./place/place_macro.h /^ t_pl_macro_member* members;$/;" m struct:s_pl_macro -memcpy ../../pcre/SRC/internal.h 48;" d -memmove ../../pcre/SRC/internal.h 49;" d -memmove ../../pcre/SRC/internal.h 61;" d -memmove ../../pcre/SRC/internal.h 63;" d -memmove ../../pcre/SRC/internal.h 73;" d memories_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* memories_verilog_file_name = "memories.v";$/;" v memory_pool ./pack/cluster.c /^static struct s_molecule_link *memory_pool; \/*Declared here so I can free easily.*\/$/;" v typeref:struct:s_molecule_link file: -memristor_inf ../../libarchfpga/include/arch_types_mrfpga.h /^ t_memristor_inf memristor_inf;$/;" m struct:s_arch_mrfpga memristor_inf ./mrfpga/mrfpga_globals.c /^t_memristor_inf memristor_inf;$/;" v -memset ../../pcre/SRC/internal.h 50;" d menu ./base/graphics.c /^static Window toplevel, menu, textarea; \/* various windows *\/$/;" v file: menu_font_size ./base/graphics.c /^static const int menu_font_size = 12; \/* Font for menus and dialog boxes. *\/$/;" v file: menutext ./base/graphics.c /^static void menutext(Window win, int xc, int yc, const char *text) $/;" f file: -messagelogger ../../libarchfpga/include/util.h /^typedef unsigned char (*messagelogger)( TIO_MessageMode_t messageMode,$/;" t messages ./power/power.h /^ char ** messages;$/;" m struct:s_log meta_characters ./timing/slre.c /^static const char *meta_characters = "|.*+?()[\\\\";$/;" v file: min ./base/graphics.c 174;" d file: min ./mrfpga/mrfpga_util.h 10;" d -min_size ../../libarchfpga/include/logic_types.h /^ int min_size; \/* minimum number of pins *\/$/;" m struct:s_model_ports -min_width ../../libarchfpga/fpga_spice_include/spice_types.h /^ float min_width;$/;" m struct:s_spice_transistor_type +mirror ./base/vpr_types.h /^ t_cb* mirror; \/* an exact mirror of this connection block, with same connection & switches *\/$/;" m struct:s_cb +mirror ./base/vpr_types.h /^ t_sb* mirror; \/* an exact mirror of this switch block, with same connection & switches *\/$/;" m struct:s_sb mode ./base/vpr_types.h /^ int mode; \/* mode that this pb is set to *\/$/;" m struct:s_pb mode ./fpga_x2p/base/fpga_x2p_types.h /^ int mode; \/* mode that this pb is set to *\/$/;" m struct:fpga_spice_phy_pb -mode_bits ../../libarchfpga/include/physical_types.h /^ char* mode_bits; \/* Mode bits to select *\/$/;" m struct:s_pb_type mode_bits ./fpga_x2p/base/fpga_x2p_types.h /^ char* mode_bits; \/* Mode bits for the logical block *\/$/;" m struct:fpga_spice_phy_pb -mode_power ../../libarchfpga/include/physical_types.h /^ t_mode_power * mode_power;$/;" m struct:s_mode -mode_select ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean mode_select;$/;" m struct:s_spice_model_port -model ../../libarchfpga/include/cad_types.h /^ t_model *model; \/* block associated with chain *\/$/;" m struct:s_model_chain_pattern -model ../../libarchfpga/include/physical_types.h /^ t_model *model;$/;" m struct:s_pb_type model ./base/read_blif.c /^ t_model * model;$/;" m struct:s_model_stats file: model ./base/read_blif.c /^static char *model = NULL;$/;" v file: model ./base/vpr_types.h /^ t_model* model; \/* Technology-mapped type (eg. LUT, Flip-flop, memory slice, inpad, etc) *\/$/;" m struct:s_logical_block -model_library ../../libarchfpga/include/physical_types.h /^ t_model *model_library;$/;" m struct:s_arch model_lines ./base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: -model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* model_name;$/;" m struct:s_spice_transistor_type -model_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* model_netlist; \/* SPICE netlist provided by user *\/$/;" m struct:s_spice_model model_pin ./base/vpr_types.h /^ int model_port, model_pin; \/* technology mapped model pin *\/$/;" m struct:s_prepacked_tnode_data -model_port ../../libarchfpga/include/physical_types.h /^ t_model_ports *model_port;$/;" m struct:s_port model_port ./base/vpr_types.h /^ int model_port, model_pin; \/* technology mapped model pin *\/$/;" m struct:s_prepacked_tnode_data model_port_ptr ./base/vpr_types.h /^ t_model_ports *model_port_ptr;$/;" m struct:s_prepacked_tnode_data -model_ref ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* model_ref;$/;" m struct:s_spice_tech_lib -models ../../libarchfpga/include/physical_types.h /^ t_model *models;$/;" m struct:s_arch modelsim_autocheck_testbench_module_postfix ./fpga_x2p/verilog/verilog_global.c /^char* modelsim_autocheck_testbench_module_postfix = "_autocheck_top_tb";$/;" v modelsim_include_user_defined_verilog_netlists ./fpga_x2p/verilog/verilog_modelsim_autodeck.c /^void modelsim_include_user_defined_verilog_netlists(FILE* fp,$/;" f file: modelsim_ini_path ./base/vpr_types.h /^ char* modelsim_ini_path;$/;" m struct:s_syn_verilog_opts @@ -4037,7 +2992,6 @@ modelsim_project_name_postfix ./fpga_x2p/verilog/verilog_global.c /^char* models modelsim_simulation_time_unit ./fpga_x2p/verilog/verilog_global.c /^char* modelsim_simulation_time_unit = "ms";$/;" v modelsim_testbench_module_postfix ./fpga_x2p/verilog/verilog_global.c /^char* modelsim_testbench_module_postfix = "_top_tb";$/;" v modelsim_top_script_name_postfix ./fpga_x2p/verilog/verilog_global.c /^char* modelsim_top_script_name_postfix = "_runsim.tcl";$/;" v -modes ../../libarchfpga/include/physical_types.h /^ t_mode *modes; \/* [0..num_modes-1] *\/$/;" m struct:s_pb_type moleculeptr ./pack/cluster.c /^ t_pack_molecule *moleculeptr;$/;" m struct:s_molecule_link file: mouseclick_ptr ./base/graphics.c /^static void (*mouseclick_ptr)(float x, float y);$/;" v file: mousemove_ptr ./base/graphics.c /^static void (*mousemove_ptr)(float x, float y);$/;" v file: @@ -4050,54 +3004,23 @@ mux_basis_posfix ./fpga_x2p/spice/spice_globals.c /^char* mux_basis_posfix = "_b mux_count ./route/rr_graph.c /^ int mux_count;$/;" m struct:s_mux_size_distribution file: mux_find_selector_values ./power/power_util.c /^boolean mux_find_selector_values(int * selector_values, t_mux_node * mux_node,$/;" f mux_graph_head ./power/power.h /^ t_mux_node * mux_graph_head;$/;" m struct:s_mux_arch -mux_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_mux* mux_info;$/;" m struct:s_spice_model_design_tech_info mux_info ./power/power.h /^ std::map mux_info;$/;" m struct:s_power_commonly_used -mux_num_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int mux_num_level;$/;" m struct:s_spice_model_mux mux_size ./power/power.h /^ int mux_size;$/;" m struct:s_power_buffer_sc_levr_inf mux_special_basis_posfix ./fpga_x2p/spice/spice_globals.c /^char* mux_special_basis_posfix = "_special_basis";$/;" v -mux_trans_size ../../libarchfpga/include/physical_types.h /^ float mux_trans_size;$/;" m struct:s_switch_inf -mux_transistor_size ../../libarchfpga/include/physical_types.h /^ float mux_transistor_size;$/;" m struct:s_power_arch mux_voltage_inf ./power/power.h /^ t_power_mux_volt_inf * mux_voltage_inf;$/;" m struct:s_power_nmos_mux_inf mux_voltage_pairs ./power/power.h /^ t_power_mux_volt_pair * mux_voltage_pairs;$/;" m struct:s_power_mux_volt_inf muxes_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* muxes_spice_file_name = "muxes.sp";$/;" v muxes_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* muxes_verilog_file_name = "muxes.v";$/;" v my_atof_2D ./util/token.c /^void my_atof_2D(INOUTP float **matrix, INP int max_i, INP int max_j,$/;" f -my_atoi ../../libarchfpga/util.c /^int my_atoi(const char *str) {$/;" f -my_calloc ../../libarchfpga/util.c /^my_calloc(size_t nelem, size_t size) {$/;" f -my_chunk_malloc ../../libarchfpga/util.c /^my_chunk_malloc(size_t size, t_chunk *chunk_info) {$/;" f my_decimal2binary ./fpga_x2p/base/fpga_x2p_utils.c /^int* my_decimal2binary(int decimal,$/;" f -my_fgets ../../libarchfpga/util.c /^my_fgets(char *buf, int max_size, FILE * fp) {$/;" f -my_fopen ../../libarchfpga/util.c /^my_fopen(const char *fname, const char *flag, int prompt) {$/;" f -my_frand ../../libarchfpga/util.c /^float my_frand(void) {$/;" f -my_free ../../libarchfpga/read_xml_spice_util.c /^void my_free(void* ptr) {$/;" f my_gettime ./fpga_x2p/base/fpga_x2p_utils.c /^char* my_gettime() {$/;" f -my_irand ../../libarchfpga/util.c /^int my_irand(int imax) {$/;" f my_itoa ./fpga_x2p/base/fpga_x2p_utils.c /^char* my_itoa(int input) {$/;" f my_itobin ./fpga_x2p/base/fpga_x2p_utils.c /^char* my_itobin(int in_int, int bin_len) {$/;" f -my_malloc ../../libarchfpga/util.c /^my_malloc(size_t size) {$/;" f my_malloc ./base/graphics.c /^static void *my_malloc(int ibytes) {$/;" f file: -my_realloc ../../libarchfpga/util.c /^my_realloc(void *ptr, size_t size) {$/;" f my_realloc ./base/graphics.c /^static void *my_realloc(void *memblk, int ibytes) {$/;" f file: my_remove_file ./fpga_x2p/base/fpga_x2p_utils.c /^void my_remove_file(char* file_path) {$/;" f -my_srandom ../../libarchfpga/util.c /^void my_srandom(int seed) {$/;" f my_strcat ./fpga_x2p/base/fpga_x2p_utils.c /^char* my_strcat(char* str1,$/;" f my_strcmp ./fpga_x2p/shell/shell_utils.c /^int my_strcmp(char* str1, char* str2) {$/;" f -my_strdup ../../libarchfpga/util.c /^my_strdup(const char *str) {$/;" f -my_strncpy ../../libarchfpga/util.c /^my_strncpy(char *dest, const char *src, size_t size) {$/;" f -my_strtok ../../libarchfpga/util.c /^my_strtok(char *ptr, const char *tokens, FILE * fp, char *buf) {$/;" f -name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* name;$/;" m struct:s_spice_model -name ../../libarchfpga/include/cad_types.h /^ char *name; \/* name of this chain of logic *\/$/;" m struct:s_model_chain_pattern -name ../../libarchfpga/include/cad_types.h /^ char *name; \/* name of this logic model pattern *\/$/;" m struct:s_pack_patterns -name ../../libarchfpga/include/ezxml.h /^ char *name; \/* tag name *\/$/;" m struct:ezxml -name ../../libarchfpga/include/logic_types.h /^ char *name; \/* name of this logic model *\/$/;" m struct:s_model -name ../../libarchfpga/include/logic_types.h /^ char *name; \/* name of this port *\/$/;" m struct:s_model_ports -name ../../libarchfpga/include/physical_types.h /^ char *name;$/;" m struct:s_direct_inf -name ../../libarchfpga/include/physical_types.h /^ char *name;$/;" m struct:s_interconnect -name ../../libarchfpga/include/physical_types.h /^ char *name;$/;" m struct:s_switch_inf -name ../../libarchfpga/include/physical_types.h /^ char *name;$/;" m struct:s_type_descriptor -name ../../libarchfpga/include/physical_types.h /^ char* name;$/;" m struct:s_mode -name ../../libarchfpga/include/physical_types.h /^ char* name;$/;" m struct:s_pb_type -name ../../libarchfpga/include/physical_types.h /^ char* name;$/;" m struct:s_port name ./base/vpr_types.h /^ char * name; \/* I\/O port name with an SDC constraint *\/$/;" m struct:s_io name ./base/vpr_types.h /^ char * name;$/;" m struct:s_clock name ./base/vpr_types.h /^ char *name; \/* Name of this physical block *\/$/;" m struct:s_pb @@ -4113,15 +3036,8 @@ name ./fpga_x2p/shell/shell_types.h /^ e_cmd_category name;$/;" m struct:s_cmd_ name ./power/power.h /^ char * name;$/;" m struct:s_log name ./timing/read_sdc.c /^ char * name;$/;" m struct:s_sdc_clock file: name ./util/hash.h /^ char *name;$/;" m struct:s_hash -name_count ../../pcre/SRC/internal.h /^ unsigned short int name_count; \/* Number of name items *\/$/;" m struct:real_pcre -name_entry_size ../../pcre/SRC/internal.h /^ int name_entry_size; \/* Size of each entry *\/$/;" m struct:compile_data -name_entry_size ../../pcre/SRC/internal.h /^ unsigned short int name_entry_size; \/* Size of any name items; 0 => none *\/$/;" m struct:real_pcre -name_mux ../../libarchfpga/include/physical_types.h /^ char* name_mux;$/;" m struct:s_pb_graph_pin name_mux ./base/vpr_types.h /^ char* name_mux;$/;" m struct:s_rr_node -name_table ../../pcre/SRC/internal.h /^ uschar *name_table; \/* The name\/number table *\/$/;" m struct:compile_data name_type ./base/draw.c /^static const char *name_type[] = { "SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY",$/;" v file: -names_found ../../pcre/SRC/internal.h /^ int names_found; \/* Number of entries so far *\/$/;" m struct:compile_data -nelem ../../libarchfpga/include/util.h /^ int nelem;$/;" m struct:s_ivec net ./base/globals_declare.h /^struct s_net *net;$/;" v typeref:struct:s_net net ./fpga_x2p/base/fpga_x2p_types.h /^ t_net** net; \/* nets to route, this is pointer to the existing nets *\/$/;" m struct:fpga_spice_rr_graph net_cnt ./route/pb_pin_eq_auto_detect.c /^ int net_cnt;$/;" m struct:s_num_mapped_opins_stats file: @@ -4147,14 +3063,6 @@ netlist_ios ./timing/read_sdc.c /^char ** netlist_ios; \/* [0..num_netlist_clock nets ./base/vpr_types.h /^ int *nets;$/;" m struct:s_block nets_in_cluster ./pack/cluster_legality.c /^static int *nets_in_cluster; \/* [0..num_nets_in_cluster-1] *\/$/;" v file: nets_sink_index ./base/vpr_types.h /^ int* nets_sink_index;$/;" m struct:s_block -next ../../libarchfpga/fpga_spice_include/linkedlist.h /^ t_llist* next;$/;" m struct:s_llist -next ../../libarchfpga/include/cad_types.h /^ struct s_model_chain_pattern *next; \/* next chain (linked list) *\/$/;" m struct:s_model_chain_pattern typeref:struct:s_model_chain_pattern::s_model_chain_pattern -next ../../libarchfpga/include/cad_types.h /^ struct s_pack_pattern_connections *next;$/;" m struct:s_pack_pattern_connections typeref:struct:s_pack_pattern_connections::s_pack_pattern_connections -next ../../libarchfpga/include/ezxml.h /^ ezxml_t next; \/* next tag with same name in this section at this depth *\/$/;" m struct:ezxml -next ../../libarchfpga/include/logic_types.h /^ struct s_model *next; \/* next model (linked list) *\/$/;" m struct:s_model typeref:struct:s_model::s_model -next ../../libarchfpga/include/logic_types.h /^ struct s_model_ports *next; \/* next port *\/$/;" m struct:s_model_ports typeref:struct:s_model_ports::s_model_ports -next ../../libarchfpga/include/util.h /^ struct s_linked_int *next;$/;" m struct:s_linked_int typeref:struct:s_linked_int::s_linked_int -next ../../libarchfpga/include/util.h /^ struct s_linked_vptr *next;$/;" m struct:s_linked_vptr typeref:struct:s_linked_vptr::s_linked_vptr next ./base/place_and_route.h /^ struct s_fmap_cell *next;$/;" m struct:s_fmap_cell typeref:struct:s_fmap_cell::s_fmap_cell next ./base/verilog_writer.h /^ struct found_connectivity *next;$/;" m struct:found_connectivity typeref:struct:found_connectivity::found_connectivity next ./base/verilog_writer.h /^ struct found_pins *next;$/;" m struct:found_pins typeref:struct:found_pins::found_pins @@ -4173,13 +3081,9 @@ next ./timing/net_delay_types.h /^ struct s_rc_node *next;$/;" m union:s_rc_nod next ./timing/net_delay_types.h /^ struct s_linked_rc_edge *next;$/;" m struct:s_linked_rc_edge typeref:struct:s_linked_rc_edge::s_linked_rc_edge next ./timing/net_delay_types.h /^ struct s_linked_rc_ptr *next;$/;" m struct:s_linked_rc_ptr typeref:struct:s_linked_rc_ptr::s_linked_rc_ptr next ./util/hash.h /^ struct s_hash *next;$/;" m struct:s_hash typeref:struct:s_hash::s_hash -next_mem_loc_ptr ../../libarchfpga/include/util.h /^ char *next_mem_loc_ptr;\/* pointer to the first available (free) *$/;" m struct:s_chunk -next_primitive ../../libarchfpga/include/cad_types.h /^ struct s_cluster_placement_primitive *next_primitive;$/;" m struct:s_cluster_placement_primitive typeref:struct:s_cluster_placement_primitive::s_cluster_placement_primitive -nint ../../libarchfpga/include/util.h 24;" d nmos_leakage_info ./power/power.h /^ t_power_nmos_leakage_inf * nmos_leakage_info;$/;" m struct:s_power_tech nmos_mux_info ./power/power.h /^ t_power_nmos_mux_inf * nmos_mux_info;$/;" m struct:s_power_tech nmos_pmos_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* nmos_pmos_spice_file_name = "nmos_pmos.sp";$/;" v -nmos_size ../../libarchfpga/fpga_spice_include/spice_types.h /^ float nmos_size;$/;" m struct:s_spice_model_pass_gate_logic nmos_size ./power/power.h /^ float nmos_size;$/;" m struct:s_power_nmos_leakage_inf nmos_size ./power/power.h /^ float nmos_size;$/;" m struct:s_power_nmos_mux_inf nmos_subckt_name ./fpga_x2p/spice/spice_globals.c /^char* nmos_subckt_name = "vpr_nmos";$/;" v @@ -4187,18 +3091,10 @@ node_block ./base/vpr_types.h /^ int *node_block;$/;" m struct:s_net node_block_pin ./base/vpr_types.h /^ int *node_block_pin;$/;" m struct:s_net node_block_port ./base/vpr_types.h /^ int *node_block_port;$/;" m struct:s_net node_to_heap ./route/route_common.c /^void node_to_heap(int inode, float cost, int prev_node, int prev_edge,$/;" f -nominal_vdd ../../libarchfpga/fpga_spice_include/spice_types.h /^ float nominal_vdd;$/;" m struct:s_spice_tech_lib normalized_T_arr ./base/vpr_types.h /^ float normalized_T_arr; \/* arrival time (normalized with respect to max time) *\/$/;" m struct:s_prepacked_tnode_data normalized_slack ./base/vpr_types.h /^ float normalized_slack; \/* slack (normalized with respect to max slack) *\/$/;" m struct:s_prepacked_tnode_data normalized_total_critical_paths ./base/vpr_types.h /^ float normalized_total_critical_paths; \/* critical path count (normalized with respect to max count) *\/$/;" m struct:s_prepacked_tnode_data -notbol ../../pcre/SRC/internal.h /^ BOOL notbol; \/* NOTBOL flag *\/$/;" m struct:match_data -notempty ../../pcre/SRC/internal.h /^ BOOL notempty; \/* Empty string match not wanted *\/$/;" m struct:match_data -noteol ../../pcre/SRC/internal.h /^ BOOL noteol; \/* NOTEOL flag *\/$/;" m struct:match_data -num_annotations ../../libarchfpga/include/physical_types.h /^ int num_annotations;$/;" m struct:s_interconnect -num_annotations ../../libarchfpga/include/physical_types.h /^ int num_annotations;$/;" m struct:s_pb_type -num_bl ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_bl; \/* Number of Bit Lines in total *\/$/;" m struct:s_mem_bank_info num_blif_models ./base/read_blif.c /^static int num_blif_models;$/;" v file: -num_blocks ../../libarchfpga/include/cad_types.h /^ int num_blocks; \/* number of blocks in pattern *\/$/;" m struct:s_pack_patterns num_blocks ./base/globals.c /^int num_blocks = 0;$/;" v num_blocks ./base/globals_declare.h /^int num_nets, num_blocks;$/;" v num_blocks ./base/vpr_types.h /^ int num_blocks; \/* number of logical blocks of molecule *\/$/;" m struct:s_pack_molecule @@ -4206,34 +3102,23 @@ num_blocks ./place/place_macro.h /^ int num_blocks;$/;" m struct:s_pl_macro num_buttons ./base/graphics.c /^static int num_buttons = 0; \/* Number of menu buttons *\/$/;" v file: num_caps ./timing/slre.c /^ int num_caps; \/\/ Number of bracket pairs$/;" m struct:slre file: num_cb_buffers ./power/power.h /^ int num_cb_buffers;$/;" m struct:s_power_commonly_used -num_cb_switch ../../libarchfpga/include/physical_types.h /^ int num_cb_switch;$/;" m struct:s_arch num_cc_constraints ./base/vpr_types.h /^ int num_cc_constraints; \/* number of special-case clock-to-clock constraints overriding default, calculated, timing constraints *\/$/;" m struct:s_timing_constraints num_cf_constraints ./base/vpr_types.h /^ int num_cf_constraints; \/* number of special-case clock-to-flipflop constraints *\/$/;" m struct:s_timing_constraints num_child_blocks_in_pb ./base/vpr_types.h /^ int num_child_blocks_in_pb;$/;" m struct:s_pb_stats -num_class ../../libarchfpga/include/physical_types.h /^ int num_class;$/;" m struct:s_type_descriptor num_clb2clb_directs ./base/globals.c /^int num_clb2clb_directs = 0;$/;" v num_clock_names ./timing/read_sdc.c /^ int num_clock_names;$/;" m struct:s_sdc_exclusive_group file: -num_clock_pins ../../libarchfpga/include/physical_types.h /^ int *num_clock_pins; \/* [0..num_clock_ports - 1] *\/$/;" m struct:s_pb_graph_node -num_clock_pins ../../libarchfpga/include/physical_types.h /^ int num_clock_pins;$/;" m struct:s_pb_type -num_clock_ports ../../libarchfpga/include/physical_types.h /^ int num_clock_ports;$/;" m struct:s_pb_graph_node -num_clocks ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_clocks;$/;" m struct:s_spice_stimulate_params num_conf_bits ./base/vpr_types.h /^ int num_conf_bits;$/;" m struct:s_pb num_conf_bits ./fpga_x2p/base/fpga_x2p_types.h /^ int num_conf_bits;$/;" m struct:fpga_spice_phy_pb num_conf_bits_cbx ./fpga_x2p/base/fpga_x2p_globals.c /^int** num_conf_bits_cbx = NULL;$/;" v num_conf_bits_cby ./fpga_x2p/base/fpga_x2p_globals.c /^int** num_conf_bits_cby = NULL;$/;" v num_conf_bits_sb ./fpga_x2p/base/fpga_x2p_globals.c /^int** num_conf_bits_sb = NULL;$/;" v -num_connectable_primtive_input_pins ../../libarchfpga/include/physical_types.h /^ int *num_connectable_primtive_input_pins; \/* [0..depth-1] number of input pins that this output pin can reach without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin num_constrained_clocks ./base/vpr_types.h /^ int num_constrained_clocks; \/* number of clocks with timing constraints *\/$/;" m struct:s_timing_constraints num_constrained_inputs ./base/vpr_types.h /^ int num_constrained_inputs; \/* number of inputs with timing constraints *\/$/;" m struct:s_timing_constraints num_constrained_outputs ./base/vpr_types.h /^ int num_constrained_outputs; \/* number of outputs with timing constraints *\/$/;" m struct:s_timing_constraints num_critical_input_paths ./base/vpr_types.h /^ long num_critical_input_paths, num_critical_output_paths; \/* count of critical paths fanning into\/out of this tnode *\/$/;" m struct:s_prepacked_tnode_data num_critical_output_paths ./base/vpr_types.h /^ long num_critical_input_paths, num_critical_output_paths; \/* count of critical paths fanning into\/out of this tnode *\/$/;" m struct:s_prepacked_tnode_data -num_data_input ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_data_input; \/* Inputs for multiplexing datapath signals*\/ $/;" m struct:s_spice_mux_arch -num_delay_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_delay_info;$/;" m struct:s_spice_model -num_directs ../../libarchfpga/include/physical_types.h /^ int num_directs;$/;" m struct:s_arch num_drive_rr_nodes ./base/vpr_types.h /^ int num_drive_rr_nodes;$/;" m struct:s_rr_node num_driver ./base/read_blif.c /^static int *num_driver, *temp_num_pins;$/;" v file: -num_drivers ../../libarchfpga/include/physical_types.h /^ int num_drivers;$/;" m struct:s_type_descriptor num_edges ./base/vpr_types.h /^ int num_edges;$/;" m struct:s_tnode num_edges ./base/vpr_types.h /^ short num_edges;$/;" m struct:s_rr_node num_edges_head ./pack/pb_type_graph.c /^static struct s_linked_vptr *num_edges_head;$/;" v typeref:struct:s_linked_vptr file: @@ -4242,29 +3127,14 @@ num_ext_inputs_logical_block ./util/vpr_utils.c /^int num_ext_inputs_logical_blo num_fc_constraints ./base/vpr_types.h /^ int num_fc_constraints; \/* number of special-case flipflop-to-clock constraints *\/$/;" m struct:s_timing_constraints num_feasible_blocks ./base/vpr_types.h /^ int num_feasible_blocks; \/* [0..num_marked_models-1] *\/$/;" m struct:s_pb_stats num_ff_constraints ./base/vpr_types.h /^ int num_ff_constraints; \/* number of special-case flipflop-to-flipflop constraints *\/$/;" m struct:s_timing_constraints -num_global_clocks ../../libarchfpga/include/physical_types.h /^ int num_global_clocks;$/;" m struct:s_clock_arch -num_grid_loc_def ../../libarchfpga/include/physical_types.h /^ int num_grid_loc_def;$/;" m struct:s_type_descriptor num_heap_allocated ./fpga_x2p/base/fpga_x2p_types.h /^ int num_heap_allocated;$/;" m struct:fpga_spice_rr_graph num_heap_allocated ./route/route_common.c /^static int num_heap_allocated = 0;$/;" v file: -num_include_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_include_netlist;$/;" m struct:s_spice num_inpads ./base/vpr_types.h /^ int num_inpads;$/;" m struct:s_pb num_inpads ./fpga_x2p/base/fpga_x2p_types.h /^ int num_inpads;$/;" m struct:fpga_spice_phy_pb -num_input ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_input; \/* All Inputs including those connect to constant generator *\/$/;" m struct:s_spice_mux_arch -num_input_basis ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_input_basis;$/;" m struct:s_spice_mux_arch -num_input_edges ../../libarchfpga/include/physical_types.h /^ int num_input_edges;$/;" m struct:s_pb_graph_pin -num_input_last_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_input_last_level;$/;" m struct:s_spice_mux_arch -num_input_per_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int* num_input_per_level; \/* [0...num_level] *\/$/;" m struct:s_spice_mux_arch -num_input_pin_class ../../libarchfpga/include/physical_types.h /^ int num_input_pin_class; \/* number of pin classes that this input pb_graph_node has *\/$/;" m struct:s_pb_graph_node -num_input_pins ../../libarchfpga/include/physical_types.h /^ int *num_input_pins; \/* [0..num_input_ports - 1] *\/$/;" m struct:s_pb_graph_node -num_input_pins ../../libarchfpga/include/physical_types.h /^ int num_input_pins; \/* inputs not including clock pins *\/$/;" m struct:s_pb_type -num_input_pins ../../libarchfpga/include/physical_types.h /^ int num_input_pins;$/;" m struct:s_pb_graph_edge -num_input_ports ../../libarchfpga/include/physical_types.h /^ int num_input_ports;$/;" m struct:s_interconnect_power -num_input_ports ../../libarchfpga/include/physical_types.h /^ int num_input_ports;$/;" m struct:s_pb_graph_node num_inputs ./power/PowerSpicedComponent.h /^ int num_inputs;$/;" m class:PowerCallibInputs num_inputs ./power/power.h /^ int num_inputs; \/* Number of inputs *\/$/;" m struct:s_mux_node num_inputs ./power/power.h /^ int num_inputs;$/;" m struct:s_mux_arch num_inputs ./power/power.h /^ short num_inputs; \/* Number of inputs *\/$/;" m struct:s_rr_node_power -num_interconnect ../../libarchfpga/include/physical_types.h /^ int num_interconnect;$/;" m struct:s_mode num_iopads ./base/vpr_types.h /^ int num_iopads;$/;" m struct:s_pb num_iopads ./fpga_x2p/base/fpga_x2p_types.h /^ int num_iopads;$/;" m struct:fpga_spice_phy_pb num_ipin_rr_nodes ./base/vpr_types.h /^ int* num_ipin_rr_nodes; \/* Switch block has some inputs that are CLB IPIN*\/$/;" m struct:s_cb @@ -4272,7 +3142,6 @@ num_ipin_rr_nodes ./base/vpr_types.h /^ int* num_ipin_rr_nodes; \/* Switch bloc num_latches ./base/read_blif.c /^static int num_luts = 0, num_latches = 0, num_subckts = 0;$/;" v file: num_leakage_pairs ./power/power.h /^ int num_leakage_pairs;$/;" m struct:s_power_nmos_leakage_inf num_legal_pos ./place/place.c /^static int *num_legal_pos = NULL; \/* [0..num_legal_pos-1] *\/$/;" v file: -num_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_level;$/;" m struct:s_spice_mux_arch num_levr_entries ./power/power.h /^ int num_levr_entries;$/;" m struct:s_power_buffer_strength_inf num_linked_f_pointer_allocated ./fpga_x2p/base/fpga_x2p_types.h /^ int num_linked_f_pointer_allocated;$/;" m struct:fpga_spice_rr_graph num_linked_f_pointer_allocated ./route/route_common.c /^static int num_linked_f_pointer_allocated = 0;$/;" v file: @@ -4286,17 +3155,11 @@ num_mapped_opins ./base/vpr_types.h /^ int num_mapped_opins;$/;" m struct:s_n num_mapped_opins ./route/pb_pin_eq_auto_detect.c /^ int num_mapped_opins;$/;" m struct:s_num_mapped_opins_stats file: num_marked_blocks ./base/vpr_types.h /^ int num_marked_nets, num_marked_blocks;$/;" m struct:s_pb_stats num_marked_nets ./base/vpr_types.h /^ int num_marked_nets, num_marked_blocks;$/;" m struct:s_pb_stats -num_mc_points ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_mc_points;$/;" m struct:s_spice_mc_params -num_mem_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_mem_bank_info -num_mem_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_scff_info -num_mem_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_standalone_sram_info num_messages ./power/power.h /^ int num_messages;$/;" m struct:s_log num_mode_bits ./base/vpr_types.h /^ int num_mode_bits;$/;" m struct:s_pb num_mode_bits ./fpga_x2p/base/fpga_x2p_types.h /^ int num_mode_bits;$/;" m struct:fpga_spice_phy_pb -num_modes ../../libarchfpga/include/physical_types.h /^ int num_modes;$/;" m struct:s_pb_type num_moved_blocks ./place/place.c /^ int num_moved_blocks;$/;" m struct:s_pl_blocks_to_be_moved file: num_multicycles ./base/vpr_types.h /^ int num_multicycles;$/;" m struct:s_override_constraint -num_mux ../../libarchfpga/include/physical_types.h /^ int num_mux;$/;" m struct:s_interconnect num_netlist_clocks ./timing/read_sdc.c /^int num_netlist_clocks = 0; \/* number of clocks in netlist *\/$/;" v num_netlist_ios ./timing/read_sdc.c /^int num_netlist_ios = 0; \/* number of clocks in netlist *\/$/;" v num_nets ./base/globals.c /^int num_nets = 0;$/;" v @@ -4305,37 +3168,17 @@ num_nets ./fpga_x2p/base/fpga_x2p_types.h /^ int num_nets; \/* number of nets t num_nets_in_cluster ./pack/cluster_legality.c /^static int num_nets_in_cluster;$/;" v file: num_nmos_leakage_info ./power/power.h /^ int num_nmos_leakage_info;$/;" m struct:s_power_tech num_nmos_mux_info ./power/power.h /^ int num_nmos_mux_info;$/;" m struct:s_power_tech -num_normal_switch ../../libarchfpga/include/arch_types_mrfpga.h /^ short num_normal_switch;$/;" m struct:s_arch_mrfpga num_normal_switch ./mrfpga/mrfpga_globals.c /^short num_normal_switch;$/;" v num_opin_drivers ./base/vpr_types.h /^ int num_opin_drivers; \/* UDSD by WMF (could use "short") *\/$/;" m struct:s_rr_node num_opin_rr_nodes ./base/vpr_types.h /^ int* num_opin_rr_nodes; \/* Connection block has some outputs that are CLB OPIN *\/$/;" m struct:s_cb num_opin_rr_nodes ./base/vpr_types.h /^ int* num_opin_rr_nodes; \/* Connection block has some outputs that are CLB OPIN *\/$/;" m struct:s_sb num_outpads ./base/vpr_types.h /^ int num_outpads;$/;" m struct:s_pb num_outpads ./fpga_x2p/base/fpga_x2p_types.h /^ int num_outpads;$/;" m struct:fpga_spice_phy_pb -num_output_edges ../../libarchfpga/include/physical_types.h /^ int num_output_edges;$/;" m struct:s_pb_graph_pin -num_output_pin_class ../../libarchfpga/include/physical_types.h /^ int num_output_pin_class; \/* number of output pin classes that this pb_graph_node has *\/$/;" m struct:s_pb_graph_node -num_output_pins ../../libarchfpga/include/physical_types.h /^ int *num_output_pins; \/* [0..num_output_ports - 1] *\/$/;" m struct:s_pb_graph_node -num_output_pins ../../libarchfpga/include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_graph_edge -num_output_pins ../../libarchfpga/include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_type -num_output_ports ../../libarchfpga/include/physical_types.h /^ int num_output_ports;$/;" m struct:s_interconnect_power -num_output_ports ../../libarchfpga/include/physical_types.h /^ int num_output_ports;$/;" m struct:s_pb_graph_node num_p_inputs ./base/globals.c /^int num_p_inputs = 0, num_p_outputs = 0;$/;" v num_p_outputs ./base/globals.c /^int num_p_inputs = 0, num_p_outputs = 0;$/;" v -num_pack_patterns ../../libarchfpga/include/physical_types.h /^ int num_pack_patterns;$/;" m struct:s_pb_graph_edge -num_pb ../../libarchfpga/include/physical_types.h /^ int num_pb;$/;" m struct:s_pb_type -num_pb_type_children ../../libarchfpga/include/physical_types.h /^ int num_pb_type_children;$/;" m struct:s_mode num_pb_types ./base/vpr_types.h /^ int num_pb_types; \/* num primitive pb_types inside complex block *\/$/;" m struct:s_cluster_placement_stats -num_pin_loc_assignments ../../libarchfpga/include/physical_types.h /^ int **num_pin_loc_assignments; \/* [0..height-1][0..3] *\/$/;" m struct:s_type_descriptor -num_pin_timing ../../libarchfpga/include/physical_types.h /^ int num_pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin -num_pins ../../libarchfpga/include/physical_types.h /^ int num_pins;$/;" m struct:s_class -num_pins ../../libarchfpga/include/physical_types.h /^ int num_pins;$/;" m struct:s_port -num_pins ../../libarchfpga/include/physical_types.h /^ int num_pins;$/;" m struct:s_type_descriptor num_pins_of_net_in_pb ./base/vpr_types.h /^ std::map num_pins_of_net_in_pb;$/;" m struct:s_pb_stats -num_pins_per_port ../../libarchfpga/include/physical_types.h /^ int num_pins_per_port;$/;" m struct:s_interconnect_power num_pl_macros ./place/place.c /^static int num_pl_macros;$/;" v file: -num_port ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_port;$/;" m struct:s_spice_model -num_ports ../../libarchfpga/include/physical_types.h /^ int num_ports;$/;" m struct:s_pb_type -num_receivers ../../libarchfpga/include/physical_types.h /^ int num_receivers;$/;" m struct:s_type_descriptor num_reserved_conf_bits ./base/vpr_types.h /^ int num_reserved_conf_bits;$/;" m struct:s_pb num_reserved_conf_bits ./base/vpr_types.h /^ int num_reserved_conf_bits; \/* number of reserved configuration bits *\/$/;" m struct:s_cb num_reserved_conf_bits ./base/vpr_types.h /^ int num_reserved_conf_bits; \/* number of reserved configuration bits *\/$/;" m struct:s_sb @@ -4348,22 +3191,16 @@ num_rr_nodes ./base/globals.c /^int num_rr_nodes = 0;$/;" v num_rr_nodes ./base/globals_declare.h /^int num_rr_nodes;$/;" v num_rr_nodes ./fpga_x2p/base/fpga_x2p_types.h /^ int num_rr_nodes;$/;" m struct:fpga_spice_rr_graph num_sb_buffers ./power/power.h /^ int num_sb_buffers;$/;" m struct:s_power_commonly_used -num_scff ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_scff; \/* Number of Scan-chain flip-flops *\/$/;" m struct:s_scff_info num_segment ./base/vpr_types.h /^ int num_segment;$/;" m struct:s_det_routing_arch -num_segments ../../libarchfpga/include/physical_types.h /^ int num_segments;$/;" m struct:s_arch num_segments ./fpga_x2p/spice/spice_mux_testbench.c /^static int num_segments;$/;" v file: num_segments ./fpga_x2p/spice/spice_routing_testbench.c /^static int num_segments;$/;" v file: num_siblings ./base/vpr_types.h /^ int num_siblings;$/;" m struct:s_trace num_sides ./base/vpr_types.h /^ int num_sides; \/* Should be fixed to 4 *\/$/;" m struct:s_cb num_sides ./base/vpr_types.h /^ int num_sides; \/* Should be fixed to 4 *\/$/;" m struct:s_sb -num_sigma ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_sigma;$/;" m struct:s_spice_mc_variation_params -num_sim_clock_cycles ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_sim_clock_cycles;$/;" m struct:s_spicetb_info num_sink ./base/vpr_types.h /^ int num_sink;$/;" m struct:s_override_constraint num_sinks ./base/vpr_types.h /^ int num_sinks;$/;" m struct:s_net num_size_entries ./power/power.h /^ int num_size_entries;$/;" m struct:s_transistor_inf num_source ./base/vpr_types.h /^ int num_source;$/;" m struct:s_override_constraint -num_spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_spice_model;$/;" m struct:s_spice -num_sram ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_sram; \/* Number of SRAMs in total *\/$/;" m struct:s_standalone_sram_info num_strengths ./power/power.h /^ int num_strengths;$/;" m struct:s_power_buffer_size_inf num_subckts ./base/read_blif.c /^static int num_luts = 0, num_latches = 0, num_subckts = 0;$/;" v file: num_swap_aborted ./place/place.c /^static int num_swap_aborted = 0;$/;" v file: @@ -4371,16 +3208,12 @@ num_swap_accepted ./place/place.c /^static int num_swap_accepted = 0;$/;" v file num_swap_rejected ./place/place.c /^static int num_swap_rejected = 0;$/;" v file: num_switch ./base/vpr_types.h /^ short num_switch;$/;" m struct:s_det_routing_arch num_switch_inf ./fpga_x2p/base/fpga_x2p_types.h /^ int num_switch_inf;$/;" m struct:fpga_spice_rr_graph -num_switches ../../libarchfpga/include/physical_types.h /^ int num_switches;$/;" m struct:s_arch -num_swseg_pattern ../../libarchfpga/include/physical_types.h /^ int num_swseg_pattern;$/;" m struct:s_arch num_swseg_pattern ./base/vpr_types.h /^ int num_swseg_pattern; \/*Xifan TANG: Switch Segment Pattern Support*\/$/;" m struct:s_det_routing_arch -num_tedges ../../libarchfpga/fpga_spice_include/spice_types.h /^ int* num_tedges; \/* 1-D Array, show number of tedges of each pin *\/$/;" m struct:s_spice_model_port num_timing_nets ./timing/path_delay.c /^static int num_timing_nets = 0;$/;" v file: num_tnode_levels ./timing/path_delay2.c /^int num_tnode_levels; \/* Number of levels in the timing graph. *\/$/;" v num_tnodes ./timing/path_delay.c /^int num_tnodes = 0; \/* Number of nodes (pins) in the timing graph *\/$/;" v num_trace_allocated ./fpga_x2p/base/fpga_x2p_types.h /^ int num_trace_allocated; \/* To watch for memory leaks. *\/$/;" m struct:fpga_spice_rr_graph num_trace_allocated ./route/route_common.c /^static int num_trace_allocated = 0; \/* To watch for memory leaks. *\/$/;" v file: -num_transistor_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_transistor_type;$/;" m struct:s_spice_tech_lib num_ts_called ./place/place.c /^static int num_ts_called = 0;$/;" v file: num_types ./base/globals.c /^int num_types = 0;$/;" v num_types_backup ./place/timing_place_lookup.c /^static int num_types_backup;$/;" v file: @@ -4393,10 +3226,8 @@ num_used_io_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_io_tb = 0;$/;" v num_used_lut_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_lut_tb = 0;$/;" v num_used_sb_mux_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_sb_mux_tb = 0;$/;" v num_used_sb_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_sb_tb = 0;$/;" v -num_value_prop_pairs ../../libarchfpga/include/physical_types.h /^ int num_value_prop_pairs;$/;" m struct:s_pin_to_pin_annotation num_voltage_pairs ./power/power.h /^ int num_voltage_pairs;$/;" m struct:s_power_mux_volt_inf num_wire_drivers ./base/vpr_types.h /^ int num_wire_drivers; \/* UDSD by WMF *\/$/;" m struct:s_rr_node -num_wl ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_wl; \/* Number of Word Lines in total *\/$/;" m struct:s_mem_bank_info nx ./base/globals.c /^int nx = 0;$/;" v nx ./base/globals_declare.h /^int nx, ny;$/;" v ny ./base/globals.c /^int ny = 0;$/;" v @@ -4407,77 +3238,48 @@ object_start ./base/graphics.c /^void object_start(int all) { }$/;" f object_start ./base/graphics.c /^void object_start(int all) {$/;" f occ ./base/vpr_types.h /^ short occ;$/;" m struct:s_rr_node occupancy ./base/vpr_types.h /^ float occupancy;$/;" m struct:s_place_region -off ../../libarchfpga/include/ezxml.h /^ size_t off; \/* tag offset from start of parent tag character content *\/$/;" m struct:ezxml offset ./base/vpr_types.h /^ int offset;$/;" m struct:s_grid_tile -offset_end ../../pcre/SRC/internal.h /^ int offset_end; \/* One past the end *\/$/;" m struct:match_data -offset_max ../../pcre/SRC/internal.h /^ int offset_max; \/* The maximum usable for return data *\/$/;" m struct:match_data -offset_overflow ../../pcre/SRC/internal.h /^ BOOL offset_overflow; \/* Set if too many extractions *\/$/;" m struct:match_data -offset_save ../../pcre/SRC/internal.h /^ int *offset_save; \/* Pointer to start of saved offsets *\/$/;" m struct:recursion_info -offset_vector ../../pcre/SRC/internal.h /^ int *offset_vector; \/* Offset vector *\/$/;" m struct:match_data -offset_vector ../../pcre/SRC/pcre.h /^ int *offset_vector; \/* The offset vector *\/$/;" m struct:pcre_callout_block -offsetof ../../pcre/SRC/internal.h 173;" d +offset_chan ./base/vpr_types.h /^ int* offset_chan; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_cb +offset_chan ./base/vpr_types.h /^ int* offset_chan; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_sb +offset_ipin ./base/vpr_types.h /^ int* offset_ipin; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_cb +offset_ipin ./base/vpr_types.h /^ int* offset_ipin; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_sb +offset_opin ./base/vpr_types.h /^ int* offset_opin; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_cb +offset_opin ./base/vpr_types.h /^ int* offset_opin; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_sb old_num_rr_nodes ./base/draw.c /^static int old_num_rr_nodes = 0;$/;" v file: olines ./base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: -op_clock_freq ../../libarchfpga/fpga_spice_include/spice_types.h /^ float op_clock_freq; \/* Operation clock frequency*\/$/;" m struct:s_spice_stimulate_params -open ../../libarchfpga/ezxml.c 58;" d file: operator < ./power/PowerSpicedComponent.h /^ const bool operator<(const PowerCallibSize & rhs) {$/;" f class:PowerCallibSize opin_rr_node ./base/vpr_types.h /^ t_rr_node*** opin_rr_node;$/;" m struct:s_cb opin_rr_node ./base/vpr_types.h /^ t_rr_node*** opin_rr_node;$/;" m struct:s_sb opin_rr_node_grid_side ./base/vpr_types.h /^ int** opin_rr_node_grid_side; \/* We need to record the side of a OPIN, because a OPIN may locate on more than one sides *\/$/;" m struct:s_cb opin_rr_node_grid_side ./base/vpr_types.h /^ int** opin_rr_node_grid_side; \/* We need to record the side of a OPIN, because a OPIN may locate on more than one sides *\/$/;" m struct:s_sb -opin_switch ../../libarchfpga/include/physical_types.h /^ short opin_switch;$/;" m struct:s_segment_inf opin_switch ./base/vpr_types.h /^ short opin_switch;$/;" m struct:s_seg_details -opin_to_cb ../../libarchfpga/include/physical_types.h /^ boolean opin_to_cb;$/;" m struct:s_type_descriptor opin_to_wire_switch ./base/vpr_types.h /^ short opin_to_wire_switch; \/* mrFPGA: Xifan TANG*\/$/;" m struct:s_det_routing_arch opt_def ./fpga_x2p/shell/read_opt_types.h /^ enum opt_default opt_def;$/;" m struct:s_opt_info typeref:enum:s_opt_info::opt_default opt_default ./fpga_x2p/shell/read_opt_types.h /^enum opt_default {$/;" g opt_manda ./fpga_x2p/shell/read_opt_types.h /^enum opt_manda {$/;" g opt_val_type ./fpga_x2p/shell/read_opt_types.h /^enum opt_val_type {$/;" g opt_with_val ./fpga_x2p/shell/read_opt_types.h /^enum opt_with_val {$/;" g -options ../../pcre/SRC/internal.h /^ unsigned long int options;$/;" m struct:real_pcre -options ../../pcre/SRC/internal.h /^ uschar options;$/;" m struct:pcre_study_data options ./timing/slre.c /^ enum slre_option options;$/;" m struct:slre typeref:enum:slre::slre_option file: opts ./fpga_x2p/shell/read_opt_types.h /^ t_opt_info opts[];$/;" m struct:s_cmd_info opts ./fpga_x2p/shell/shell_types.h /^ t_opt_info* opts;$/;" m struct:s_shell_cmd -ord2utf8 ../../pcre/SRC/pcre.c /^ord2utf8(int cvalue, uschar *buffer)$/;" f file: -ordered ../../libarchfpga/include/ezxml.h /^ ezxml_t ordered; \/* next tag, same section and depth, in original order *\/$/;" m struct:ezxml ortho_cost_index ./base/vpr_types.h /^ int ortho_cost_index;$/;" m struct:s_rr_indexed_data out ./power/power.h /^ FILE * out;$/;" m struct:s_power_output out_edges ./base/vpr_types.h /^ t_tedge *out_edges; \/* [0..num_edges - 1] array of edges fanning out from this tnode.$/;" m struct:s_tnode -out_file_prefix ../../libarchfpga/util.c /^char *out_file_prefix = NULL;$/;" v out_file_prefix ./base/ReadOptions.h /^ char *out_file_prefix;$/;" m struct:s_options out_file_prefix ./base/vpr_types.h /^ char *out_file_prefix;$/;" m struct:s_file_name_opts -out_port_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* out_port_name;$/;" m struct:s_spice_model_delay_info -outer ../../pcre/SRC/internal.h /^ struct branch_chain *outer;$/;" m struct:branch_chain typeref:struct:branch_chain::branch_chain -outport_link_pin ../../libarchfpga/include/cad_types.h /^ int outport_link_pin; \/* applicable pin of chain output port *\/$/;" m struct:s_model_chain_pattern outputFileNames ./base/ReadOptions.c /^static char **outputFileNames = NULL;$/;" v file: output_blif ./pack/output_blif.c /^void output_blif (t_block *clb, int num_clusters, boolean global_clocks,$/;" f -output_buffer ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* output_buffer;$/;" m struct:s_spice_model output_clustering ./pack/output_clustering.c /^void output_clustering(t_block *clb, int num_clusters, boolean global_clocks,$/;" f -output_edges ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_edge** output_edges; \/* [0..num_output_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge output_file ./base/vpr_types.h /^ char *output_file;$/;" m struct:s_packer_opts -output_link_port ../../libarchfpga/include/cad_types.h /^ t_model_ports *output_link_port; \/* pointer to port of chain output *\/$/;" m struct:s_model_chain_pattern output_log ./power/power_util.c /^void output_log(t_log * log_ptr, FILE * fp) {$/;" f output_logs ./power/power_util.c /^void output_logs(FILE * fp, t_log * logs, int num_logs) {$/;" f output_net_tnodes ./base/vpr_types.h /^ struct s_tnode ***output_net_tnodes; \/* [0..num_output_ports-1][0..num_pins -1] correspnding output net tnode *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_tnode output_nets ./base/vpr_types.h /^ int **output_nets; \/* [0..num_output_ports-1][0..num_port_pins-1] List of output nets connected to this logical_block. *\/$/;" m struct:s_logical_block -output_pin_class_size ../../libarchfpga/include/physical_types.h /^ int *output_pin_class_size; \/* Stores the number of pins that belong to a particular output pin class *\/$/;" m struct:s_pb_graph_node -output_pins ../../libarchfpga/include/physical_types.h /^ char * output_pins;$/;" m struct:s_pin_to_pin_annotation -output_pins ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_pin *** output_pins; \/\/ [0..num_output_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin -output_pins ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin **output_pins; \/* [0..num_output_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node -output_pins ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin **output_pins;$/;" m struct:s_pb_graph_edge output_pins_used ./base/vpr_types.h /^ int **output_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of output pins of this class that are used *\/$/;" m struct:s_pb_stats -output_ports_eq_auto_detect ../../libarchfpga/include/physical_types.h /^ boolean output_ports_eq_auto_detect;$/;" m struct:s_type_descriptor -output_string ../../libarchfpga/include/physical_types.h /^ char *output_string;$/;" m struct:s_interconnect -output_thres_pct_fall ../../libarchfpga/fpga_spice_include/spice_types.h /^ float output_thres_pct_fall;$/;" m struct:s_spice_meas_params -output_thres_pct_rise ../../libarchfpga/fpga_spice_include/spice_types.h /^ float output_thres_pct_rise;$/;" m struct:s_spice_meas_params -outputs ../../libarchfpga/include/logic_types.h /^ t_model_ports *outputs; \/* linked list of output ports *\/$/;" m struct:s_model override_one_rr_node_for_top_primitive_phy_pb_graph_node ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void override_one_rr_node_for_top_primitive_phy_pb_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin,$/;" f pack_clb_pin_remap ./base/vpr_types.h /^ boolean pack_clb_pin_remap;$/;" m struct:s_packer_opts pack_intrinsic_cost ./base/vpr_types.h /^ float pack_intrinsic_cost;$/;" m struct:s_rr_node pack_pattern ./base/vpr_types.h /^ t_pack_patterns *pack_pattern; \/* If this is a forced_pack molecule, pattern this molecule matches *\/$/;" m struct:s_pack_molecule -pack_pattern_indices ../../libarchfpga/include/physical_types.h /^ int *pack_pattern_indices; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge -pack_pattern_names ../../libarchfpga/include/physical_types.h /^ char **pack_pattern_names; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge pack_route_time ./base/globals.c /^float pack_route_time = 0.;$/;" v packed_molecules ./base/vpr_types.h /^ struct s_linked_vptr *packed_molecules; \/* List of t_pack_molecules that this logical block is a part of *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_linked_vptr packer_algorithm ./base/ReadOptions.h /^ enum e_packer_algorithm packer_algorithm;$/;" m struct:s_options typeref:enum:s_options::e_packer_algorithm @@ -4485,141 +3287,50 @@ packer_algorithm ./base/vpr_types.h /^ enum e_packer_algorithm packer_algorithm; pad_loc_file ./base/vpr_types.h /^ char *pad_loc_file;$/;" m struct:s_placer_opts pad_loc_type ./base/vpr_types.h /^ enum e_pad_loc_type pad_loc_type;$/;" m struct:s_placer_opts typeref:enum:s_placer_opts::e_pad_loc_type parasitic_net_estimation ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void parasitic_net_estimation() {$/;" f file: -parent ../../libarchfpga/include/ezxml.h /^ ezxml_t parent; \/* parent tag, NULL if current tag is root tag *\/$/;" m struct:ezxml parent ./power/PowerSpicedComponent.h /^ PowerSpicedComponent * parent;$/;" m class:PowerCallibInputs -parent_mode ../../libarchfpga/include/physical_types.h /^ t_mode * parent_mode;$/;" m struct:s_interconnect -parent_mode ../../libarchfpga/include/physical_types.h /^ t_mode *parent_mode;$/;" m struct:s_pb_type -parent_mode_index ../../libarchfpga/include/physical_types.h /^ int parent_mode_index;$/;" m struct:s_interconnect -parent_node ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_node *parent_node;$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_node parent_node ./route/route_tree_timing.h /^ struct s_rt_node *parent_node;$/;" m struct:s_rt_node typeref:struct:s_rt_node::s_rt_node parent_pb ./base/vpr_types.h /^ struct s_pb *parent_pb; \/* pointer to parent node *\/$/;" m struct:s_pb typeref:struct:s_pb::s_pb parent_pb ./fpga_x2p/base/fpga_x2p_types.h /^ t_phy_pb *parent_pb; \/* pointer to parent node *\/$/;" m struct:fpga_spice_phy_pb -parent_pb_graph_node ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_node *parent_pb_graph_node;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node -parent_pb_type ../../libarchfpga/include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type -parent_pb_type ../../libarchfpga/include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_port typeref:struct:s_port::s_pb_type -parent_pin_class ../../libarchfpga/include/physical_types.h /^ int *parent_pin_class; \/* [0..depth-1] the grouping of pins that this particular pin belongs to *\/$/;" m struct:s_pb_graph_pin -parent_spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* parent_spice_model;$/;" m struct:s_conf_bit_info -parent_spice_model_index ../../libarchfpga/fpga_spice_include/spice_types.h /^ int parent_spice_model_index;$/;" m struct:s_conf_bit_info parent_switch ./route/route_tree_timing.h /^ short parent_switch;$/;" m struct:s_rt_node parse_direct_pin_name ./util/vpr_utils.c /^void parse_direct_pin_name(char * src_string, int line, int * start_pin_index, $/;" f partition ./fpga_x2p/base/quicksort.c /^int partition(int len, float* sort_value, int pivot_index) {$/;" f file: partition_index ./fpga_x2p/base/quicksort.c /^int partition_index(int len, int* sort_index, $/;" f file: -pass_gate_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_info;$/;" m struct:s_spice_model_design_tech_info -pass_gate_logic ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_logic;$/;" m struct:s_spice_model -path ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_model_netlist -path ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_tech_lib path_cost ./route/route_common.h /^ float path_cost;$/;" m struct:__anon15 path_criticality ./base/vpr_types.h /^ float ** path_criticality;$/;" m struct:s_slack pathfinder_update_cost ./route/route_common.c /^void pathfinder_update_cost(float pres_fac, float acc_fac) {$/;" f pathfinder_update_one_cost ./route/route_common.c /^void pathfinder_update_one_cost(struct s_trace *route_segment_start,$/;" f pathfinder_update_rr_graph_cost ./fpga_x2p/router/fpga_x2p_router.c /^void pathfinder_update_rr_graph_cost(t_rr_graph* local_rr_graph,$/;" f pathfinder_update_rr_graph_one_cost ./fpga_x2p/router/fpga_x2p_router.c /^void pathfinder_update_rr_graph_one_cost(t_rr_graph* local_rr_graph, $/;" f -pattern_index ../../libarchfpga/include/cad_types.h /^ int pattern_index; \/* index of pattern that this block is a part of *\/$/;" m struct:s_pack_pattern_block -pattern_length ../../libarchfpga/include/physical_types.h /^ int pattern_length;$/;" m struct:s_swseg_pattern_inf -patterns ../../libarchfpga/include/physical_types.h /^ boolean* patterns;$/;" m struct:s_swseg_pattern_inf pb ./base/verilog_writer.h /^ t_pb *pb;$/;" m struct:found_pins pb ./base/vpr_types.h /^ t_pb *pb;$/;" m struct:s_block pb ./base/vpr_types.h /^ t_pb* pb; \/* pb primitive that this block is packed into *\/$/;" m struct:s_logical_block pb ./base/vpr_types.h /^ t_pb* pb;$/;" m struct:s_rr_node -pb_graph_head ../../libarchfpga/include/physical_types.h /^ t_pb_graph_node *pb_graph_head;$/;" m struct:s_type_descriptor -pb_graph_node ../../libarchfpga/include/cad_types.h /^ t_pb_graph_node *pb_graph_node;$/;" m struct:s_cluster_placement_primitive pb_graph_node ./base/vpr_types.h /^ t_pb_graph_node *pb_graph_node; \/* pointer to pb_graph_node this pb corresponds to *\/$/;" m struct:s_pb pb_graph_node ./fpga_x2p/base/fpga_x2p_types.h /^ t_pb_graph_node *pb_graph_node; \/* pointer to pb_graph_node this pb corresponds to *\/$/;" m struct:fpga_spice_phy_pb pb_graph_pin ./base/vpr_types.h /^ t_pb_graph_pin *pb_graph_pin; \/* pb_graph_pin that this block is connected to *\/$/;" m struct:s_tnode pb_graph_pin ./base/vpr_types.h /^ t_pb_graph_pin *pb_graph_pin;$/;" m struct:s_rr_node pb_list ./base/verilog_writer.h /^}pb_list;$/;" t typeref:struct:found_pins pb_max_internal_delay ./base/globals.c /^float pb_max_internal_delay = UNDEFINED; \/* biggest internal delay of physical block *\/$/;" v -pb_node_power ../../libarchfpga/include/physical_types.h /^ t_pb_graph_node_power * pb_node_power;$/;" m struct:s_pb_graph_node pb_pin_density ./fpga_x2p/base/fpga_x2p_utils.c /^float pb_pin_density(t_rr_node* pb_rr_graph, $/;" f pb_pin_init_value ./fpga_x2p/base/fpga_x2p_utils.c /^int pb_pin_init_value(t_rr_node* pb_rr_graph, $/;" f pb_pin_net_num ./fpga_x2p/base/fpga_x2p_utils.c /^int pb_pin_net_num(t_rr_node* pb_rr_graph, $/;" f pb_pin_probability ./fpga_x2p/base/fpga_x2p_utils.c /^float pb_pin_probability(t_rr_node* pb_rr_graph, $/;" f pb_stats ./base/vpr_types.h /^ struct s_pb_stats *pb_stats; \/* statistics for current pb *\/$/;" m struct:s_pb typeref:struct:s_pb::s_pb_stats -pb_type ../../libarchfpga/include/cad_types.h /^ const t_pb_type *pb_type; \/* pb_type that this block is an instance of *\/$/;" m struct:s_pack_pattern_block -pb_type ../../libarchfpga/include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_type -pb_type ../../libarchfpga/include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_pb_type -pb_type_children ../../libarchfpga/include/physical_types.h /^ struct s_pb_type *pb_type_children; \/* [0..num_child_pb_types] *\/$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type -pb_type_power ../../libarchfpga/include/physical_types.h /^ t_pb_type_power * pb_type_power;$/;" m struct:s_pb_type -pb_types ../../libarchfpga/include/logic_types.h /^ struct s_linked_vptr *pb_types; \/* Physical block types that implement this model *\/$/;" m struct:s_model typeref:struct:s_model::s_linked_vptr pbtype_max_internal_delay ./base/globals.c /^const t_pb_type *pbtype_max_internal_delay = NULL; \/* physical block type with highest internal delay *\/$/;" v -pchars ../../pcre/SRC/pcre.c /^pchars(const uschar *p, int length, BOOL is_subject, match_data *md)$/;" f file: -pcre ../../pcre/SRC/pcre.h /^typedef struct real_pcre pcre;$/;" t typeref:struct:real_pcre -pcre_callout ../../pcre/SRC/pcre.c /^int (*pcre_callout)(pcre_callout_block *) = NULL;$/;" v -pcre_callout ../../pcre/SRC/pcre.h /^PCRE_DATA_SCOPE int (*pcre_callout)(pcre_callout_block *);$/;" v -pcre_callout_block ../../pcre/SRC/pcre.h /^typedef struct pcre_callout_block {$/;" s -pcre_callout_block ../../pcre/SRC/pcre.h /^} pcre_callout_block;$/;" t typeref:struct:pcre_callout_block -pcre_compile ../../pcre/SRC/pcre.c /^pcre_compile(const char *pattern, int options, const char **errorptr,$/;" f -pcre_config ../../pcre/SRC/pcre.c /^pcre_config(int what, void *where)$/;" f -pcre_copy_named_substring ../../pcre/SRC/get.c /^pcre_copy_named_substring(const pcre *code, const char *subject, int *ovector,$/;" f -pcre_copy_substring ../../pcre/SRC/get.c /^pcre_copy_substring(const char *subject, int *ovector, int stringcount,$/;" f -pcre_default_tables ../../pcre/SRC/chartables.h /^static unsigned char pcre_default_tables[] = {$/;" v -pcre_exec ../../pcre/SRC/pcre.c /^pcre_exec(const pcre *external_re, const pcre_extra *extra_data,$/;" f -pcre_extra ../../pcre/SRC/pcre.h /^typedef struct pcre_extra {$/;" s -pcre_extra ../../pcre/SRC/pcre.h /^} pcre_extra;$/;" t typeref:struct:pcre_extra -pcre_free ../../pcre/SRC/pcre.c /^void (*pcre_free)(void *) = free;$/;" v -pcre_free ../../pcre/SRC/pcre.h /^PCRE_DATA_SCOPE void (*pcre_free)(void *);$/;" v -pcre_free_substring ../../pcre/SRC/get.c /^pcre_free_substring(char *pointer)$/;" f -pcre_free_substring_list ../../pcre/SRC/get.c /^pcre_free_substring_list(const char **pointer)$/;" f -pcre_fullinfo ../../pcre/SRC/pcre.c /^pcre_fullinfo(const pcre *external_re, const pcre_extra *extra_data, int what,$/;" f -pcre_get_named_substring ../../pcre/SRC/get.c /^pcre_get_named_substring(const pcre *code, const char *subject, int *ovector,$/;" f -pcre_get_stringnumber ../../pcre/SRC/get.c /^pcre_get_stringnumber(const pcre *code, const char *stringname)$/;" f -pcre_get_substring ../../pcre/SRC/get.c /^pcre_get_substring(const char *subject, int *ovector, int stringcount,$/;" f -pcre_get_substring_list ../../pcre/SRC/get.c /^pcre_get_substring_list(const char *subject, int *ovector, int stringcount,$/;" f -pcre_info ../../pcre/SRC/pcre.c /^pcre_info(const pcre *external_re, int *optptr, int *first_byte)$/;" f -pcre_malloc ../../pcre/SRC/pcre.c /^void *(*pcre_malloc)(size_t) = malloc;$/;" v -pcre_malloc ../../pcre/SRC/pcre.h /^PCRE_DATA_SCOPE void *(*pcre_malloc)(size_t);$/;" v -pcre_memmove ../../pcre/SRC/internal.h /^pcre_memmove(unsigned char *dest, const unsigned char *src, size_t n)$/;" f -pcre_study_data ../../pcre/SRC/internal.h /^typedef struct pcre_study_data {$/;" s -pcre_study_data ../../pcre/SRC/internal.h /^} pcre_study_data;$/;" t typeref:struct:pcre_study_data -pcre_version ../../pcre/SRC/pcre.c /^pcre_version(void)$/;" f -peak ../../libarchfpga/include/physical_types.h /^ float peak;$/;" m struct:s_chan -period ../../libarchfpga/include/physical_types.h /^ float period; \/* Period of clock *\/$/;" m struct:s_clock_network period ./timing/read_sdc.c /^ float period;$/;" m struct:s_sdc_clock file: pfreq ./base/vpr_types.h /^enum pfreq {$/;" g -phy_mode_pin_rotate_offset_acc ../../libarchfpga/include/physical_types.h /^ int phy_mode_pin_rotate_offset_acc; \/* The pin number will rotate by an offset unit when mapping to physical modes *\/$/;" m struct:s_port phy_pb ./base/vpr_types.h /^ void* phy_pb;$/;" m struct:s_block phy_pb ./base/vpr_types.h /^ void* phy_pb;$/;" m struct:s_pb -phy_pb_type ../../libarchfpga/include/physical_types.h /^ struct s_pb_type* phy_pb_type;$/;" m struct:s_pb_type typeref:struct:s_pb_type::s_pb_type -phy_pb_type_port ../../libarchfpga/include/physical_types.h /^ t_port* phy_pb_type_port;$/;" m struct:s_port -phy_pb_type_port_lsb ../../libarchfpga/include/physical_types.h /^ int phy_pb_type_port_lsb;$/;" m struct:s_port -phy_pb_type_port_msb ../../libarchfpga/include/physical_types.h /^ int phy_pb_type_port_msb;$/;" m struct:s_port -physical_mode_name ../../libarchfpga/include/physical_types.h /^ char* physical_mode_name;$/;" m struct:s_pb_type -physical_mode_num_conf_bits ../../libarchfpga/include/physical_types.h /^ int physical_mode_num_conf_bits;$/;" m struct:s_pb_type -physical_mode_num_iopads ../../libarchfpga/include/physical_types.h /^ int physical_mode_num_iopads;$/;" m struct:s_pb_type -physical_mode_num_reserved_conf_bits ../../libarchfpga/include/physical_types.h /^ int physical_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type -physical_mode_pin ../../libarchfpga/include/physical_types.h /^ char* physical_mode_pin;$/;" m struct:s_port -physical_mode_pin_rotate_offset ../../libarchfpga/include/physical_types.h /^ int physical_mode_pin_rotate_offset; \/* The pin number will rotate by an offset unit when mapping to physical modes *\/$/;" m struct:s_port -physical_pb_graph_node ../../libarchfpga/include/physical_types.h /^ t_pb_graph_node* physical_pb_graph_node; \/* physical pb_graph_node *\/$/;" m struct:s_pb_graph_node -physical_pb_graph_pin ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin* physical_pb_graph_pin;$/;" m struct:s_pb_graph_pin -physical_pb_type_index_factor ../../libarchfpga/include/physical_types.h /^ float physical_pb_type_index_factor;$/;" m struct:s_pb_type -physical_pb_type_index_offset ../../libarchfpga/include/physical_types.h /^ int physical_pb_type_index_offset;$/;" m struct:s_pb_type -physical_pb_type_name ../../libarchfpga/include/physical_types.h /^ char* physical_pb_type_name;$/;" m struct:s_pb_type -pi ../../libarchfpga/include/ezxml.h /^ char ***pi; \/* processing instructions *\/$/;" m struct:ezxml_root pic_on_screen ./base/draw.c /^static enum pic_type pic_on_screen = NO_PICTURE; \/* What do I draw? *\/$/;" v typeref:enum:pic_type file: pic_type ./base/vpr_types.h /^enum pic_type {$/;" g pin_and_chan_adjacent ./route/check_route.c /^static int pin_and_chan_adjacent(int pin_node, int chan_node) {$/;" f file: -pin_class ../../libarchfpga/include/physical_types.h /^ int *pin_class; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -pin_class ../../libarchfpga/include/physical_types.h /^ int pin_class;$/;" m struct:s_pb_graph_pin -pin_count_in_cluster ../../libarchfpga/include/physical_types.h /^ int pin_count_in_cluster;$/;" m struct:s_pb_graph_pin pin_count_in_cluster ./pack/pb_type_graph.c /^static int pin_count_in_cluster;$/;" v file: pin_criticality ./place/timing_place_lookup.c /^static float *pin_criticality;$/;" v file: pin_dens ./power/power_util.c /^float pin_dens(t_pb * pb, t_pb_graph_pin * pin) {$/;" f -pin_height ../../libarchfpga/include/physical_types.h /^ int *pin_height; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -pin_index_per_side ../../libarchfpga/include/physical_types.h /^ int* pin_index_per_side;$/;" m struct:s_type_descriptor -pin_loc_assignments ../../libarchfpga/include/physical_types.h /^ char ****pin_loc_assignments; \/* [0..height-1][0..3][0..num_tokens-1][0..string_name] *\/$/;" m struct:s_type_descriptor -pin_location_distribution ../../libarchfpga/include/physical_types.h /^ enum e_pin_location_distr pin_location_distribution;$/;" m struct:s_type_descriptor typeref:enum:s_type_descriptor::e_pin_location_distr -pin_number ../../libarchfpga/include/physical_types.h /^ int pin_number;$/;" m struct:s_pb_graph_pin -pin_power ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin_power * pin_power;$/;" m struct:s_pb_graph_pin pin_prefer_side ./base/vpr_types.h /^ int** pin_prefer_side; \/* [0..num_pins-1][0..3] *\/$/;" m struct:s_block pin_prob ./power/power_util.c /^float pin_prob(t_pb * pb, t_pb_graph_pin * pin) {$/;" f -pin_ptc_to_side ../../libarchfpga/include/physical_types.h /^ int* pin_ptc_to_side;$/;" m struct:s_type_descriptor pin_side_count ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int pin_side_count(int pin_side[]) {$/;" f pin_size ./base/draw.c /^static float tile_width, pin_size;$/;" v file: -pin_timing ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_pin** pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin -pin_timing_del_max ../../libarchfpga/include/physical_types.h /^ float *pin_timing_del_max; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin -pin_toggle_initialized ../../libarchfpga/include/physical_types.h /^ boolean pin_toggle_initialized;$/;" m struct:s_port_power -pinlist ../../libarchfpga/include/physical_types.h /^ int *pinlist; \/* [0..num_pins - 1] *\/$/;" m struct:s_class -pinloc ../../libarchfpga/include/physical_types.h /^ int ***pinloc; \/* [0..height-1][0..3][0..num_pins-1] *\/$/;" m struct:s_type_descriptor pl_macros ./place/place.c /^static t_pl_macro * pl_macros = NULL;$/;" v file: place_algorithm ./base/vpr_types.h /^ enum e_place_algorithm place_algorithm;$/;" m struct:s_placer_opts typeref:enum:s_placer_opts::e_place_algorithm place_and_route ./base/place_and_route.c /^void place_and_route(enum e_operation operation,$/;" f @@ -4630,36 +3341,18 @@ place_cost_exp ./base/vpr_types.h /^ float place_cost_exp;$/;" m struct:s_placer place_exp_first ./base/ReadOptions.h /^ float place_exp_first;$/;" m struct:s_options place_exp_last ./base/ReadOptions.h /^ float place_exp_last;$/;" m struct:s_options place_freq ./base/vpr_types.h /^ enum pfreq place_freq;$/;" m struct:s_placer_opts typeref:enum:s_placer_opts::pfreq -placement_index ../../libarchfpga/include/physical_types.h /^ int placement_index;$/;" m struct:s_pb_graph_node -placement_index_in_top_node ../../libarchfpga/include/physical_types.h /^ int placement_index_in_top_node; \/* index at the top-level pb_graph node *\/$/;" m struct:s_pb_graph_node -pmos_size ../../libarchfpga/fpga_spice_include/spice_types.h /^ float pmos_size;$/;" m struct:s_spice_model_pass_gate_logic pmos_subckt_name ./fpga_x2p/spice/spice_globals.c /^char* pmos_subckt_name = "vpr_pmos";$/;" v -pn_ratio ../../libarchfpga/fpga_spice_include/spice_types.h /^ float pn_ratio;$/;" m struct:s_spice_tech_lib point_to_point_delay_cost ./place/place.c /^static float **point_to_point_delay_cost = NULL;$/;" v file: point_to_point_timing_cost ./place/place.c /^static float **point_to_point_timing_cost = NULL;$/;" v file: poly ./base/graphics.c /^ int poly[3][2]; $/;" m struct:__anon4 file: -port ../../libarchfpga/include/physical_types.h /^ t_port *port;$/;" m struct:s_pb_graph_pin -port_class ../../libarchfpga/include/physical_types.h /^ char * port_class;$/;" m struct:s_port -port_index_by_type ../../libarchfpga/include/physical_types.h /^ int port_index_by_type;$/;" m struct:s_port -port_info_initialized ../../libarchfpga/include/physical_types.h /^ boolean port_info_initialized;$/;" m struct:s_interconnect_power -port_power ../../libarchfpga/include/physical_types.h /^ t_port_power * port_power;$/;" m struct:s_port -ports ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_port* ports;$/;" m struct:s_spice_model -ports ../../libarchfpga/include/physical_types.h /^ t_port *ports; \/* [0..num_ports] *\/$/;" m struct:s_pb_type -posix_class_maps ../../pcre/SRC/pcre.c /^static const int posix_class_maps[] = {$/;" v file: -posix_name_lengths ../../pcre/SRC/pcre.c /^static const uschar posix_name_lengths[] = {$/;" v file: -posix_names ../../pcre/SRC/pcre.c /^static const char *posix_names[] = {$/;" v file: -post ../../libarchfpga/fpga_spice_include/spice_types.h /^ int post;$/;" m struct:s_spice_params post_place_sync ./base/place_and_route.c /^void post_place_sync(INP int L_num_blocks,$/;" f postscript ./base/graphics.c /^postscript (void (*drawscreen) (void)) $/;" f file: -power ../../libarchfpga/include/physical_types.h /^ t_power_arch * power;$/;" m struct:s_arch power ./power/PowerSpicedComponent.h /^ float power;$/;" m class:PowerCallibSize power_MTAs ./power/power_sizing.c /^static double power_MTAs(float W_size) {$/;" f file: power_MTAs_L ./power/power_sizing.c /^static double power_MTAs_L(float L_size) {$/;" f file: power_add_usage ./power/power_util.c /^void power_add_usage(t_power_usage * dest, const t_power_usage * src) {$/;" f power_alloc_and_init_pb_pin ./power/power.c /^void power_alloc_and_init_pb_pin(t_pb_graph_pin * pin) {$/;" f -power_buffer_size ../../libarchfpga/include/physical_types.h /^ float power_buffer_size;$/;" m struct:s_switch_inf power_buffer_size_from_logical_effort ./power/power_util.c /^float power_buffer_size_from_logical_effort(float C_load) {$/;" f -power_buffer_type ../../libarchfpga/include/physical_types.h /^ e_power_buffer_type power_buffer_type;$/;" m struct:s_switch_inf power_calc_buffer_num_stages ./power/power_util.c /^int power_calc_buffer_num_stages(float final_stage_size,$/;" f power_calc_buffer_size_from_Cout ./power/power_lowlevel.c /^float power_calc_buffer_size_from_Cout(float C_out) {$/;" f power_calc_leakage_gate ./power/power_lowlevel.c /^static float power_calc_leakage_gate(e_tx_type transistor_type, float size) {$/;" f file: @@ -4701,13 +3394,11 @@ power_find_buffer_strength_inf ./power/power_cmos_tech.c /^void power_find_buffe power_find_mux_volt_inf ./power/power_cmos_tech.c /^void power_find_mux_volt_inf(t_power_mux_volt_pair ** lower,$/;" f power_find_nmos_leakage ./power/power_cmos_tech.c /^void power_find_nmos_leakage(t_power_nmos_leakage_inf * nmos_leakage_info,$/;" f power_find_transistor_info ./power/power_cmos_tech.c /^boolean power_find_transistor_info(t_transistor_size_inf ** lower,$/;" f -power_gated ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean power_gated;$/;" m struct:s_spice_model_design_tech_info power_get_mux_arch ./power/power_util.c /^t_mux_arch * power_get_mux_arch(int num_mux_inputs, float transistor_size) {$/;" f power_init ./power/power.c /^boolean power_init(char * power_out_filepath,$/;" f power_init_pb_pins_rec ./power/power.c /^void power_init_pb_pins_rec(t_pb_graph_node * pb_node) {$/;" f power_log_msg ./power/power_util.c /^void power_log_msg(e_power_log_type log_type, char * msg) {$/;" f power_lowlevel_init ./power/power_lowlevel.c /^void power_lowlevel_init() {$/;" f -power_method_inherited ../../libarchfpga/read_xml_arch_file.c /^e_power_estimation_method power_method_inherited($/;" f power_method_is_recursive ./power/power_util.c /^boolean power_method_is_recursive(e_power_estimation_method method) {$/;" f power_method_is_transistor_level ./power/power_util.c /^boolean power_method_is_transistor_level($/;" f power_mux_node_max_inputs ./power/power_sizing.c /^static void power_mux_node_max_inputs(t_mux_node * mux_node,$/;" f file: @@ -4742,15 +3433,11 @@ power_transistor_area ./power/power_sizing.c /^double power_transistor_area(doub power_transistors_for_pb_node ./power/power_sizing.c /^static double power_transistors_for_pb_node(t_pb_graph_node * pb_node) {$/;" f file: power_transistors_per_tile ./power/power_sizing.c /^static double power_transistors_per_tile(t_arch * arch) {$/;" f file: power_uninit ./power/power.c /^boolean power_uninit(void) {$/;" f -power_usage ../../libarchfpga/include/physical_types.h /^ t_power_usage power_usage; \/* Power usage of this mode *\/$/;" m struct:s_mode_power -power_usage ../../libarchfpga/include/physical_types.h /^ t_power_usage power_usage; \/* Total power usage of this pb type *\/$/;" m struct:s_pb_type_power -power_usage ../../libarchfpga/include/physical_types.h /^ t_power_usage power_usage;$/;" m struct:s_interconnect_power power_usage_MUX2_transmission ./power/power_lowlevel.c /^void power_usage_MUX2_transmission(t_power_usage * power_usage, float size,$/;" f power_usage_blocks ./power/power.c /^static void power_usage_blocks(t_power_usage * power_usage) {$/;" f file: power_usage_buf_for_callibration ./power/power_callibrate.c /^float power_usage_buf_for_callibration(int num_inputs, float transistor_size) {$/;" f power_usage_buf_levr_for_callibration ./power/power_callibrate.c /^float power_usage_buf_levr_for_callibration(int num_inputs,$/;" f power_usage_buffer ./power/power_components.c /^void power_usage_buffer(t_power_usage * power_usage, float size, float in_prob,$/;" f -power_usage_bufs_wires ../../libarchfpga/include/physical_types.h /^ t_power_usage power_usage_bufs_wires; \/* Power dissipated in local buffers and wire switching (Subset of total power) *\/$/;" m struct:s_pb_type_power power_usage_clock ./power/power.c /^static void power_usage_clock(t_power_usage * power_usage,$/;" f file: power_usage_clock_single ./power/power.c /^static void power_usage_clock_single(t_power_usage * power_usage,$/;" f file: power_usage_ff ./power/power_components.c /^void power_usage_ff(t_power_usage * power_usage, float size, float D_prob,$/;" f @@ -4775,15 +3462,11 @@ power_usage_routing ./power/power.c /^static void power_usage_routing(t_power_us power_usage_wire ./power/power_lowlevel.c /^void power_usage_wire(t_power_usage * power_usage, float capacitance,$/;" f power_zero_usage ./power/power_util.c /^void power_zero_usage(t_power_usage * power_usage) {$/;" f prefer_side ./base/vpr_types.h /^ int** prefer_side; \/* [0..num_sinks][0..3] *\/$/;" m struct:s_net -prefix ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* prefix; $/;" m struct:s_spice_model_port -prefix ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* prefix; \/* Prefix when it show up in the spice netlist *\/$/;" m struct:s_spice_model prepacked_data ./base/vpr_types.h /^ t_prepacked_tnode_data * prepacked_data;$/;" m struct:s_tnode pres_cost ./route/route_common.h /^ float pres_cost;$/;" m struct:__anon15 pres_fac ./pack/cluster_legality.c /^static float pres_fac;$/;" v file: pres_fac_mult ./base/ReadOptions.h /^ float pres_fac_mult;$/;" m struct:s_options pres_fac_mult ./base/vpr_types.h /^ float pres_fac_mult;$/;" m struct:s_router_opts -prev ../../pcre/SRC/internal.h /^ struct recursion_info *prev; \/* Previous recursion record (or NULL) *\/$/;" m struct:recursion_info typeref:struct:recursion_info::recursion_info -prev ../../pcre/SRC/pcre.c /^ struct eptrblock *prev;$/;" m struct:eptrblock typeref:struct:eptrblock::eptrblock file: prev_edge ./base/vpr_types.h /^ int prev_edge;$/;" m struct:s_rr_node prev_edge ./route/route_common.h /^ int prev_edge;$/;" m struct:s_heap prev_edge ./route/route_common.h /^ short prev_edge;$/;" m struct:__anon15 @@ -4811,12 +3494,12 @@ print_criticality ./timing/path_delay.c /^void print_criticality(t_slack * slack print_distribution ./route/rr_graph.c /^print_distribution(FILE * fptr,$/;" f file: print_formal_verification_top_netlist ./base/vpr_types.h /^ boolean print_formal_verification_top_netlist;$/;" m struct:s_syn_verilog_opts print_global_criticality_stats ./timing/path_delay.c /^static void print_global_criticality_stats(FILE * fp, float ** criticality, const char * singular_name, const char * capitalized_plural_name) {$/;" f file: -print_help ../../libarchfpga/main.c /^void print_help() {$/;" f print_input_blif_testbench ./base/vpr_types.h /^ boolean print_input_blif_testbench;$/;" m struct:s_syn_verilog_opts -print_int_matrix3 ../../libarchfpga/util.c /^void print_int_matrix3(int ***vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f print_interconnect ./pack/output_clustering.c /^static void print_interconnect(int inode, int *column, int num_tabs,$/;" f file: print_lambda ./base/stats.c /^void print_lambda(void) {$/;" f print_lut_remapping ./timing/path_delay.c /^void print_lut_remapping(const char *fname) {$/;" f +print_mirror_connection_block_stats ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void print_mirror_connection_block_stats() {$/;" f +print_mirror_switch_block_stats ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void print_mirror_switch_block_stats() {$/;" f print_modelsim_autodeck ./base/vpr_types.h /^ boolean print_modelsim_autodeck;$/;" m struct:s_syn_verilog_opts print_net_delay ./timing/path_delay.c /^void print_net_delay(float **net_delay, const char *fname) {$/;" f print_net_name ./pack/output_blif.c /^static void print_net_name(int inet, int *column, FILE * fpout) {$/;" f file: @@ -4857,10 +3540,7 @@ print_timing_stats ./timing/path_delay.c /^void print_timing_stats(void) {$/;" f print_top_testbench ./base/vpr_types.h /^ boolean print_top_testbench;$/;" m struct:s_syn_verilog_opts print_user_defined_template ./base/vpr_types.h /^ boolean print_user_defined_template;$/;" m struct:s_syn_verilog_opts print_wirelen_prob_dist ./base/stats.c /^void print_wirelen_prob_dist(void) {$/;" f -priority ../../libarchfpga/include/physical_types.h /^ int priority;$/;" m struct:s_grid_loc_def private_cmap ./base/graphics.c /^static Colormap private_cmap; \/* "None" unless a private cmap was allocated. *\/$/;" v file: -prob ../../libarchfpga/include/physical_types.h /^ float prob; \/* Static probability of net assigned to this clock *\/$/;" m struct:s_clock_network -probability ../../libarchfpga/fpga_spice_include/spice_types.h /^ float probability;$/;" m struct:s_spice_net_info probability ./base/vpr_types.h /^ float probability;$/;" m struct:s_net_power proc_time ./base/place_and_route.h /^ int proc_time;$/;" m struct:s_fmap_cell proceed ./base/graphics.c /^proceed (void (*drawscreen) (void)) $/;" f file: @@ -4874,8 +3554,6 @@ process_int_arg ./fpga_x2p/shell/read_opt.c /^int process_int_arg(INP char* arg) process_settings ./base/read_settings.c /^static int process_settings(ezxml_t Cur, char ** outv)$/;" f file: process_shell_command ./fpga_x2p/shell/shell_utils.c /^void process_shell_command(char* line, t_shell_env* env) {$/;" f process_tech_xml_load_transistor_info ./power/power_cmos_tech.c /^static void process_tech_xml_load_transistor_info(ezxml_t parent) {$/;" f file: -prog_clock_freq ../../libarchfpga/fpga_spice_include/spice_types.h /^ float prog_clock_freq; \/* Programming clock frequency, used during programming phase only *\/$/;" m struct:s_spice_stimulate_params -prop ../../libarchfpga/include/physical_types.h /^ int * prop; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation propagate_clock_domain_and_skew ./timing/path_delay.c /^static void propagate_clock_domain_and_skew(int inode) {$/;" f file: ps ./base/graphics.c /^static FILE *ps;$/;" v file: ps_bot ./base/graphics.c /^static float ps_left, ps_right, ps_top, ps_bot; \/* Figure boundaries for *$/;" v file: @@ -4891,8 +3569,6 @@ pt_on_object ./base/graphics.c /^int pt_on_object(float x, float y) { }$/;" f pt_on_object ./base/graphics.c /^int pt_on_object(int all, float x, float y) {$/;" f ptc_num ./base/vpr_types.h /^ short ptc_num;$/;" m struct:s_rr_node ptr ./timing/slre.c /^ const char *ptr; \/\/ Pointer to the substring$/;" m struct:cap file: -pwh ../../libarchfpga/fpga_spice_include/spice_types.h /^ float pwh;$/;" m struct:s_spice_net_info -pwl ../../libarchfpga/fpga_spice_include/spice_types.h /^ float pwl;$/;" m struct:s_spice_net_info quantifier ./timing/slre.c /^static void quantifier(struct slre *r, int prev, int op) {$/;" f file: quicksort_float ./fpga_x2p/base/quicksort.c /^void quicksort_float(int len, $/;" f quicksort_float_index ./fpga_x2p/base/quicksort.c /^void quicksort_float_index(int len, $/;" f @@ -4900,7 +3576,6 @@ quit ./base/graphics.c /^quit (void (*drawscreen) (void)) $/;" f file: random_top_testbench_verilog_file_postfix ./fpga_x2p/verilog/verilog_global.c /^char* random_top_testbench_verilog_file_postfix = "_formal_random_top_tb.v"; $/;" v rc_node ./timing/net_delay_types.h /^ struct s_rc_node *rc_node;$/;" m struct:s_linked_rc_ptr typeref:struct:s_linked_rc_ptr::s_rc_node re_expand ./route/route_tree_timing.h /^ short re_expand;$/;" m struct:s_rt_node -read ../../libarchfpga/ezxml.c 59;" d file: read_act_file ./base/vpr_types.h /^ boolean read_act_file;$/;" m struct:s_fpga_spice_opts read_activity ./base/read_blif.c /^static void read_activity(char * activity_file) {$/;" f file: read_and_process_blif ./base/read_blif.c /^void read_and_process_blif(char *blif_file,$/;" f @@ -4908,14 +3583,10 @@ read_blif ./base/read_blif.c /^static void read_blif(char *blif_file, boolean sw read_netlist ./base/read_netlist.c /^void read_netlist(INP const char *net_file, INP const t_arch *arch,$/;" f read_options ./fpga_x2p/shell/read_opt.c /^boolean read_options(INP int argc,$/;" f read_place ./base/read_place.c /^void read_place(INP const char *place_file, INP const char *arch_file,$/;" f -read_repeat_counts ../../pcre/SRC/pcre.c /^read_repeat_counts(const uschar *p, int *minp, int *maxp,$/;" f file: read_sdc ./timing/read_sdc.c /^void read_sdc(t_timing_inf timing_inf) {$/;" f read_settings ./base/ReadOptions.h /^ int read_settings;$/;" m struct:s_options read_settings_file ./base/read_settings.c /^int read_settings_file(char * file_name, char *** outv)$/;" f read_user_pad_loc ./base/read_place.c /^void read_user_pad_loc(char *pad_loc_file) {$/;" f -read_xml_spice ../../libarchfpga/include/physical_types.h /^ boolean read_xml_spice;$/;" m struct:s_arch -real_pcre ../../pcre/SRC/internal.h /^typedef struct real_pcre {$/;" s -real_pcre ../../pcre/SRC/internal.h /^} real_pcre;$/;" t typeref:struct:real_pcre realloc_and_load_pb_graph_pin_ptrs_at_var ./pack/pb_type_graph.c /^static boolean realloc_and_load_pb_graph_pin_ptrs_at_var(INP int line_num,$/;" f file: reassign_rr_node_net_num_from_scratch ./route/pb_pin_eq_auto_detect.c /^void reassign_rr_node_net_num_from_scratch() {$/;" f rec_add_pb_type_keywords_to_list ./fpga_x2p/base/fpga_x2p_setup.c /^void rec_add_pb_type_keywords_to_list(t_pb_type* cur_pb_type,$/;" f file: @@ -4972,24 +3643,16 @@ recompute_timing_after ./base/ReadOptions.h /^ int recompute_timing_after;$/;" m recompute_timing_after ./base/vpr_types.h /^ int recompute_timing_after;$/;" m struct:s_packer_opts recover_rr_nodes_ipin_driver_switch ./route/rr_graph_opincb.c /^void recover_rr_nodes_ipin_driver_switch() {$/;" f file: rect_off_screen ./base/graphics.c /^rect_off_screen (float x1, float y1, float x2, float y2) $/;" f file: -recursion_info ../../pcre/SRC/internal.h /^typedef struct recursion_info {$/;" s -recursion_info ../../pcre/SRC/internal.h /^} recursion_info;$/;" t typeref:struct:recursion_info -recursive ../../pcre/SRC/internal.h /^ recursion_info *recursive; \/* Linked list of recursion data *\/$/;" m struct:match_data redraw_screen ./base/draw.c /^static void redraw_screen() {$/;" f file: reference_verilog_benchmark_file ./base/vpr_types.h /^ char* reference_verilog_benchmark_file;$/;" m struct:s_syn_verilog_opts regex_match ./timing/read_sdc.c /^static boolean regex_match (char * string, char * regular_expression) {$/;" f file: relapos_rec_s ./place/place_stats.c /^typedef struct relapos_rec_s {$/;" s file: relapos_rec_t ./place/place_stats.c /^} relapos_rec_t;$/;" t typeref:struct:relapos_rec_s file: -relative_length ../../libarchfpga/include/physical_types.h /^ float relative_length;$/;" m union:s_port_power::__anon22 reload_ext_net_rr_terminal_cluster ./pack/cluster_legality.c /^void reload_ext_net_rr_terminal_cluster(void) {$/;" f reload_intra_cluster_nets ./base/vpr_api.c /^static void reload_intra_cluster_nets(t_pb *pb) {$/;" f file: relocate ./timing/slre.c /^static void relocate(struct slre *r, int begin, int shift) {$/;" f file: -remove_llist_node ../../libarchfpga/linkedlist.c /^void remove_llist_node(t_llist* cur) { $/;" f rename_illegal_port ./base/vpr_types.h /^ boolean rename_illegal_port; \/* Rename illegal port names that is not compatible with verilog\/SPICE syntax *\/$/;" m struct:s_fpga_spice_opts renaming_report_postfix ./fpga_x2p/base/fpga_x2p_globals.c /^char* renaming_report_postfix = "_io_renaming.rpt";$/;" v -rep_max ../../pcre/SRC/pcre.c /^static const char rep_max[] = { 0, 0, 0, 0, 1, 1 };$/;" v file: -rep_min ../../pcre/SRC/pcre.c /^static const char rep_min[] = { 0, 0, 1, 1, 0, 0 };$/;" v file: -repeat ../../libarchfpga/include/physical_types.h /^ int repeat;$/;" m struct:s_grid_loc_def report_cb_timing ./fpga_x2p/verilog/verilog_report_timing.c /^ boolean report_cb_timing;$/;" m struct:s_trpt_opts file: report_pb_timing ./fpga_x2p/verilog/verilog_report_timing.c /^ boolean report_pb_timing;$/;" m struct:s_trpt_opts file: report_routing_timing ./fpga_x2p/verilog/verilog_report_timing.c /^ boolean report_routing_timing;$/;" m struct:s_trpt_opts file: @@ -4997,14 +3660,9 @@ report_sb_timing ./fpga_x2p/verilog/verilog_report_timing.c /^ boolean report_s report_structure ./base/graphics.c /^void report_structure(t_report *report) {$/;" f report_structure ./base/graphics.c /^void report_structure(t_report*) { }$/;" f report_timing_path ./base/vpr_types.h /^ char* report_timing_path;$/;" m struct:s_syn_verilog_opts -req_byte ../../pcre/SRC/internal.h /^ unsigned short int req_byte;$/;" m struct:real_pcre -req_varyopt ../../pcre/SRC/internal.h /^ int req_varyopt; \/* "After variable item" flag for reqbyte *\/$/;" m struct:compile_data requeue_primitive ./pack/cluster_placement.c /^static void requeue_primitive($/;" f file: -res_val ../../libarchfpga/fpga_spice_include/spice_types.h /^ float res_val;$/;" m struct:s_spice_model_wire_param reserve_locally_used_opins ./route/route_common.c /^void reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins,$/;" f -reserved_bl ../../libarchfpga/fpga_spice_include/spice_types.h /^ int reserved_bl; \/* Number of reserved BLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info reserved_syntax_char_head ./fpga_x2p/base/fpga_x2p_globals.c /^t_llist* reserved_syntax_char_head = NULL;$/;" v -reserved_wl ../../libarchfpga/fpga_spice_include/spice_types.h /^ int reserved_wl; \/* Number of reserved WLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info reset_cluster_placement_stats ./pack/cluster_placement.c /^void reset_cluster_placement_stats($/;" f reset_common_state ./base/graphics.c /^static void reset_common_state () {$/;" f file: reset_flags ./route/check_route.c /^static void reset_flags(int inet, boolean * connected_to_route) {$/;" f file: @@ -5026,15 +3684,12 @@ restore_routing_cluster ./pack/cluster_legality.c /^void restore_routing_cluster resync_pb_graph_nodes_in_pb ./base/vpr_api.c /^static void resync_pb_graph_nodes_in_pb(t_pb_graph_node *pb_graph_node,$/;" f file: resync_post_route_netlist ./base/vpr_api.c /^void resync_post_route_netlist() {$/;" f ret_track_swseg_pattern ./route/rr_graph_swseg.c /^enum ret_track_swseg_pattern {$/;" g file: -reverse_llist ../../libarchfpga/linkedlist.c /^t_llist* reverse_llist(t_llist* head) {$/;" f -reverse_scaled ../../libarchfpga/include/physical_types.h /^ boolean reverse_scaled; \/* Scale by (1-prob) *\/$/;" m struct:s_port_power revert_place_logical_block ./pack/cluster.c /^static void revert_place_logical_block(INP int iblock, INP int max_models) {$/;" f file: rising_edge ./timing/read_sdc.c /^ float rising_edge;$/;" m struct:s_sdc_clock file: -roff ../../libarchfpga/fpga_spice_include/spice_types.h /^ float roff;$/;" m struct:s_spice_model_rram -ron ../../libarchfpga/fpga_spice_include/spice_types.h /^ float ron;$/;" m struct:s_spice_model_rram root ./base/vpr_types.h /^ int root; \/* root index of molecule, logical_block_ptrs[root] is ptr to root logical block *\/$/;" m struct:s_pack_molecule -root_block ../../libarchfpga/include/cad_types.h /^ t_pack_pattern_block *root_block; \/* root block used by this pattern *\/$/;" m struct:s_pack_patterns root_passes_early_filter ./pack/cluster_placement.c /^static boolean root_passes_early_filter(INP t_pb_graph_node *root, INP t_pack_molecule *molecule, INP int clb_index) {$/;" f file: +rotatable ./base/vpr_types.h /^ t_cb* rotatable; $/;" m struct:s_cb +rotatable ./base/vpr_types.h /^ t_sb* rotatable; $/;" m struct:s_sb rotate_shift_swseg_pattern ./route/rr_graph_swseg.c /^boolean* rotate_shift_swseg_pattern(int pattern_length,$/;" f file: route_bb ./fpga_x2p/base/fpga_x2p_types.h /^ t_bb *route_bb; \/* [0..num_nets-1]. Limits area in which each *\/$/;" m struct:fpga_spice_rr_graph route_bb ./route/route_common.c /^struct s_bb *route_bb = NULL; \/* [0..num_nets-1]. Limits area in which each *\/$/;" v typeref:struct:s_bb @@ -5063,7 +3718,6 @@ rr_node ./base/globals_declare.h /^t_rr_node *rr_node; \/* [0..num_rr_nodes-1] rr_node ./fpga_x2p/base/fpga_x2p_types.h /^ t_rr_node* rr_node;$/;" m struct:fpga_spice_rr_graph rr_node_color ./base/draw.c /^static enum color_types *rr_node_color = NULL;$/;" v typeref:enum:color_types file: rr_node_drive_switch_box ./fpga_x2p/base/fpga_x2p_utils.c /^int rr_node_drive_switch_box(t_rr_node* src_rr_node,$/;" f -rr_node_index_physical_pb ../../libarchfpga/include/physical_types.h /^ int rr_node_index_physical_pb; \/* rr_node in the physical pb rr_graph*\/$/;" m struct:s_pb_graph_pin rr_node_indices ./base/globals.c /^t_ivec ***rr_node_indices = NULL;$/;" v rr_node_indices ./base/globals_declare.h /^t_ivec ***rr_node_indices;$/;" v rr_node_indices ./fpga_x2p/base/fpga_x2p_types.h /^ t_ivec*** rr_node_indices;$/;" m struct:fpga_spice_rr_graph @@ -5076,10 +3730,7 @@ rr_node_to_pb_mapping ./base/vpr_types.h /^ struct s_pb **rr_node_to_pb_mapping; rr_node_to_pb_mapping ./fpga_x2p/base/fpga_x2p_types.h /^ t_phy_pb **rr_node_to_pb_mapping; \/* [0..num_local_rr_nodes-1] pointer look-up of which pb this rr_node belongs based on index, NULL if pb does not exist *\/$/;" m struct:fpga_spice_phy_pb rr_node_to_rt_node ./route/route_tree_timing.c /^static t_rt_node **rr_node_to_rt_node = NULL; \/* [0..num_rr_nodes-1] *\/$/;" v file: rram_design_tech ./fpga_x2p/spice/spice_globals.c /^int rram_design_tech = 0;$/;" v -rram_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_rram* rram_info;$/;" m struct:s_spice_model_design_tech_info -rram_pass_tran_value ../../libarchfpga/include/arch_types_mrfpga.h /^ float rram_pass_tran_value;$/;" m struct:s_arch_mrfpga rram_pass_tran_value ./mrfpga/mrfpga_globals.c /^float rram_pass_tran_value = 0;$/;" v -rram_variation ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params rram_variation;$/;" m struct:s_spice_mc_params rram_veriloga_file_name ./fpga_x2p/spice/spice_globals.c /^char* rram_veriloga_file_name = "rram_behavior.va";$/;" v rt_edge_free_list ./route/route_tree_timing.c /^static t_linked_rt_edge *rt_edge_free_list = NULL;$/;" v file: rt_node_free_list ./route/route_tree_timing.c /^static t_rt_node *rt_node_free_list = NULL;$/;" v file: @@ -5088,67 +3739,37 @@ run_hspice_shell_script_name ./fpga_x2p/spice/spice_run_scripts.c /^static char* run_parasitic_net_estimation ./fpga_x2p/base/fpga_x2p_globals.c /^boolean run_parasitic_net_estimation = TRUE;$/;" v run_shell ./fpga_x2p/shell/mini_shell.c /^void run_shell(int argc, char ** argv) {$/;" f run_testbench_load_extraction ./fpga_x2p/base/fpga_x2p_globals.c /^boolean run_testbench_load_extraction = TRUE;$/;" v -s ../../libarchfpga/include/ezxml.h /^ char *s; \/* start of work area *\/$/;" m struct:ezxml_root s_TokenPair ./base/vpr_types.h /^struct s_TokenPair {$/;" s s_annealing_sched ./base/vpr_types.h /^struct s_annealing_sched {$/;" s -s_arch ../../libarchfpga/include/physical_types.h /^struct s_arch {$/;" s -s_arch_mrfpga ../../libarchfpga/include/arch_types_mrfpga.h /^struct s_arch_mrfpga {$/;" s s_bb ./base/vpr_types.h /^struct s_bb {$/;" s s_bitstream_gen_opts ./base/vpr_types.h /^struct s_bitstream_gen_opts {$/;" s s_block ./base/vpr_types.h /^struct s_block {$/;" s -s_buffer_inf ../../libarchfpga/include/arch_types_mrfpga.h /^struct s_buffer_inf { $/;" s s_buffer_plan ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" s file: s_buffer_plan_list ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_list { t_buffer_plan_node* front; } t_buffer_plan_list;$/;" s file: s_buffer_plan_node ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node;$/;" s file: s_cb ./base/vpr_types.h /^struct s_cb {$/;" s -s_chan ../../libarchfpga/include/physical_types.h /^typedef struct s_chan {$/;" s -s_chan_width_dist ../../libarchfpga/include/physical_types.h /^typedef struct s_chan_width_dist {$/;" s -s_chunk ../../libarchfpga/include/util.h /^typedef struct s_chunk {$/;" s -s_class ../../libarchfpga/include/physical_types.h /^struct s_class {$/;" s -s_clb_grid ../../libarchfpga/include/physical_types.h /^struct s_clb_grid {$/;" s s_clb_to_clb_directs ./base/vpr_types.h /^typedef struct s_clb_to_clb_directs {$/;" s s_clock ./base/vpr_types.h /^typedef struct s_clock {$/;" s -s_clock_arch ../../libarchfpga/include/physical_types.h /^struct s_clock_arch {$/;" s -s_clock_network ../../libarchfpga/include/physical_types.h /^struct s_clock_network {$/;" s -s_cluster_placement_primitive ../../libarchfpga/include/cad_types.h /^typedef struct s_cluster_placement_primitive {$/;" s s_cluster_placement_stats ./base/vpr_types.h /^typedef struct s_cluster_placement_stats {$/;" s s_cmd_category ./fpga_x2p/shell/shell_types.h /^struct s_cmd_category {$/;" s s_cmd_info ./fpga_x2p/shell/read_opt_types.h /^struct s_cmd_info {$/;" s -s_conf_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_conf_bit {$/;" s -s_conf_bit_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_conf_bit_info {$/;" s s_det_routing_arch ./base/vpr_types.h /^struct s_det_routing_arch {$/;" s -s_direct_inf ../../libarchfpga/include/physical_types.h /^typedef struct s_direct_inf {$/;" s s_file_name_opts ./base/vpr_types.h /^struct s_file_name_opts {$/;" s s_fmap_cell ./base/place_and_route.h /^typedef struct s_fmap_cell {$/;" s s_fpga_spice_opts ./base/vpr_types.h /^struct s_fpga_spice_opts {$/;" s -s_grid_loc_def ../../libarchfpga/include/physical_types.h /^typedef struct s_grid_loc_def {$/;" s s_grid_tile ./base/vpr_types.h /^typedef struct s_grid_tile {$/;" s s_hash ./util/hash.h /^struct s_hash {$/;" s s_hash_iterator ./util/hash.h /^struct s_hash_iterator {$/;" s s_heap ./route/route_common.h /^struct s_heap {$/;" s -s_interconnect ../../libarchfpga/include/physical_types.h /^struct s_interconnect {$/;" s -s_interconnect_pins ../../libarchfpga/include/physical_types.h /^struct s_interconnect_pins {$/;" s -s_interconnect_power ../../libarchfpga/include/physical_types.h /^struct s_interconnect_power {$/;" s s_io ./base/vpr_types.h /^typedef struct s_io {$/;" s -s_ivec ../../libarchfpga/include/util.h /^typedef struct s_ivec {$/;" s s_legal_pos ./place/place.c /^typedef struct s_legal_pos {$/;" s file: s_linked_edge ./route/rr_graph_util.h /^struct s_linked_edge {$/;" s s_linked_f_pointer ./base/vpr_types.h /^struct s_linked_f_pointer {$/;" s -s_linked_int ../../libarchfpga/include/util.h /^typedef struct s_linked_int {$/;" s s_linked_rc_edge ./timing/net_delay_types.h /^struct s_linked_rc_edge {$/;" s s_linked_rc_ptr ./timing/net_delay_types.h /^struct s_linked_rc_ptr {$/;" s s_linked_rt_edge ./route/route_tree_timing.h /^struct s_linked_rt_edge {$/;" s -s_linked_vptr ../../libarchfpga/include/util.h /^typedef struct s_linked_vptr {$/;" s -s_llist ../../libarchfpga/fpga_spice_include/linkedlist.h /^struct s_llist$/;" s s_log ./power/power.h /^struct s_log {$/;" s s_logical_block ./base/vpr_types.h /^typedef struct s_logical_block {$/;" s -s_mem_bank_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_mem_bank_info {$/;" s -s_memristor_inf ../../libarchfpga/include/arch_types_mrfpga.h /^struct s_memristor_inf { $/;" s -s_mode ../../libarchfpga/include/physical_types.h /^struct s_mode {$/;" s -s_mode_power ../../libarchfpga/include/physical_types.h /^struct s_mode_power {$/;" s -s_model ../../libarchfpga/include/logic_types.h /^typedef struct s_model {$/;" s -s_model_chain_pattern ../../libarchfpga/include/cad_types.h /^typedef struct s_model_chain_pattern {$/;" s -s_model_ports ../../libarchfpga/include/logic_types.h /^typedef struct s_model_ports {$/;" s s_model_stats ./base/read_blif.c /^struct s_model_stats {$/;" s file: s_molecule_link ./pack/cluster.c /^struct s_molecule_link {$/;" s file: s_mux ./route/rr_graph.c /^typedef struct s_mux {$/;" s file: @@ -5162,29 +3783,15 @@ s_opt_info ./fpga_x2p/shell/read_opt_types.h /^struct s_opt_info {$/;" s s_options ./base/ReadOptions.h /^struct s_options {$/;" s s_override_constraint ./base/vpr_types.h /^typedef struct s_override_constraint {$/;" s s_pack_molecule ./base/vpr_types.h /^typedef struct s_pack_molecule {$/;" s -s_pack_pattern_block ../../libarchfpga/include/cad_types.h /^typedef struct s_pack_pattern_block {$/;" s -s_pack_pattern_connections ../../libarchfpga/include/cad_types.h /^typedef struct s_pack_pattern_connections {$/;" s -s_pack_patterns ../../libarchfpga/include/cad_types.h /^typedef struct s_pack_patterns {$/;" s s_packer_opts ./base/vpr_types.h /^struct s_packer_opts {$/;" s s_pb ./base/vpr_types.h /^typedef struct s_pb {$/;" s -s_pb_graph_edge ../../libarchfpga/include/physical_types.h /^struct s_pb_graph_edge {$/;" s -s_pb_graph_node ../../libarchfpga/include/physical_types.h /^struct s_pb_graph_node {$/;" s -s_pb_graph_node_power ../../libarchfpga/include/physical_types.h /^struct s_pb_graph_node_power {$/;" s -s_pb_graph_pin ../../libarchfpga/include/physical_types.h /^struct s_pb_graph_pin {$/;" s -s_pb_graph_pin_power ../../libarchfpga/include/physical_types.h /^struct s_pb_graph_pin_power {$/;" s s_pb_stats ./base/vpr_types.h /^typedef struct s_pb_stats {$/;" s -s_pb_type ../../libarchfpga/include/physical_types.h /^struct s_pb_type {$/;" s -s_pb_type_power ../../libarchfpga/include/physical_types.h /^struct s_pb_type_power {$/;" s -s_pin_to_pin_annotation ../../libarchfpga/include/physical_types.h /^struct s_pin_to_pin_annotation {$/;" s s_pl_blocks_to_be_moved ./place/place.c /^typedef struct s_pl_blocks_to_be_moved {$/;" s file: s_pl_macro ./place/place_macro.h /^typedef struct s_pl_macro{$/;" s s_pl_macro_member ./place/place_macro.h /^typedef struct s_pl_macro_member{$/;" s s_pl_moved_block ./place/place.c /^typedef struct s_pl_moved_block {$/;" s file: s_place_region ./base/vpr_types.h /^struct s_place_region {$/;" s s_placer_opts ./base/vpr_types.h /^struct s_placer_opts {$/;" s -s_port ../../libarchfpga/include/physical_types.h /^struct s_port {$/;" s -s_port_power ../../libarchfpga/include/physical_types.h /^struct s_port_power {$/;" s -s_power_arch ../../libarchfpga/include/physical_types.h /^struct s_power_arch {$/;" s s_power_breakdown ./power/power_components.h /^struct s_power_breakdown {$/;" s s_power_buffer_sc_levr_inf ./power/power.h /^struct s_power_buffer_sc_levr_inf {$/;" s s_power_buffer_size_inf ./power/power.h /^struct s_power_buffer_size_inf {$/;" s @@ -5199,62 +3806,26 @@ s_power_nmos_mux_inf ./power/power.h /^struct s_power_nmos_mux_inf {$/;" s s_power_opts ./base/vpr_types.h /^struct s_power_opts {$/;" s s_power_output ./power/power.h /^struct s_power_output {$/;" s s_power_tech ./power/power.h /^struct s_power_tech {$/;" s -s_power_usage ../../libarchfpga/include/physical_types.h /^struct s_power_usage {$/;" s s_prepacked_tnode_data ./base/vpr_types.h /^typedef struct s_prepacked_tnode_data {$/;" s s_rc_node ./timing/net_delay_types.h /^struct s_rc_node {$/;" s -s_reserved_syntax_char ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_reserved_syntax_char {$/;" s s_router_opts ./base/vpr_types.h /^struct s_router_opts {$/;" s s_rr_indexed_data ./base/vpr_types.h /^typedef struct s_rr_indexed_data {$/;" s s_rr_node ./base/vpr_types.h /^struct s_rr_node {$/;" s s_rr_node_power ./power/power.h /^struct s_rr_node_power {$/;" s s_rt_node ./route/route_tree_timing.h /^struct s_rt_node {$/;" s s_sb ./base/vpr_types.h /^struct s_sb {$/;" s -s_scff_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_scff_info {$/;" s s_sdc_clock ./timing/read_sdc.c /^typedef struct s_sdc_clock {$/;" s file: s_sdc_exclusive_group ./timing/read_sdc.c /^typedef struct s_sdc_exclusive_group {$/;" s file: s_sdc_opts ./fpga_x2p/verilog/verilog_sdc.c /^struct s_sdc_opts {$/;" s file: s_seg_details ./base/vpr_types.h /^typedef struct s_seg_details {$/;" s -s_segment_inf ../../libarchfpga/include/physical_types.h /^typedef struct s_segment_inf {$/;" s s_shell_cmd ./fpga_x2p/shell/shell_types.h /^struct s_shell_cmd {$/;" s s_shell_env ./fpga_x2p/shell/shell_types.h /^struct s_shell_env {$/;" s s_slack ./base/vpr_types.h /^typedef struct s_slack {$/;" s s_solution_inf ./power/power.h /^struct s_solution_inf {$/;" s -s_spice ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice {$/;" s -s_spice_mc_params ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_mc_params {$/;" s -s_spice_mc_variation_params ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_mc_variation_params {$/;" s -s_spice_meas_params ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_meas_params {$/;" s -s_spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model {$/;" s -s_spice_model_buffer ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_buffer {$/;" s -s_spice_model_delay_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_delay_info {$/;" s -s_spice_model_design_tech_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_design_tech_info {$/;" s -s_spice_model_gate ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_gate {$/;" s -s_spice_model_lut ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_lut {$/;" s -s_spice_model_mux ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_mux {$/;" s -s_spice_model_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_netlist {$/;" s -s_spice_model_pass_gate_logic ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_pass_gate_logic {$/;" s -s_spice_model_port ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_port {$/;" s -s_spice_model_rram ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_rram {$/;" s -s_spice_model_tedge ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_tedge {$/;" s -s_spice_model_wire_param ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_wire_param {$/;" s -s_spice_mux_arch ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_mux_arch {$/;" s -s_spice_mux_model ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_mux_model {$/;" s -s_spice_net_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_net_info {$/;" s s_spice_opts ./base/vpr_types.h /^struct s_spice_opts {$/;" s -s_spice_params ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_params {$/;" s -s_spice_stimulate_params ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_stimulate_params {$/;" s -s_spice_tech_lib ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_tech_lib {$/;" s -s_spice_transistor_type ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_transistor_type {$/;" s -s_spicetb_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spicetb_info {$/;" s -s_sram_inf ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_sram_inf {$/;" s -s_sram_inf_orgz ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_sram_inf_orgz {$/;" s -s_sram_orgz_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_sram_orgz_info {$/;" s -s_standalone_sram_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_standalone_sram_info {$/;" s -s_switch_inf ../../libarchfpga/include/physical_types.h /^typedef struct s_switch_inf {$/;" s -s_swseg_pattern_inf ../../libarchfpga/include/physical_types.h /^struct s_swseg_pattern_inf {$/;" s s_syn_verilog_opts ./base/vpr_types.h /^struct s_syn_verilog_opts {$/;" s s_tedge ./base/vpr_types.h /^typedef struct s_tedge {$/;" s s_timing_constraints ./base/vpr_types.h /^typedef struct s_timing_constraints { \/* Container structure for all SDC timing constraints. $/;" s -s_timing_inf ../../libarchfpga/include/physical_types.h /^typedef struct s_timing_inf {$/;" s s_timing_stats ./base/vpr_types.h /^typedef struct s_timing_stats {$/;" s s_tnode ./base/vpr_types.h /^typedef struct s_tnode {$/;" s s_token ./util/token.h /^struct s_token {$/;" s @@ -5262,7 +3833,6 @@ s_trace ./base/vpr_types.h /^typedef struct s_trace {$/;" s s_transistor_inf ./power/power.h /^struct s_transistor_inf {$/;" s s_transistor_size_inf ./power/power.h /^struct s_transistor_size_inf {$/;" s s_trpt_opts ./fpga_x2p/verilog/verilog_report_timing.c /^struct s_trpt_opts {$/;" s file: -s_type_descriptor ../../libarchfpga/include/physical_types.h /^struct s_type_descriptor \/* TODO rename this. maybe physical type descriptor or complex logic block or physical logic block*\/$/;" s s_vpr_setup ./base/vpr_types.h /^typedef struct s_vpr_setup {$/;" s s_wireL_cnt ./fpga_x2p/verilog/verilog_report_timing.c /^struct s_wireL_cnt {$/;" s file: sat_blks_pins_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^int sat_blks_pins_prefer_side(int n_nets, t_net* nets, $/;" f @@ -5272,24 +3842,17 @@ save_best_buffer_list ./mrfpga/buffer_insertion.c /^static void save_best_buffer save_best_timing ./mrfpga/buffer_insertion.c /^static void save_best_timing( float* sink_delay, t_linked_int* index, float* net_delay )$/;" f file: save_cluster_solution ./pack/cluster_legality.c /^void save_cluster_solution(void) {$/;" f save_routing ./route/route_common.c /^void save_routing(struct s_trace **best_routing,$/;" f -save_start ../../pcre/SRC/internal.h /^ const uschar *save_start; \/* Old value of md->start_match *\/$/;" m struct:recursion_info saved_base_cost ./base/vpr_types.h /^ float saved_base_cost;$/;" m struct:s_rr_indexed_data -saved_eptr ../../pcre/SRC/pcre.c /^ const uschar *saved_eptr;$/;" m struct:eptrblock file: -saved_max ../../pcre/SRC/internal.h /^ int saved_max; \/* Number of saved offsets *\/$/;" m struct:recursion_info saved_net_rr_terminals ./pack/cluster_legality.c /^static int **saved_net_rr_terminals;$/;" v file: saved_num_nets_in_cluster ./pack/cluster_legality.c /^static int saved_num_nets_in_cluster;$/;" v file: saved_xleft ./base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: saved_xright ./base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: saved_ybot ./base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: saved_ytop ./base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: -sb ../../libarchfpga/include/physical_types.h /^ boolean *sb;$/;" m struct:s_segment_inf sb ./base/vpr_types.h /^ boolean *sb;$/;" m struct:s_seg_details sb_drive_rr_nodes ./base/vpr_types.h /^ t_rr_node** sb_drive_rr_nodes;$/;" m struct:s_rr_node sb_drive_switches ./base/vpr_types.h /^ int* sb_drive_switches;$/;" m struct:s_rr_node -sb_index_high ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** sb_index_high;$/;" m struct:s_spice_model -sb_index_low ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** sb_index_low;$/;" m struct:s_spice_model sb_info ./base/globals.c /^t_sb** sb_info = NULL;$/;" v -sb_len ../../libarchfpga/include/physical_types.h /^ int sb_len;$/;" m struct:s_segment_inf sb_num_drive_rr_nodes ./base/vpr_types.h /^ int sb_num_drive_rr_nodes;$/;" m struct:s_rr_node sb_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* sb_spice_file_name_prefix = "sb_";$/;" v sb_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* sb_verilog_file_name_prefix = "sb_";$/;" v @@ -5297,20 +3860,16 @@ sc_levr ./power/power.h /^ float sc_levr;$/;" m struct:s_power_buffer_sc_levr_in sc_levr_inf ./power/power.h /^ t_power_buffer_sc_levr_inf * sc_levr_inf;$/;" m struct:s_power_buffer_strength_inf sc_no_levr ./power/power.h /^ float sc_no_levr;$/;" m struct:s_power_buffer_strength_inf scale_factor ./power/PowerSpicedComponent.c /^float PowerSpicedComponent::scale_factor(int num_inputs,$/;" f class:PowerSpicedComponent -scaled_by_pin ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin * scaled_by_pin;$/;" m struct:s_pb_graph_pin_power -scaled_by_port ../../libarchfpga/include/physical_types.h /^ t_port * scaled_by_port;$/;" m struct:s_port_power -scaled_by_port_pin_idx ../../libarchfpga/include/physical_types.h /^ int scaled_by_port_pin_idx;$/;" m struct:s_port_power scan_chain_heads ./fpga_x2p/spice/spice_globals.c /^t_llist* scan_chain_heads = NULL;$/;" v -scff_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_scff_info* scff_info; \/* Only be allocated when orgz type is scan-chain *\/$/;" m struct:s_sram_orgz_info sched_type ./base/vpr_types.h /^enum sched_type {$/;" g -scratch_pad ../../libarchfpga/include/physical_types.h /^ int scratch_pad; \/* temporary data structure useful to store traversal info *\/$/;" m struct:s_pb_graph_pin screen_num ./base/graphics.c /^static int screen_num;$/;" v file: sdc ./timing/read_sdc.c /^static FILE *sdc;$/;" v file: sdc_analysis_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_analysis_file_name = "fpga_top_analysis.sdc";$/;" v sdc_break_loop_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_break_loop_file_name = "break_loop.sdc";$/;" v -sdc_clock_period_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_clock_period_file_name = "clock.sdc";$/;" v +sdc_clock_period_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_clock_period_file_name = "clb_clock.sdc";$/;" v sdc_clocks ./timing/read_sdc.c /^t_sdc_clock * sdc_clocks = NULL; \/* List of clock periods and offsets from create_clock commands *\/$/;" v sdc_constrain_cb_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_constrain_cb_file_name = "cb.sdc";$/;" v +sdc_constrain_pb_type_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_constrain_pb_type_file_name = "clb_constraints.sdc";$/;" v sdc_constrain_routing_chan_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_constrain_routing_chan_file_name = "routing_channels.sdc";$/;" v sdc_constrain_sb_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_constrain_sb_file_name = "sb.sdc";$/;" v sdc_dir ./fpga_x2p/verilog/verilog_report_timing.c /^ char* sdc_dir;$/;" m struct:s_trpt_opts file: @@ -5323,19 +3882,15 @@ sdc_rec_dump_child_pb_graph_node ./fpga_x2p/verilog/verilog_sdc_pb_types.c /^voi sdf_DFF_delay_printing ./base/verilog_writer.c /^void sdf_DFF_delay_printing(FILE *SDF , t_pb *pb)$/;" f sdf_LUT_delay_printing ./base/verilog_writer.c /^void sdf_LUT_delay_printing(FILE *SDF , t_pb *pb)$/;" f search_and_add_num_mapped_opin_llist ./route/pb_pin_eq_auto_detect.c /^t_llist* search_and_add_num_mapped_opin_llist(t_llist* head, $/;" f -search_in_int_list ../../libarchfpga/util.c /^t_linked_int* search_in_int_list(t_linked_int* int_list_head, $/;" f -search_llist_tail ../../libarchfpga/linkedlist.c /^t_llist* search_llist_tail(t_llist* head) {$/;" f search_mapped_block ./fpga_x2p/base/fpga_x2p_utils.c /^t_block* search_mapped_block(int x, int y, int z) {$/;" f search_mux_linked_list ./fpga_x2p/base/fpga_x2p_mux_utils.c /^t_llist* search_mux_linked_list(t_llist* mux_head,$/;" f search_swseg_pattern_seg_len ./route/rr_graph_swseg.c /^t_swseg_pattern_inf* search_swseg_pattern_seg_len(INP int num_swseg_pattern,$/;" f file: search_tapbuf_llist_same_settings ./fpga_x2p/spice/spice_subckt.c /^int search_tapbuf_llist_same_settings(t_llist* head,$/;" f file: +searching_used_latch ./fpga_x2p/verilog/verilog_formality_autodeck.c /^static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chomped_circuit_name, char* inst_name){$/;" f file: seed ./base/vpr_types.h /^ int seed;$/;" m struct:s_placer_opts -seg_direction_type ../../libarchfpga/include/physical_types.h /^ enum e_directionality seg_direction_type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_directionality seg_index ./base/vpr_types.h /^ int seg_index;$/;" m struct:s_rr_indexed_data seg_index_of_cblock ./route/rr_graph_util.c /^int seg_index_of_cblock(t_rr_type from_rr_type, int to_node) {$/;" f seg_index_of_sblock ./route/rr_graph_util.c /^int seg_index_of_sblock(int from_node, int to_node) {$/;" f -seg_length ../../libarchfpga/include/physical_types.h /^ int seg_length;$/;" m struct:s_swseg_pattern_inf -seg_switch ../../libarchfpga/include/physical_types.h /^ short seg_switch;$/;" m struct:s_segment_inf seg_switch ./base/vpr_types.h /^ short seg_switch;$/;" m struct:s_seg_details segments ./fpga_x2p/spice/spice_mux_testbench.c /^static t_segment_inf* segments;$/;" v file: segments ./fpga_x2p/spice/spice_routing_testbench.c /^static t_segment_inf* segments;$/;" v file: @@ -5420,43 +3975,26 @@ show_defects ./base/draw.c /^static boolean show_defects = FALSE; \/* Show defec show_graphics ./base/draw.c /^static boolean show_graphics; \/* Graphics enabled or not? *\/$/;" v file: show_nets ./base/draw.c /^static boolean show_nets = FALSE; \/* Show nets of placement or routing? *\/$/;" v file: show_opt_list ./fpga_x2p/shell/read_opt.c /^int show_opt_list(t_opt_info* cur) {$/;" f -sibling ../../libarchfpga/include/ezxml.h /^ ezxml_t sibling; \/* next tag with different name in same section and depth *\/$/;" m struct:ezxml signal_density_weight ./base/vpr_types.h /^ float signal_density_weight;$/;" m struct:s_fpga_spice_opts -sim_clock_freq_slack ../../libarchfpga/fpga_spice_include/spice_types.h /^ float sim_clock_freq_slack;$/;" m struct:s_spice_stimulate_params -sim_num_clock_cycle ../../libarchfpga/fpga_spice_include/spice_types.h /^ int sim_num_clock_cycle; \/* Number of clock cycle in simulation *\/$/;" m struct:s_spice_meas_params sim_results_dir_name ./fpga_x2p/spice/spice_run_scripts.c /^static char* sim_results_dir_name = "results\/";$/;" v file: -sim_temp ../../libarchfpga/fpga_spice_include/spice_types.h /^ int sim_temp; \/* Simulation Temperature*\/$/;" m struct:s_spice_params sim_window_size ./base/vpr_types.h /^ float sim_window_size;$/;" m struct:s_fpga_spice_opts simulator_path ./base/vpr_types.h /^ char* simulator_path;$/;" m struct:s_spice_opts sink_delay ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: sink_head ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: sink_list ./base/vpr_types.h /^ char ** sink_list;$/;" m struct:s_override_constraint sink_order ./place/timing_place_lookup.c /^static int *sink_order;$/;" v file: -size ../../libarchfpga/fpga_spice_include/spice_types.h /^ float size;$/;" m struct:s_spice_model_buffer -size ../../libarchfpga/fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_model_port -size ../../libarchfpga/fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_mux_model -size ../../libarchfpga/include/logic_types.h /^ int size; \/* maximum number of pins *\/$/;" m struct:s_model_ports -size ../../pcre/SRC/internal.h /^ size_t size; \/* Total that was malloced *\/$/;" m struct:pcre_study_data -size ../../pcre/SRC/internal.h /^ size_t size; \/* Total that was malloced *\/$/;" m struct:real_pcre size ./power/power.h /^ float size;$/;" m struct:s_transistor_size_inf size ./route/rr_graph.c /^ int size;$/;" m struct:s_mux file: size_inf ./power/power.h /^ t_transistor_size_inf * size_inf; \/* Array of transistor sizes *\/$/;" m struct:s_transistor_inf skip_clustering ./base/ReadOptions.h /^ boolean skip_clustering;$/;" m struct:s_options skip_clustering ./base/vpr_types.h /^ boolean skip_clustering;$/;" m struct:s_packer_opts slack ./base/vpr_types.h /^ float ** slack;$/;" m struct:s_slack -slew_fall ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_fall;$/;" m struct:s_spice_net_info -slew_lower_thres_pct_fall ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_fall;$/;" m struct:s_spice_meas_params -slew_lower_thres_pct_rise ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_rise;$/;" m struct:s_spice_meas_params -slew_rise ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_rise;$/;" m struct:s_spice_net_info -slew_upper_thres_pct_fall ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_fall;$/;" m struct:s_spice_meas_params -slew_upper_thres_pct_rise ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_rise;$/;" m struct:s_spice_meas_params slre ./timing/slre.c /^struct slre {$/;" s file: slre_capture ./timing/slre.h /^enum slre_capture {SLRE_STRING, SLRE_INT, SLRE_FLOAT};$/;" g slre_match ./timing/slre.c /^const char *slre_match(enum slre_option options, const char *re,$/;" f slre_option ./timing/slre.h /^enum slre_option {SLRE_CASE_INSENSITIVE = 1};$/;" g snapshot_spice_model_counter ./fpga_x2p/base/fpga_x2p_utils.c /^int* snapshot_spice_model_counter(int num_spice_models,$/;" f snapshot_sram_orgz_info ./fpga_x2p/base/fpga_x2p_utils.c /^t_sram_orgz_info* snapshot_sram_orgz_info(t_sram_orgz_info* src_sram_orgz_info) {$/;" f -snprintf ../../libarchfpga/ezxml.c 57;" d file: sort_me ./power/PowerSpicedComponent.c /^void PowerCallibInputs::sort_me() {$/;" f class:PowerCallibInputs sort_me ./power/PowerSpicedComponent.c /^void PowerSpicedComponent::sort_me(void) {$/;" f class:PowerSpicedComponent sort_one_class_conflict_pins_by_low_slack ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int* sort_one_class_conflict_pins_by_low_slack(t_block* target_blk, int class_index,$/;" f @@ -5465,7 +4003,6 @@ sorted ./power/PowerSpicedComponent.h /^ bool sorted;$/;" m class:PowerSpicedCom sorter_PowerCallibInputs ./power/PowerSpicedComponent.c /^bool sorter_PowerCallibInputs(PowerCallibInputs * a, PowerCallibInputs * b) {$/;" f sorter_PowerCallibSize ./power/PowerSpicedComponent.c /^bool sorter_PowerCallibSize(PowerCallibSize * a, PowerCallibSize * b) {$/;" f source_list ./base/vpr_types.h /^ char ** source_list; \/* Array of net names of flip-flops or clocks *\/$/;" m struct:s_override_constraint -spice ../../libarchfpga/include/physical_types.h /^ t_spice* spice;$/;" m struct:s_arch spice_backannotate_vpr_post_route_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void spice_backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch,$/;" f spice_cb_mux_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_cb_mux_tb_dir_name = "cb_mux_tb\/";$/;" v file: spice_cb_mux_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_cb_mux_testbench_postfix = "_cbmux_testbench.sp";$/;" v @@ -5483,38 +4020,12 @@ spice_io_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_io_tb_dir spice_io_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_io_testbench_postfix = "_io_testbench.sp";$/;" v spice_lut_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_lut_tb_dir_name = "lut_tb\/";$/;" v file: spice_lut_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_lut_testbench_postfix = "_lut_testbench.sp";$/;" v -spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz -spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_buffer -spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_pass_gate_logic -spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_port -spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_mux_model -spice_model ../../libarchfpga/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_direct_inf -spice_model ../../libarchfpga/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_interconnect -spice_model ../../libarchfpga/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_pb_type -spice_model ../../libarchfpga/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_segment_inf -spice_model ../../libarchfpga/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_switch_inf spice_model ./base/vpr_types.h /^ t_spice_model* spice_model;$/;" m struct:s_clb_to_clb_directs -spice_model_delay_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum spice_model_delay_type {$/;" g -spice_model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* spice_model_name; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz -spice_model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_buffer -spice_model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_pass_gate_logic -spice_model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_port -spice_model_name ../../libarchfpga/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_direct_inf -spice_model_name ../../libarchfpga/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_interconnect -spice_model_name ../../libarchfpga/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_pb_type -spice_model_name ../../libarchfpga/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_segment_inf -spice_model_name ../../libarchfpga/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_switch_inf -spice_model_port ../../libarchfpga/include/physical_types.h /^ t_spice_model_port* spice_model_port;$/;" m struct:s_port -spice_model_sram_offset ../../libarchfpga/include/physical_types.h /^ int spice_model_sram_offset;$/;" m struct:s_interconnect -spice_model_sram_offset ../../libarchfpga/include/physical_types.h /^ int spice_model_sram_offset;$/;" m struct:s_pb_type -spice_models ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_models;$/;" m struct:s_spice -spice_mux_arch ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_mux_arch* spice_mux_arch;$/;" m struct:s_spice_mux_model spice_name_tag ./base/vpr_types.h /^ char* spice_name_tag;$/;" m struct:s_pb spice_name_tag ./fpga_x2p/base/fpga_x2p_types.h /^ char* spice_name_tag;$/;" m struct:fpga_spice_phy_pb spice_net_info ./base/vpr_types.h /^ t_spice_net_info* spice_net_info;$/;" m struct:s_net spice_net_info_add_density_weight ./fpga_x2p/base/fpga_x2p_setup.c /^void spice_net_info_add_density_weight(float signal_density_weight) {$/;" f file: spice_netlist_file_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_netlist_file_postfix = ".sp";$/;" v -spice_params ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_params spice_params;$/;" m struct:s_spice spice_pb_mux_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_pb_mux_tb_dir_name = "pb_mux_tb\/";$/;" v file: spice_pb_mux_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_pb_mux_testbench_postfix = "_pbmux_testbench.sp";$/;" v spice_print_cb_testbench ./fpga_x2p/spice/spice_routing_testbench.c /^void spice_print_cb_testbench(char* formatted_spice_dir,$/;" f @@ -5526,13 +4037,11 @@ spice_print_primitive_testbench ./fpga_x2p/spice/spice_primitive_testbench.c /^v spice_print_sb_testbench ./fpga_x2p/spice/spice_routing_testbench.c /^void spice_print_sb_testbench(char* formatted_spice_dir,$/;" f spice_print_subckt_header_file ./fpga_x2p/spice/spice_utils.c /^void spice_print_subckt_header_file(t_llist* subckt_llist_head,$/;" f spice_print_top_netlist ./fpga_x2p/spice/spice_top_netlist.c /^void spice_print_top_netlist(char* circuit_name,$/;" f -spice_reserved ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean spice_reserved;$/;" m struct:s_reserved_syntax_char spice_sb_mux_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_sb_mux_tb_dir_name = "sb_mux_tb\/";$/;" v file: spice_sb_mux_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_sb_mux_testbench_postfix = "_sbmux_testbench.sp";$/;" v spice_sb_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_sb_tb_dir_name = "sb_tb\/";$/;" v file: spice_sb_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_sb_testbench_postfix = "_sb_testbench.sp";$/;" v spice_sim_multi_thread_num ./fpga_x2p/spice/spice_globals.c /^int spice_sim_multi_thread_num = 8;$/;" v -spice_sram_inf_orgz ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* spice_sram_inf_orgz;$/;" m struct:s_sram_inf spice_tb_global_clock_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_clock_port_name = "gclock";$/;" v spice_tb_global_config_done_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_config_done_port_name = "gconfig_done";$/;" v spice_tb_global_gnd_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_gnd_port_name = "ggnd";$/;" v @@ -5556,29 +4065,15 @@ spice_top_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_top_tb_d spice_top_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_top_testbench_postfix = "_top.sp";$/;" v split_path_prog_name ./fpga_x2p/base/fpga_x2p_utils.c /^int split_path_prog_name(char* prog_path,$/;" f spot_blk_position_in_a_macro ./place/place_macro.c /^int spot_blk_position_in_a_macro(t_pl_macro pl_macros,$/;" f -spot_int_in_array ../../libarchfpga/util.c /^int spot_int_in_array(int array_len, int* array,$/;" f -sram_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_conf_bit* sram_bit;$/;" m struct:s_conf_bit_info -sram_inf ../../libarchfpga/include/physical_types.h /^ t_sram_inf sram_inf;$/;" m struct:s_arch sram_spice_model ./fpga_x2p/spice/spice_globals.c /^t_spice_model* sram_spice_model = NULL;$/;" v sram_spice_orgz_info ./fpga_x2p/spice/spice_globals.c /^t_sram_orgz_info* sram_spice_orgz_info = NULL;$/;" v sram_spice_orgz_type ./fpga_x2p/spice/spice_globals.c /^enum e_sram_orgz sram_spice_orgz_type = SPICE_SRAM_STANDALONE;$/;" v typeref:enum:e_sram_orgz sram_verilog_model ./fpga_x2p/verilog/verilog_global.c /^t_spice_model* sram_verilog_model = NULL;$/;" v stage_gain ./power/power.h /^ float stage_gain;$/;" m struct:s_power_buffer_strength_inf -standalone ../../libarchfpga/include/ezxml.h /^ short standalone; \/* non-zero if *\/$/;" m struct:ezxml_root -standalone_sram_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_standalone_sram_info* standalone_sram_info; \/* Only be allocated when orgz type is standalone *\/$/;" m struct:s_sram_orgz_info start ./base/vpr_types.h /^ int start;$/;" m struct:s_seg_details -start_bits ../../pcre/SRC/internal.h /^ uschar start_bits[32];$/;" m struct:pcre_study_data -start_code ../../pcre/SRC/internal.h /^ const uschar *start_code; \/* For use when recursing *\/$/;" m struct:match_data -start_code ../../pcre/SRC/internal.h /^ const uschar *start_code; \/* The start of the compiled code *\/$/;" m struct:compile_data -start_col ../../libarchfpga/include/physical_types.h /^ int start_col;$/;" m struct:s_grid_loc_def start_hash_table_iterator ./util/hash.c /^struct s_hash_iterator start_hash_table_iterator(void) {$/;" f -start_match ../../pcre/SRC/internal.h /^ const uschar *start_match; \/* Start of this match attempt *\/$/;" m struct:match_data -start_match ../../pcre/SRC/pcre.h /^ int start_match; \/* Offset to start of this match attempt *\/$/;" m struct:pcre_callout_block start_new_cluster ./pack/cluster.c /^static void start_new_cluster($/;" f file: -start_offset ../../pcre/SRC/internal.h /^ int start_offset; \/* The start offset value *\/$/;" m struct:match_data -start_seg_switch ../../libarchfpga/include/arch_types_mrfpga.h /^ short start_seg_switch;$/;" m struct:s_arch_mrfpga start_seg_switch ./mrfpga/mrfpga_globals.c /^short start_seg_switch;$/;" v -start_subject ../../pcre/SRC/internal.h /^ const uschar *start_subject; \/* Start of the subject string *\/$/;" m struct:match_data starting_pin_idx ./power/power.h /^ int starting_pin_idx; \/* Applicable to level 0 only, the overall mux primary input index *\/$/;" m struct:s_mux_node starting_t ./place/place.c /^static float starting_t(float *cost_ptr, float *bb_cost_ptr,$/;" f file: stats_lut_spice_mux ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void stats_lut_spice_mux(t_llist** muxes_head,$/;" f @@ -5598,17 +4093,9 @@ std ./power/power_components.c /^using namespace std;$/;" v std ./power/power_sizing.c /^using namespace std;$/;" v std ./power/power_util.c /^using namespace std;$/;" v stimu_header_file_name ./fpga_x2p/spice/spice_globals.c /^char* stimu_header_file_name = "stimulate_params.sp";$/;" v -stimulate_params ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_stimulate_params stimulate_params;$/;" m struct:s_spice_params store_char_in_data ./timing/slre.c /^static void store_char_in_data(struct slre *r, int ch) {$/;" f file: strength_inf ./power/power.h /^ t_power_buffer_strength_inf * strength_inf;$/;" m struct:s_power_buffer_size_inf -strncmp ../../pcre/SRC/internal.h 47;" d -structure ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_model_mux typeref:enum:s_spice_model_mux::e_spice_model_structure -structure ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_mux_arch typeref:enum:s_spice_mux_arch::e_spice_model_structure -structure ../../libarchfpga/include/physical_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_switch_inf typeref:enum:s_switch_inf::e_spice_model_structure -study_data ../../pcre/SRC/pcre.h /^ void *study_data; \/* Opaque data from pcre_study() *\/$/;" m struct:pcre_extra subckt_dir ./base/vpr_types.h /^ char* subckt_dir;$/;" m struct:s_spice_opts -subject ../../pcre/SRC/pcre.h /^ const char *subject; \/* The subject being matched *\/$/;" m struct:pcre_callout_block -subject_length ../../pcre/SRC/pcre.h /^ int subject_length; \/* The length of the subject *\/$/;" m struct:pcre_callout_block submodule_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* submodule_verilog_file_name = "sub_module.v";$/;" v submodule_verilog_subckt_file_path_head ./fpga_x2p/verilog/verilog_global.c /^t_llist* submodule_verilog_subckt_file_path_head = NULL;$/;" v sum_pin_class ./pack/cluster_feasibility_filter.c /^static void sum_pin_class(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f file: @@ -5623,79 +4110,48 @@ switch_block_type ./base/vpr_types.h /^ enum e_switch_block_type switch_block_ty switch_inf ./base/globals.c /^struct s_switch_inf *switch_inf = NULL; \/* [0..(det_routing_arch.num_switch-1)] *\/$/;" v typeref:struct:s_switch_inf switch_inf ./base/globals_declare.h /^struct s_switch_inf *switch_inf; \/* [0..det_routing_arch.num_switch-1] *\/$/;" v typeref:struct:s_switch_inf switch_inf ./fpga_x2p/base/fpga_x2p_types.h /^ t_switch_inf* switch_inf;$/;" m struct:fpga_spice_rr_graph -switch_num_level ../../libarchfpga/include/physical_types.h /^ int switch_num_level;$/;" m struct:s_switch_inf switches ./base/vpr_types.h /^ short *switches;$/;" m struct:s_rr_node swseg_pattern_change_switch_type ./route/rr_graph_swseg.c /^int swseg_pattern_change_switch_type(int cur_node,$/;" f file: -swseg_patterns ../../libarchfpga/include/physical_types.h /^ t_swseg_pattern_inf* swseg_patterns;$/;" m struct:s_arch swseg_patterns ./base/vpr_types.h /^ t_swseg_pattern_inf* swseg_patterns; \/* Xifan TANG: Switch Segment Pattern Support *\/$/;" m struct:s_vpr_setup syn_verilog_dump_dir ./base/vpr_types.h /^ char* syn_verilog_dump_dir;$/;" m struct:s_syn_verilog_opts sync_arch_mrfpga_globals ./mrfpga/mrfpga_api.c /^void sync_arch_mrfpga_globals(t_arch_mrfpga arch_mrfpga) {$/;" f sync_grid_to_blocks ./util/vpr_utils.c /^void sync_grid_to_blocks(INP int L_num_blocks,$/;" f sync_pb_graph_pin_vpack_net_num_to_phy_pb ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void sync_pb_graph_pin_vpack_net_num_to_phy_pb(t_rr_node* cur_op_pb_rr_graph, $/;" f -syntax_char ../../libarchfpga/fpga_spice_include/spice_types.h /^ char syntax_char;$/;" m struct:s_reserved_syntax_char szAppName ./base/graphics.c /^static TCHAR szAppName[256], $/;" v file: szButtonsName ./base/graphics.c /^szButtonsName[] = TEXT("VPR Buttons");$/;" v file: szGraphicsName ./base/graphics.c /^szGraphicsName[] = TEXT("VPR Graphics"), $/;" v file: szStatusName ./base/graphics.c /^szStatusName[] = TEXT("VPR Status"),$/;" v file: -t_arch ../../libarchfpga/include/physical_types.h /^typedef struct s_arch t_arch;$/;" t typeref:struct:s_arch -t_arch_mrfpga ../../libarchfpga/include/arch_types_mrfpga.h /^typedef struct s_arch_mrfpga t_arch_mrfpga;$/;" t typeref:struct:s_arch_mrfpga t_bb ./base/vpr_types.h /^typedef struct s_bb t_bb;$/;" t typeref:struct:s_bb t_bitstream_gen_opts ./base/vpr_types.h /^typedef struct s_bitstream_gen_opts t_bitstream_gen_opts;$/;" t typeref:struct:s_bitstream_gen_opts t_block ./base/vpr_types.h /^typedef struct s_block t_block;$/;" t typeref:struct:s_block -t_buffer_inf ../../libarchfpga/include/arch_types_mrfpga.h /^typedef struct s_buffer_inf t_buffer_inf;$/;" t typeref:struct:s_buffer_inf t_buffer_plan ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" t typeref:struct:s_buffer_plan file: t_buffer_plan_list ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_list { t_buffer_plan_node* front; } t_buffer_plan_list;$/;" t typeref:struct:s_buffer_plan_list file: t_buffer_plan_node ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node;$/;" t typeref:struct:s_buffer_plan_node file: t_button ./base/graphics.c /^} t_button;$/;" t typeref:struct:__anon4 file: t_button_type ./base/graphics.c /^} t_button_type;$/;" t typeref:enum:__anon3 file: t_cb ./base/vpr_types.h /^typedef struct s_cb t_cb;$/;" t typeref:struct:s_cb -t_chan ../../libarchfpga/include/physical_types.h /^} t_chan;$/;" t typeref:struct:s_chan -t_chan_width_dist ../../libarchfpga/include/physical_types.h /^} t_chan_width_dist;$/;" t typeref:struct:s_chan_width_dist -t_chunk ../../libarchfpga/include/util.h /^} t_chunk;$/;" t typeref:struct:s_chunk -t_class ../../libarchfpga/include/physical_types.h /^typedef struct s_class t_class;$/;" t typeref:struct:s_class t_clb_to_clb_directs ./base/vpr_types.h /^} t_clb_to_clb_directs;$/;" t typeref:struct:s_clb_to_clb_directs t_clock ./base/vpr_types.h /^} t_clock;$/;" t typeref:struct:s_clock -t_clock_arch ../../libarchfpga/include/physical_types.h /^typedef struct s_clock_arch t_clock_arch;$/;" t typeref:struct:s_clock_arch -t_clock_network ../../libarchfpga/include/physical_types.h /^typedef struct s_clock_network t_clock_network;$/;" t typeref:struct:s_clock_network -t_cluster_placement_primitive ../../libarchfpga/include/cad_types.h /^} t_cluster_placement_primitive;$/;" t typeref:struct:s_cluster_placement_primitive t_cluster_placement_stats ./base/vpr_types.h /^} t_cluster_placement_stats;$/;" t typeref:struct:s_cluster_placement_stats t_cmd_category ./fpga_x2p/shell/shell_types.h /^typedef struct s_cmd_category t_cmd_category;$/;" t typeref:struct:s_cmd_category t_cmd_info ./fpga_x2p/shell/read_opt_types.h /^typedef struct s_cmd_info t_cmd_info;$/;" t typeref:struct:s_cmd_info -t_conf_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_conf_bit t_conf_bit;$/;" t typeref:struct:s_conf_bit -t_conf_bit_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_conf_bit_info t_conf_bit_info;$/;" t typeref:struct:s_conf_bit_info t_det_routing_arch ./base/vpr_types.h /^typedef struct s_det_routing_arch t_det_routing_arch;$/;" t typeref:struct:s_det_routing_arch -t_direct_inf ../../libarchfpga/include/physical_types.h /^} t_direct_inf;$/;" t typeref:struct:s_direct_inf t_display_type ./base/graphics.c /^} t_display_type;$/;" t typeref:enum:__anon2 file: t_fmap_cell ./base/place_and_route.h /^} t_fmap_cell;$/;" t typeref:struct:s_fmap_cell t_fpga_spice_opts ./base/vpr_types.h /^typedef struct s_fpga_spice_opts t_fpga_spice_opts;$/;" t typeref:struct:s_fpga_spice_opts t_gl_state ./base/graphics.c /^} t_gl_state;$/;" t typeref:struct:__anon5 file: t_graph_type ./route/rr_graph.h /^typedef enum e_graph_type t_graph_type;$/;" t typeref:enum:e_graph_type -t_grid_loc_def ../../libarchfpga/include/physical_types.h /^} t_grid_loc_def;$/;" t typeref:struct:s_grid_loc_def t_grid_tile ./base/vpr_types.h /^} t_grid_tile;$/;" t typeref:struct:s_grid_tile t_heap ./route/route_common.h /^typedef struct s_heap t_heap;$/;" t typeref:struct:s_heap -t_interconnect ../../libarchfpga/include/physical_types.h /^typedef struct s_interconnect t_interconnect;$/;" t typeref:struct:s_interconnect -t_interconnect_pins ../../libarchfpga/include/physical_types.h /^typedef struct s_interconnect_pins t_interconnect_pins;$/;" t typeref:struct:s_interconnect_pins -t_interconnect_power ../../libarchfpga/include/physical_types.h /^typedef struct s_interconnect_power t_interconnect_power;$/;" t typeref:struct:s_interconnect_power t_io ./base/vpr_types.h /^} t_io;$/;" t typeref:struct:s_io -t_ivec ../../libarchfpga/include/util.h /^} t_ivec;$/;" t typeref:struct:s_ivec t_legal_pos ./place/place.c /^}t_legal_pos;$/;" t typeref:struct:s_legal_pos file: t_linked_edge ./route/rr_graph_util.h /^typedef struct s_linked_edge t_linked_edge;$/;" t typeref:struct:s_linked_edge t_linked_f_pointer ./base/vpr_types.h /^typedef struct s_linked_f_pointer t_linked_f_pointer;$/;" t typeref:struct:s_linked_f_pointer -t_linked_int ../../libarchfpga/include/util.h /^} t_linked_int;$/;" t typeref:struct:s_linked_int t_linked_rc_edge ./timing/net_delay_types.h /^typedef struct s_linked_rc_edge t_linked_rc_edge;$/;" t typeref:struct:s_linked_rc_edge t_linked_rc_ptr ./timing/net_delay_types.h /^typedef struct s_linked_rc_ptr t_linked_rc_ptr;$/;" t typeref:struct:s_linked_rc_ptr t_linked_rt_edge ./route/route_tree_timing.h /^typedef struct s_linked_rt_edge t_linked_rt_edge;$/;" t typeref:struct:s_linked_rt_edge -t_linked_vptr ../../libarchfpga/include/util.h /^} t_linked_vptr;$/;" t typeref:struct:s_linked_vptr -t_llist ../../libarchfpga/fpga_spice_include/linkedlist.h /^typedef struct s_llist t_llist;$/;" t typeref:struct:s_llist t_log ./power/power.h /^typedef struct s_log t_log;$/;" t typeref:struct:s_log t_logical_block ./base/vpr_types.h /^} t_logical_block;$/;" t typeref:struct:s_logical_block -t_mem_bank_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_mem_bank_info t_mem_bank_info;$/;" t typeref:struct:s_mem_bank_info -t_memristor_inf ../../libarchfpga/include/arch_types_mrfpga.h /^typedef struct s_memristor_inf t_memristor_inf;$/;" t typeref:struct:s_memristor_inf -t_mode ../../libarchfpga/include/physical_types.h /^typedef struct s_mode t_mode;$/;" t typeref:struct:s_mode -t_mode_power ../../libarchfpga/include/physical_types.h /^typedef struct s_mode_power t_mode_power;$/;" t typeref:struct:s_mode_power -t_model ../../libarchfpga/include/logic_types.h /^} t_model;$/;" t typeref:struct:s_model -t_model_chain_pattern ../../libarchfpga/include/cad_types.h /^} t_model_chain_pattern;$/;" t typeref:struct:s_model_chain_pattern -t_model_ports ../../libarchfpga/include/logic_types.h /^} t_model_ports;$/;" t typeref:struct:s_model_ports t_mux ./route/rr_graph.c /^} t_mux;$/;" t typeref:struct:s_mux file: t_mux_arch ./power/power.h /^typedef struct s_mux_arch t_mux_arch;$/;" t typeref:struct:s_mux_arch t_mux_node ./power/power.h /^typedef struct s_mux_node t_mux_node;$/;" t typeref:struct:s_mux_node @@ -5707,34 +4163,19 @@ t_opt_info ./fpga_x2p/shell/read_opt_types.h /^typedef struct s_opt_info t_opt_i t_options ./base/ReadOptions.h /^typedef struct s_options t_options;$/;" t typeref:struct:s_options t_override_constraint ./base/vpr_types.h /^} t_override_constraint;$/;" t typeref:struct:s_override_constraint t_pack_molecule ./base/vpr_types.h /^} t_pack_molecule;$/;" t typeref:struct:s_pack_molecule -t_pack_pattern_block ../../libarchfpga/include/cad_types.h /^} t_pack_pattern_block;$/;" t typeref:struct:s_pack_pattern_block -t_pack_pattern_connections ../../libarchfpga/include/cad_types.h /^} t_pack_pattern_connections;$/;" t typeref:struct:s_pack_pattern_connections -t_pack_patterns ../../libarchfpga/include/cad_types.h /^} t_pack_patterns;$/;" t typeref:struct:s_pack_patterns t_pb ./base/vpr_types.h /^} t_pb;$/;" t typeref:struct:s_pb -t_pb_graph_edge ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_graph_edge t_pb_graph_edge;$/;" t typeref:struct:s_pb_graph_edge -t_pb_graph_node ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_graph_node t_pb_graph_node;$/;" t typeref:struct:s_pb_graph_node -t_pb_graph_node_power ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_graph_node_power t_pb_graph_node_power;$/;" t typeref:struct:s_pb_graph_node_power -t_pb_graph_pin ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_graph_pin t_pb_graph_pin;$/;" t typeref:struct:s_pb_graph_pin -t_pb_graph_pin_power ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_graph_pin_power t_pb_graph_pin_power;$/;" t typeref:struct:s_pb_graph_pin_power t_pb_stats ./base/vpr_types.h /^} t_pb_stats;$/;" t typeref:struct:s_pb_stats -t_pb_type ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_type t_pb_type;$/;" t typeref:struct:s_pb_type -t_pb_type_power ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_type_power t_pb_type_power;$/;" t typeref:struct:s_pb_type_power t_phy_pb ./fpga_x2p/base/fpga_x2p_types.h /^typedef struct fpga_spice_phy_pb t_phy_pb;$/;" t typeref:struct:fpga_spice_phy_pb -t_pin_to_pin_annotation ../../libarchfpga/include/physical_types.h /^typedef struct s_pin_to_pin_annotation t_pin_to_pin_annotation;$/;" t typeref:struct:s_pin_to_pin_annotation t_pl_blocks_to_be_moved ./place/place.c /^}t_pl_blocks_to_be_moved;$/;" t typeref:struct:s_pl_blocks_to_be_moved file: t_pl_macro ./place/place_macro.h /^} t_pl_macro;$/;" t typeref:struct:s_pl_macro t_pl_macro_member ./place/place_macro.h /^} t_pl_macro_member;$/;" t typeref:struct:s_pl_macro_member t_pl_moved_block ./place/place.c /^}t_pl_moved_block;$/;" t typeref:struct:s_pl_moved_block file: t_point ./base/easygl_constants.h /^} t_point; \/* Used in calls to fillpoly *\/$/;" t typeref:struct:__anon1 -t_port ../../libarchfpga/include/physical_types.h /^typedef struct s_port t_port;$/;" t typeref:struct:s_port -t_port_power ../../libarchfpga/include/physical_types.h /^typedef struct s_port_power t_port_power;$/;" t typeref:struct:s_port_power -t_power_arch ../../libarchfpga/include/physical_types.h /^typedef struct s_power_arch t_power_arch;$/;" t typeref:struct:s_power_arch t_power_buffer_sc_levr_inf ./power/power.h /^typedef struct s_power_buffer_sc_levr_inf t_power_buffer_sc_levr_inf;$/;" t typeref:struct:s_power_buffer_sc_levr_inf t_power_buffer_size_inf ./power/power.h /^typedef struct s_power_buffer_size_inf t_power_buffer_size_inf;$/;" t typeref:struct:s_power_buffer_size_inf t_power_buffer_strength_inf ./power/power.h /^typedef struct s_power_buffer_strength_inf t_power_buffer_strength_inf;$/;" t typeref:struct:s_power_buffer_strength_inf t_power_commonly_used ./power/power.h /^typedef struct s_power_commonly_used t_power_commonly_used;$/;" t typeref:struct:s_power_commonly_used t_power_components ./power/power_components.h /^typedef struct s_power_breakdown t_power_components;$/;" t typeref:struct:s_power_breakdown -t_power_estimation_method ../../libarchfpga/include/physical_types.h /^typedef enum e_power_estimation_method_ t_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ t_power_mux_info ./power/power.h /^typedef struct s_power_mux_info t_power_mux_info;$/;" t typeref:struct:s_power_mux_info t_power_mux_volt_inf ./power/power.h /^typedef struct s_power_mux_volt_inf t_power_mux_volt_inf;$/;" t typeref:struct:s_power_mux_volt_inf t_power_mux_volt_pair ./power/power.h /^typedef struct s_power_mux_volt_pair t_power_mux_volt_pair;$/;" t typeref:struct:s_power_mux_volt_pair @@ -5745,11 +4186,9 @@ t_power_nmos_mux_inf ./power/power.h /^typedef struct s_power_nmos_mux_inf t_pow t_power_opts ./base/vpr_types.h /^typedef struct s_power_opts t_power_opts;$/;" t typeref:struct:s_power_opts t_power_output ./power/power.h /^typedef struct s_power_output t_power_output;$/;" t typeref:struct:s_power_output t_power_tech ./power/power.h /^typedef struct s_power_tech t_power_tech;$/;" t typeref:struct:s_power_tech -t_power_usage ../../libarchfpga/include/physical_types.h /^typedef struct s_power_usage t_power_usage;$/;" t typeref:struct:s_power_usage t_prepacked_tnode_data ./base/vpr_types.h /^} t_prepacked_tnode_data;$/;" t typeref:struct:s_prepacked_tnode_data t_rc_node ./timing/net_delay_types.h /^typedef struct s_rc_node t_rc_node;$/;" t typeref:struct:s_rc_node t_report ./base/graphics.h /^} t_report;$/;" t typeref:struct:__anon6 -t_reserved_syntax_char ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_reserved_syntax_char t_reserved_syntax_char;$/;" t typeref:struct:s_reserved_syntax_char t_router_opts ./base/vpr_types.h /^typedef struct s_router_opts t_router_opts;$/;" t typeref:struct:s_router_opts t_rr_graph ./fpga_x2p/base/fpga_x2p_types.h /^typedef struct fpga_spice_rr_graph t_rr_graph;$/;" t typeref:struct:fpga_spice_rr_graph t_rr_indexed_data ./base/vpr_types.h /^} t_rr_indexed_data;$/;" t typeref:struct:s_rr_indexed_data @@ -5759,53 +4198,18 @@ t_rr_node_route_inf ./route/route_common.h /^} t_rr_node_route_inf;$/;" t typere t_rr_type ./base/vpr_types.h /^} t_rr_type;$/;" t typeref:enum:e_rr_type t_rt_node ./route/route_tree_timing.h /^typedef struct s_rt_node t_rt_node;$/;" t typeref:struct:s_rt_node t_sb ./base/vpr_types.h /^typedef struct s_sb t_sb;$/;" t typeref:struct:s_sb -t_scff_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_scff_info t_scff_info;$/;" t typeref:struct:s_scff_info t_sdc_clock ./timing/read_sdc.c /^} t_sdc_clock;$/;" t typeref:struct:s_sdc_clock file: t_sdc_exclusive_group ./timing/read_sdc.c /^} t_sdc_exclusive_group;$/;" t typeref:struct:s_sdc_exclusive_group file: t_sdc_opts ./fpga_x2p/verilog/verilog_sdc.c /^typedef struct s_sdc_opts t_sdc_opts;$/;" t typeref:struct:s_sdc_opts file: t_seg_details ./base/vpr_types.h /^} t_seg_details;$/;" t typeref:struct:s_seg_details -t_segment_inf ../../libarchfpga/include/physical_types.h /^} t_segment_inf;$/;" t typeref:struct:s_segment_inf t_shell_cmd ./fpga_x2p/shell/shell_types.h /^typedef struct s_shell_cmd t_shell_cmd;$/;" t typeref:struct:s_shell_cmd t_shell_env ./fpga_x2p/shell/shell_types.h /^typedef struct s_shell_env t_shell_env;$/;" t typeref:struct:s_shell_env t_slack ./base/vpr_types.h /^} t_slack;$/;" t typeref:struct:s_slack t_solution_inf ./power/power.h /^typedef struct s_solution_inf t_solution_inf;$/;" t typeref:struct:s_solution_inf -t_spice ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice t_spice;$/;" t typeref:struct:s_spice -t_spice_mc_params ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_params t_spice_mc_params;$/;" t typeref:struct:s_spice_mc_params -t_spice_mc_variation_params ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_variation_params t_spice_mc_variation_params;$/;" t typeref:struct:s_spice_mc_variation_params -t_spice_meas_params ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_meas_params t_spice_meas_params;$/;" t typeref:struct:s_spice_meas_params -t_spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model t_spice_model;$/;" t typeref:struct:s_spice_model -t_spice_model_buffer ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_buffer t_spice_model_buffer;$/;" t typeref:struct:s_spice_model_buffer -t_spice_model_delay_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_delay_info t_spice_model_delay_info;$/;" t typeref:struct:s_spice_model_delay_info -t_spice_model_design_tech_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_design_tech_info t_spice_model_design_tech_info;$/;" t typeref:struct:s_spice_model_design_tech_info -t_spice_model_gate ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_gate t_spice_model_gate;$/;" t typeref:struct:s_spice_model_gate -t_spice_model_lut ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_lut t_spice_model_lut;$/;" t typeref:struct:s_spice_model_lut -t_spice_model_mux ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_mux t_spice_model_mux;$/;" t typeref:struct:s_spice_model_mux -t_spice_model_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_netlist t_spice_model_netlist;$/;" t typeref:struct:s_spice_model_netlist -t_spice_model_pass_gate_logic ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_pass_gate_logic t_spice_model_pass_gate_logic;$/;" t typeref:struct:s_spice_model_pass_gate_logic -t_spice_model_port ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_port t_spice_model_port;$/;" t typeref:struct:s_spice_model_port -t_spice_model_rram ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_rram t_spice_model_rram;$/;" t typeref:struct:s_spice_model_rram -t_spice_model_tedge ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_tedge t_spice_model_tedge;$/;" t typeref:struct:s_spice_model_tedge -t_spice_model_wire_param ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_wire_param t_spice_model_wire_param;$/;" t typeref:struct:s_spice_model_wire_param -t_spice_mux_arch ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_arch t_spice_mux_arch;$/;" t typeref:struct:s_spice_mux_arch -t_spice_mux_model ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_model t_spice_mux_model;$/;" t typeref:struct:s_spice_mux_model -t_spice_net_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_net_info t_spice_net_info;$/;" t typeref:struct:s_spice_net_info t_spice_opts ./base/vpr_types.h /^typedef struct s_spice_opts t_spice_opts;$/;" t typeref:struct:s_spice_opts -t_spice_params ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_params t_spice_params;$/;" t typeref:struct:s_spice_params -t_spice_stimulate_params ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_stimulate_params t_spice_stimulate_params;$/;" t typeref:struct:s_spice_stimulate_params -t_spice_tech_lib ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_tech_lib t_spice_tech_lib;$/;" t typeref:struct:s_spice_tech_lib -t_spice_transistor_type ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_transistor_type t_spice_transistor_type;$/;" t typeref:struct:s_spice_transistor_type -t_spicetb_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spicetb_info t_spicetb_info;$/;" t typeref:struct:s_spicetb_info -t_sram_inf ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_sram_inf t_sram_inf;$/;" t typeref:struct:s_sram_inf -t_sram_inf_orgz ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_sram_inf_orgz t_sram_inf_orgz;$/;" t typeref:struct:s_sram_inf_orgz -t_sram_orgz_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_sram_orgz_info t_sram_orgz_info;$/;" t typeref:struct:s_sram_orgz_info -t_standalone_sram_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_standalone_sram_info t_standalone_sram_info;$/;" t typeref:struct:s_standalone_sram_info -t_switch_block_type ../../libarchfpga/include/physical_types.h /^typedef enum e_switch_block_type t_switch_block_type;$/;" t typeref:enum:e_switch_block_type -t_switch_inf ../../libarchfpga/include/physical_types.h /^} t_switch_inf;$/;" t typeref:struct:s_switch_inf -t_swseg_pattern_inf ../../libarchfpga/include/physical_types.h /^typedef struct s_swseg_pattern_inf t_swseg_pattern_inf;$/;" t typeref:struct:s_swseg_pattern_inf t_syn_verilog_opts ./base/vpr_types.h /^typedef struct s_syn_verilog_opts t_syn_verilog_opts;$/;" t typeref:struct:s_syn_verilog_opts t_tedge ./base/vpr_types.h /^} t_tedge;$/;" t typeref:struct:s_tedge t_timing_constraints ./base/vpr_types.h /^} t_timing_constraints;$/;" t typeref:struct:s_timing_constraints -t_timing_inf ../../libarchfpga/include/physical_types.h /^} t_timing_inf;$/;" t typeref:struct:s_timing_inf t_timing_stats ./base/vpr_types.h /^} t_timing_stats;$/;" t typeref:struct:s_timing_stats t_tnode ./base/vpr_types.h /^} t_tnode;$/;" t typeref:struct:s_tnode t_token ./util/token.h /^typedef struct s_token t_token;$/;" t typeref:struct:s_token @@ -5813,35 +4217,21 @@ t_trace ./base/vpr_types.h /^} t_trace;$/;" t typeref:struct:s_trace t_transistor_inf ./power/power.h /^typedef struct s_transistor_inf t_transistor_inf;$/;" t typeref:struct:s_transistor_inf t_transistor_size_inf ./power/power.h /^typedef struct s_transistor_size_inf t_transistor_size_inf;$/;" t typeref:struct:s_transistor_size_inf t_trpt_opts ./fpga_x2p/verilog/verilog_report_timing.c /^typedef struct s_trpt_opts t_trpt_opts;$/;" t typeref:struct:s_trpt_opts file: -t_type_descriptor ../../libarchfpga/include/physical_types.h /^typedef struct s_type_descriptor t_type_descriptor;$/;" t typeref:struct:s_type_descriptor -t_type_ptr ../../libarchfpga/include/physical_types.h /^typedef const struct s_type_descriptor *t_type_ptr;$/;" t typeref:struct:s_type_descriptor t_vpr_setup ./base/vpr_types.h /^} t_vpr_setup;$/;" t typeref:struct:s_vpr_setup t_wireL_cnt ./fpga_x2p/verilog/verilog_report_timing.c /^typedef struct s_wireL_cnt t_wireL_cnt;$/;" t typeref:struct:s_wireL_cnt file: -tables ../../pcre/SRC/internal.h /^ const unsigned char *tables; \/* Pointer to tables *\/$/;" m struct:real_pcre -tables_length ../../pcre/SRC/internal.h 657;" d tag ./fpga_x2p/shell/read_opt_types.h /^ char* tag; \/* tag of option *\/$/;" m struct:s_opt_info -tap_buf_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int tap_buf_level;$/;" m struct:s_spice_model_buffer -tapered_buf ../../libarchfpga/fpga_spice_include/spice_types.h /^ int tapered_buf; \/*Valid only when this is a buffer*\/$/;" m struct:s_spice_model_buffer target_flag ./route/route_common.h /^ short target_flag;$/;" m struct:__anon15 -tb_cnt ../../libarchfpga/fpga_spice_include/spice_types.h /^ int tb_cnt;$/;" m struct:s_spice_model tb_head ./fpga_x2p/spice/spice_globals.c /^t_llist* tb_head = NULL;$/;" v -tb_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* tb_name;$/;" m struct:s_spicetb_info tb_num_grid ./fpga_x2p/spice/spice_grid_testbench.c /^static int tb_num_grid = 0;$/;" v file: tb_num_primitive ./fpga_x2p/spice/spice_primitive_testbench.c /^static int tb_num_primitive = 0;$/;" v file: td_place_exp_first ./base/vpr_types.h /^ float td_place_exp_first;$/;" m struct:s_placer_opts td_place_exp_last ./base/vpr_types.h /^ float td_place_exp_last;$/;" m struct:s_placer_opts -tech_comp ../../libarchfpga/include/arch_types_mrfpga.h /^ enum e_tech_comp tech_comp;$/;" m struct:s_arch_mrfpga typeref:enum:s_arch_mrfpga::e_tech_comp -tech_lib ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_tech_lib tech_lib;$/;" m struct:s_spice tech_size ./power/power.h /^ float tech_size; \/* Tech size in nm, for example 90e-9 for 90nm *\/$/;" m struct:s_power_tech -tedge ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_tedge*** tedge; \/* 3-D array, considering the each pin in this port, [pin_number][num_edges[iedge]] is an edge pointor *\/$/;" m struct:s_spice_model_port tedge_ch ./timing/path_delay.c /^static t_chunk tedge_ch = {NULL, 0, NULL};$/;" v file: temp_net_cost ./place/place.c /^static float *net_cost = NULL, *temp_net_cost = NULL; \/* [0..num_nets-1] *\/$/;" v file: -temp_net_num ../../libarchfpga/include/physical_types.h /^ int temp_net_num;$/;" m struct:s_pb_graph_pin temp_num_pins ./base/read_blif.c /^static int *num_driver, *temp_num_pins;$/;" v file: -temp_placement_index ../../libarchfpga/include/physical_types.h /^ int temp_placement_index;$/;" m struct:s_pb_type temp_point_to_point_delay_cost ./place/place.c /^static float **temp_point_to_point_delay_cost = NULL;$/;" v file: temp_point_to_point_timing_cost ./place/place.c /^static float **temp_point_to_point_timing_cost = NULL;$/;" v file: -temp_scratch_pad ../../libarchfpga/include/physical_types.h /^ void *temp_scratch_pad; \/* temporary data, useful for keeping track of things when traversing data structure *\/$/;" m struct:s_pb_graph_node temp_used ./base/vpr_types.h /^ int temp_used;$/;" m struct:s_logical_block temperature ./power/power.h /^ float temperature; \/* Temp in C *\/$/;" m struct:s_power_tech test_if_exposed ./base/graphics.c /^static Bool test_if_exposed (Display *disp, XEvent *event_ptr, XPointer dummy) $/;" f file: @@ -5857,13 +4247,11 @@ testbench_sb_mux_cnt ./fpga_x2p/spice/spice_mux_testbench.c /^static int testben testbench_sram_cnt ./fpga_x2p/spice/spice_mux_testbench.c /^static int testbench_sram_cnt = 0;$/;" v file: text ./base/graphics.c /^ char text[BUTTON_TEXT_LEN]; $/;" m struct:__anon4 file: textarea ./base/graphics.c /^static Window toplevel, menu, textarea; \/* various windows *\/$/;" v file: -tfall ../../libarchfpga/fpga_spice_include/spice_types.h /^ float tfall; \/* Fall condition: delay *\/$/;" m struct:s_spice_model_tedge tie_break_high_fanout_net ./base/vpr_types.h /^ int tie_break_high_fanout_net; \/* If no marked candidate atoms, use this high fanout net to determine the next candidate atom *\/$/;" m struct:s_pb_stats tile_length ./power/power.h /^ float tile_length;$/;" m struct:s_power_commonly_used tile_width ./base/draw.c /^static float tile_width, pin_size;$/;" v file: tile_x ./base/draw.c /^static float *tile_x, *tile_y;$/;" v file: tile_y ./base/draw.c /^static float *tile_x, *tile_y;$/;" v file: -timing_analysis_enabled ../../libarchfpga/include/physical_types.h /^ boolean timing_analysis_enabled;$/;" m struct:s_timing_inf timing_criticality ./base/vpr_types.h /^ float ** timing_criticality;$/;" m struct:s_slack timing_driven ./base/ReadOptions.h /^ boolean timing_driven;$/;" m struct:s_options timing_driven ./base/vpr_types.h /^ boolean timing_driven;$/;" m struct:s_packer_opts @@ -5878,22 +4266,14 @@ timinggain ./base/vpr_types.h /^ std::map timinggain; \/* [0..num_lo tnode ./base/vpr_types.h /^ t_tnode *tnode;$/;" m struct:s_rr_node tnode ./timing/path_delay.c /^t_tnode *tnode = NULL; \/* [0..num_tnodes - 1] *\/$/;" v tnodes_at_level ./timing/path_delay2.c /^struct s_ivec *tnodes_at_level;$/;" v typeref:struct:s_ivec -to_block ../../libarchfpga/include/cad_types.h /^ t_pack_pattern_block *to_block;$/;" m struct:s_pack_pattern_connections to_clb_pin_end_index ./base/vpr_types.h /^ int to_clb_pin_end_index;$/;" m struct:s_clb_to_clb_directs to_clb_pin_start_index ./base/vpr_types.h /^ int to_clb_pin_start_index;$/;" m struct:s_clb_to_clb_directs to_clb_type ./base/vpr_types.h /^ t_type_descriptor *to_clb_type;$/;" m struct:s_clb_to_clb_directs to_node ./base/vpr_types.h /^ int to_node; \/* index of node at the sink end of this edge *\/$/;" m struct:s_tedge -to_pin ../../libarchfpga/include/cad_types.h /^ t_pb_graph_pin *to_pin;$/;" m struct:s_pack_pattern_connections -to_pin ../../libarchfpga/include/physical_types.h /^ char *to_pin;$/;" m struct:s_direct_inf -to_port ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_port* to_port;$/;" m struct:s_spice_model_tedge -to_port_pin_number ../../libarchfpga/fpga_spice_include/spice_types.h /^ int to_port_pin_number;$/;" m struct:s_spice_model_tedge toggle_congestion ./base/draw.c /^static void toggle_congestion(void (*drawscreen_ptr)(void)) {$/;" f file: toggle_defects ./base/draw.c /^static void toggle_defects(void (*drawscreen_ptr)(void)) {$/;" f file: toggle_nets ./base/draw.c /^static void toggle_nets(void (*drawscreen_ptr)(void)) {$/;" f file: toggle_rr ./base/draw.c /^static void toggle_rr(void (*drawscreen_ptr)(void)) {$/;" f file: -top_backref ../../pcre/SRC/internal.h /^ int top_backref; \/* Maximum back reference *\/$/;" m struct:compile_data -top_backref ../../pcre/SRC/internal.h /^ unsigned short int top_backref;$/;" m struct:real_pcre -top_bracket ../../pcre/SRC/internal.h /^ unsigned short int top_bracket;$/;" m struct:real_pcre top_height ./base/graphics.c /^static int top_width, top_height; \/* window size *\/$/;" v file: top_height ./base/graphics.h /^ int top_width, top_height;$/;" m struct:__anon6 top_netlist_addr_bl_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_addr_bl_port_name = "addr_bl";$/;" v @@ -5928,7 +4308,6 @@ toplevel ./base/graphics.c /^static Window toplevel, menu, textarea; \/* variou total_cb_buffer_size ./power/power.h /^ float total_cb_buffer_size;$/;" m struct:s_power_commonly_used total_cb_mux_input_density ./fpga_x2p/spice/spice_mux_testbench.c /^static float total_cb_mux_input_density = 0.;$/;" v file: total_pb_mux_input_density ./fpga_x2p/spice/spice_mux_testbench.c /^static float total_pb_mux_input_density = 0.;$/;" v file: -total_pb_pins ../../libarchfpga/include/physical_types.h /^ int total_pb_pins; \/* only valid for top-level *\/$/;" m struct:s_pb_graph_node total_sb_buffer_size ./power/power.h /^ float total_sb_buffer_size;$/;" m struct:s_power_commonly_used total_sb_mux_input_density ./fpga_x2p/spice/spice_mux_testbench.c /^static float total_sb_mux_input_density = 0.;$/;" v file: trace_ch ./fpga_x2p/base/fpga_x2p_types.h /^ t_chunk trace_ch;$/;" m struct:fpga_spice_rr_graph @@ -5944,16 +4323,9 @@ trace_tail ./fpga_x2p/base/fpga_x2p_types.h /^ t_trace **trace_tail; \/* [0..(n trans_per_R ./route/rr_graph_area.c /^static float trans_per_R(float Rtrans, float R_minW_trans) {$/;" f file: trans_per_buf ./route/rr_graph_area.c /^float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos) {$/;" f trans_per_mux ./route/rr_graph_area.c /^static float trans_per_mux(int num_inputs, float trans_sram_bit,$/;" f file: -transistor_cnt ../../libarchfpga/include/physical_types.h /^ float transistor_cnt;$/;" m struct:s_interconnect_power -transistor_cnt_buffers ../../libarchfpga/include/physical_types.h /^ float transistor_cnt_buffers;$/;" m struct:s_pb_graph_node_power -transistor_cnt_interc ../../libarchfpga/include/physical_types.h /^ float transistor_cnt_interc; \/* Total transistor size of the interconnect in this pb *\/$/;" m struct:s_pb_graph_node_power -transistor_cnt_pb_children ../../libarchfpga/include/physical_types.h /^ float transistor_cnt_pb_children; \/* Total transistor size of this pb *\/$/;" m struct:s_pb_graph_node_power transistor_size ./power/PowerSpicedComponent.h /^ float transistor_size;$/;" m class:PowerCallibSize transistor_size ./power/power.h /^ float transistor_size;$/;" m struct:s_mux_arch -transistor_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* transistor_type;$/;" m struct:s_spice_tech_lib transistor_type_name ./power/power_util.c /^char * transistor_type_name(e_tx_type type) {$/;" f -transistor_types ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_transistor_type* transistor_types;$/;" m struct:s_spice_tech_lib -transistors_per_SRAM_bit ../../libarchfpga/include/physical_types.h /^ float transistors_per_SRAM_bit;$/;" m struct:s_power_arch translate_down ./base/graphics.c /^translate_down (void (*drawscreen) (void)) $/;" f file: translate_left ./base/graphics.c /^translate_left (void (*drawscreen) (void)) $/;" f file: translate_right ./base/graphics.c /^translate_right (void (*drawscreen) (void)) $/;" f file: @@ -5962,10 +4334,8 @@ traverse_clb ./base/verilog_writer.c /^pb_list *traverse_clb(t_pb *pb , pb_list traverse_linked_list ./base/verilog_writer.c /^void traverse_linked_list(pb_list *list)$/;" f traverse_linked_list_conn ./base/verilog_writer.c /^void traverse_linked_list_conn(conn_list *list)$/;" f tree_mux_last_level_input_num ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int tree_mux_last_level_input_num(int num_level,$/;" f -tri_state_map ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* tri_state_map;$/;" m struct:s_spice_model_port tried ./base/vpr_types.h /^ t_cluster_placement_primitive *tried; \/* ptrs to primitives that are open but current logic block unable to pack to *\/$/;" m struct:s_cluster_placement_stats trigger_type ./base/vpr_types.h /^ char* trigger_type;$/;" m struct:s_logical_block -trise ../../libarchfpga/fpga_spice_include/spice_types.h /^ float trise; \/* Rise condition: delay *\/$/;" m struct:s_spice_model_tedge trpt_routing_file_name ./fpga_x2p/verilog/verilog_global.c /^char* trpt_routing_file_name = "report_timing_routing.tcl";$/;" v trpt_sb_file_name ./fpga_x2p/verilog/verilog_global.c /^char* trpt_sb_file_name = "report_timing_sb.tcl";$/;" v truth_table ./base/vpr_types.h /^ struct s_linked_vptr *truth_table; \/* If this is a LUT (.names), then this is the logic that the LUT implements *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_linked_vptr @@ -5996,29 +4366,8 @@ try_update_sram_orgz_info_reserved_blwl ./fpga_x2p/base/fpga_x2p_utils.c /^void ts_bb_coord_new ./place/place.c /^static struct s_bb *ts_bb_coord_new = NULL;$/;" v typeref:struct:s_bb file: ts_bb_edge_new ./place/place.c /^static struct s_bb *ts_bb_edge_new = NULL;$/;" v typeref:struct:s_bb file: ts_nets_to_update ./place/place.c /^static int *ts_nets_to_update = NULL;$/;" v file: -tsu_tco ../../libarchfpga/include/physical_types.h /^ float tsu_tco; \/* For sequential logic elements, this is the setup time (if input) or clock-to-q time (if output) *\/$/;" m struct:s_pb_graph_pin turn_on_off ./base/graphics.c /^static void turn_on_off (int pressed) {$/;" f file: twisted ./base/vpr_types.h /^ boolean twisted;$/;" m struct:s_seg_details -txt ../../libarchfpga/include/ezxml.h /^ char *txt; \/* tag character content, empty string if none *\/$/;" m struct:ezxml -type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_buffer_type type;$/;" m struct:s_spice_model_buffer typeref:enum:s_spice_model_buffer::e_spice_model_buffer_type -type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_gate_type type;$/;" m struct:s_spice_model_gate typeref:enum:s_spice_model_gate::e_spice_model_gate_type -type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_pass_gate_logic_type type;$/;" m struct:s_spice_model_pass_gate_logic typeref:enum:s_spice_model_pass_gate_logic::e_spice_model_pass_gate_logic_type -type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_port_type type;$/;" m struct:s_spice_model_port typeref:enum:s_spice_model_port::e_spice_model_port_type -type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_type type;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_type -type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_tech_lib_type type;$/;" m struct:s_spice_tech_lib typeref:enum:s_spice_tech_lib::e_spice_tech_lib_type -type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_trans_type type;$/;" m struct:s_spice_transistor_type typeref:enum:s_spice_transistor_type::e_spice_trans_type -type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_inf_orgz typeref:enum:s_sram_inf_orgz::e_sram_orgz -type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_orgz_info typeref:enum:s_sram_orgz_info::e_sram_orgz -type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_wire_model_type type;$/;" m struct:s_spice_model_wire_param typeref:enum:s_spice_model_wire_param::e_wire_model_type -type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum spice_model_delay_type type;$/;" m struct:s_spice_model_delay_info typeref:enum:s_spice_model_delay_info::spice_model_delay_type -type ../../libarchfpga/include/physical_types.h /^ enum PORTS type;$/;" m struct:s_port typeref:enum:s_port::PORTS -type ../../libarchfpga/include/physical_types.h /^ enum e_interconnect type;$/;" m struct:s_interconnect typeref:enum:s_interconnect::e_interconnect -type ../../libarchfpga/include/physical_types.h /^ enum e_pb_graph_pin_type type; \/* Is a sequential logic element (TRUE), inpad\/outpad (TRUE), or neither (FALSE) *\/$/;" m struct:s_pb_graph_pin typeref:enum:s_pb_graph_pin::e_pb_graph_pin_type -type ../../libarchfpga/include/physical_types.h /^ enum e_pin_to_pin_annotation_type type;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_type -type ../../libarchfpga/include/physical_types.h /^ enum e_pin_type type;$/;" m struct:s_class typeref:enum:s_class::e_pin_type -type ../../libarchfpga/include/physical_types.h /^ enum e_stat type;$/;" m struct:s_chan typeref:enum:s_chan::e_stat -type ../../libarchfpga/include/physical_types.h /^ char* type;$/;" m struct:s_switch_inf -type ../../libarchfpga/include/physical_types.h /^ enum e_swseg_pattern_type type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_swseg_pattern_type type ./base/graphics.c /^ t_button_type type;$/;" m struct:__anon4 file: type ./base/vpr_types.h /^ e_tnode_type type; \/* see the above enum *\/$/;" m struct:s_tnode type ./base/vpr_types.h /^ enum e_pack_pattern_molecule_type type; \/* what kind of molecule is this? *\/$/;" m struct:s_pack_molecule typeref:enum:s_pack_molecule::e_pack_pattern_molecule_type @@ -6031,11 +4380,9 @@ type ./base/vpr_types.h /^ t_rr_type type;$/;" m struct:s_cb type ./util/token.h /^ enum e_token_type type;$/;" m struct:s_token typeref:enum:s_token::e_token_type type_descriptors ./base/globals.c /^struct s_type_descriptor *type_descriptors = NULL;$/;" v typeref:struct:s_type_descriptor type_descriptors_backup ./place/timing_place_lookup.c /^static t_type_descriptor *type_descriptors_backup;$/;" v file: -u ../../libarchfpga/include/ezxml.h /^ char *u; \/* UTF-8 conversion of string if original was UTF-16 *\/$/;" m struct:ezxml_root u ./route/route_common.h /^ } u;$/;" m struct:s_heap typeref:union:s_heap::__anon14 u ./route/route_tree_timing.h /^ } u;$/;" m struct:s_rt_node typeref:union:s_rt_node::__anon16 u ./timing/net_delay_types.h /^ } u;$/;" m struct:s_rc_node typeref:union:s_rc_node::__anon18 -unbuf_switch ../../libarchfpga/include/physical_types.h /^ short unbuf_switch;$/;" m struct:s_swseg_pattern_inf unbuf_switched ./base/vpr_types.h /^ int unbuf_switched; \/* Xifan TANG: Switch Segment Pattern Support*\/$/;" m struct:s_rr_node unclustered_list_head ./pack/cluster.c /^static struct s_molecule_link *unclustered_list_head;$/;" v typeref:struct:s_molecule_link file: unclustered_list_head_size ./pack/cluster.c /^int unclustered_list_head_size;$/;" v @@ -6056,8 +4403,11 @@ update_mem_bank_info_num_mem_bit ./fpga_x2p/base/fpga_x2p_utils.c /^void update_ update_mem_bank_info_reserved_blwl ./fpga_x2p/base/fpga_x2p_utils.c /^void update_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info,$/;" f update_message ./base/graphics.c /^update_message (const char *msg) $/;" f update_message ./base/graphics.c /^void update_message (const char *msg) { }$/;" f +update_mirror_connection_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void update_mirror_connection_blocks() {$/;" f +update_mirror_switch_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void update_mirror_switch_blocks() {$/;" f update_net_delays_from_route_tree ./route/route_tree_timing.c /^void update_net_delays_from_route_tree(float *net_delay,$/;" f update_normalized_costs ./timing/path_delay.c /^static void update_normalized_costs(float criticality_denom, long max_critical_input_paths,$/;" f file: +update_one_connection_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void update_one_connection_block_mirror(t_cb* cur_cb) {$/;" f update_one_grid_pack_net_num ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_one_grid_pack_net_num(int x, int y) {$/;" f update_one_grid_pb_pins_parasitic_nets ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_one_grid_pb_pins_parasitic_nets(int ix, int iy) {$/;" f update_one_io_grid_pack_net_num ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_one_io_grid_pack_net_num(int x, int y) {$/;" f @@ -6065,6 +4415,7 @@ update_one_spice_model_grid_index_high ./fpga_x2p/base/fpga_x2p_utils.c /^void u update_one_spice_model_grid_index_low ./fpga_x2p/base/fpga_x2p_utils.c /^void update_one_spice_model_grid_index_low(int x, int y, $/;" f update_one_spice_model_routing_index_high ./fpga_x2p/base/fpga_x2p_utils.c /^void update_one_spice_model_routing_index_high(int x, int y, t_rr_type chan_type,$/;" f update_one_spice_model_routing_index_low ./fpga_x2p/base/fpga_x2p_utils.c /^void update_one_spice_model_routing_index_low(int x, int y, t_rr_type chan_type,$/;" f +update_one_switch_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void update_one_switch_block_mirror(t_sb* cur_sb) {$/;" f update_one_unused_grid_output_pins_parasitic_nets ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_one_unused_grid_output_pins_parasitic_nets(int ix, int iy) {$/;" f update_one_used_grid_pb_pins_parasitic_nets ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_one_used_grid_pb_pins_parasitic_nets(t_phy_pb* cur_pb,$/;" f update_pb_graph_node_temp_net_num_to_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void update_pb_graph_node_temp_net_num_to_pb(t_pb_graph_node* cur_pb_graph_node,$/;" f @@ -6098,31 +4449,23 @@ update_unbuffered_ancestors_C_downstream ./route/route_tree_timing.c /^update_un update_win ./base/graphics.c /^update_win (int x[2], int y[2], void (*drawscreen)(void)) $/;" f file: update_wire_L_counter_in_llist ./fpga_x2p/verilog/verilog_report_timing.c /^void update_wire_L_counter_in_llist(t_llist* rr_path_cnt, $/;" f usage ./base/vpr_types.h /^ int usage;$/;" m struct:s_grid_tile -uschar ../../pcre/SRC/internal.h /^typedef unsigned char uschar;$/;" t use_default_timing_constraints ./timing/read_sdc.c /^static void use_default_timing_constraints(void) {$/;" f file: -used ../../libarchfpga/include/logic_types.h /^ int used;$/;" m struct:s_model used_input_pins ./base/vpr_types.h /^ int used_input_pins; \/* Number of used input pins *\/$/;" m struct:s_logical_block user_defined_template_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* user_defined_template_verilog_file_name = "user_defined_templates.v";$/;" v user_models ./base/vpr_types.h /^ t_model * user_models; \/* blif models defined by the user *\/$/;" m struct:s_vpr_setup -utf8 ../../pcre/SRC/internal.h /^ BOOL utf8; \/* UTF8 flag *\/$/;" m struct:match_data -utf8_table1 ../../pcre/SRC/pcre.c /^static int utf8_table1[] = { 0x7f, 0x7ff, 0xffff, 0x1fffff, 0x3ffffff, 0x7fffffff};$/;" v file: -utf8_table2 ../../pcre/SRC/pcre.c /^static int utf8_table2[] = { 0, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc};$/;" v file: -utf8_table3 ../../pcre/SRC/pcre.c /^static int utf8_table3[] = { 0xff, 0x1f, 0x0f, 0x07, 0x03, 0x01};$/;" v file: -utf8_table4 ../../pcre/SRC/pcre.c /^static uschar utf8_table4[] = {$/;" v file: v_ds ./power/power.h /^ float v_ds;$/;" m struct:s_power_nmos_leakage_pair v_in ./power/power.h /^ float v_in;$/;" m struct:s_power_mux_volt_pair v_out_max ./power/power.h /^ float v_out_max;$/;" m struct:s_power_mux_volt_pair v_out_min ./power/power.h /^ float v_out_min;$/;" m struct:s_power_mux_volt_pair -val ../../libarchfpga/fpga_spice_include/spice_types.h /^ int val; \/* binary value to be writtent: either 0 or 1 *\/$/;" m struct:s_conf_bit val ./fpga_x2p/shell/read_opt_types.h /^ char* val; \/*The value*\/$/;" m struct:s_opt_info val_type ./fpga_x2p/shell/read_opt_types.h /^ enum opt_val_type val_type; $/;" m struct:s_opt_info typeref:enum:s_opt_info::opt_val_type -valid ../../libarchfpga/include/cad_types.h /^ boolean valid;$/;" m struct:s_cluster_placement_primitive valid ./base/vpr_types.h /^ boolean valid; \/* Whether or not this molecule is still valid *\/$/;" m struct:s_pack_molecule valid_primitives ./base/vpr_types.h /^ t_cluster_placement_primitive **valid_primitives; \/* [0..num_pb_types-1] ptrs to linked list of valid primitives, for convenience, each linked list head is empty *\/$/;" m struct:s_cluster_placement_stats -value ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* value; $/;" m struct:s_spice_model_delay_info -value ../../libarchfpga/include/physical_types.h /^ char ** value; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation +validate_mirror_connection_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean validate_mirror_connection_blocks() {$/;" f +validate_mirror_switch_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean validate_mirror_switch_blocks() {$/;" f +validate_one_connection_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean validate_one_connection_block_mirror(t_cb* cur_cb) {$/;" f +validate_one_switch_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean validate_one_switch_block_mirror(t_sb* cur_sb) {$/;" f value ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node;$/;" m struct:s_buffer_plan_node file: -variation_on ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean variation_on;$/;" m struct:s_spice_mc_variation_params verify_binary_search ./base/vpr_types.h /^ boolean verify_binary_search;$/;" m struct:s_router_opts verilog_compact_generate_fake_xy_for_io_border_side ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void verilog_compact_generate_fake_xy_for_io_border_side(int border_side, $/;" f verilog_config_peripheral_prefix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_config_peripheral_prefix = "config_peripheral";$/;" v @@ -6149,7 +4492,7 @@ verilog_generate_sdc_break_loop_mux ./fpga_x2p/verilog/verilog_sdc.c /^void veri verilog_generate_sdc_break_loop_sb ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_break_loop_sb(FILE* fp,$/;" f verilog_generate_sdc_break_loop_sram ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_break_loop_sram(FILE* fp, $/;" f verilog_generate_sdc_break_loops ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_break_loops(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -verilog_generate_sdc_clock_period ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_clock_period(t_sdc_opts sdc_opts) {$/;" f +verilog_generate_sdc_clock_period ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_clock_period(t_sdc_opts sdc_opts,$/;" f verilog_generate_sdc_constrain_cbs ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_constrain_cbs(t_sram_orgz_info* cur_sram_orgz_info,$/;" f verilog_generate_sdc_constrain_one_cb ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_constrain_one_cb(FILE* fp,$/;" f verilog_generate_sdc_constrain_one_cb_path ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_constrain_one_cb_path(FILE* fp,$/;" f @@ -6182,16 +4525,12 @@ verilog_include_simulation_defines_file ./fpga_x2p/verilog/verilog_utils.c /^voi verilog_mem_posfix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_mem_posfix = "_mem";$/;" v verilog_mux_basis_posfix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_mux_basis_posfix = "_basis";$/;" v verilog_mux_special_basis_posfix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_mux_special_basis_posfix = "_special_basis";$/;" v -verilog_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* verilog_netlist; \/* Verilog netlist provided by user *\/$/;" m struct:s_spice_model verilog_netlist_file_postfix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_netlist_file_postfix = ".v";$/;" v -verilog_reserved ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean verilog_reserved;$/;" m struct:s_reserved_syntax_char verilog_signal_init_preproc_flag ./fpga_x2p/verilog/verilog_global.c /^char* verilog_signal_init_preproc_flag = "ENABLE_SIGNAL_INITIALIZATION"; \/\/ the flag to enable signal initialization during compilation$/;" v verilog_sim_timescale ./fpga_x2p/verilog/verilog_global.c /^float verilog_sim_timescale = 1e-9; \/\/ Verilog Simulation time scale (minimum time unit) : 1ns$/;" v -verilog_sram_inf_orgz ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* verilog_sram_inf_orgz;$/;" m struct:s_sram_inf verilog_timing_preproc_flag ./fpga_x2p/verilog/verilog_global.c /^char* verilog_timing_preproc_flag = "ENABLE_TIMING"; \/\/ the flag to enable timing definition during compilation$/;" v verilog_top_postfix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_top_postfix = "_top.v";$/;" v verilog_writer ./base/verilog_writer.c /^void verilog_writer(void)$/;" f -version ../../pcre/SRC/pcre.h /^ int version; \/* Identifies version of block *\/$/;" m struct:pcre_callout_block view_mux_size_distribution ./route/rr_graph.c /^view_mux_size_distribution(t_ivec *** L_rr_node_indices,$/;" f file: visited ./power/power.h /^ boolean visited; \/* When traversing netlist, need to track whether the node has been processed *\/$/;" m struct:s_rr_node_power vpack_net ./base/globals.c /^struct s_net *vpack_net = NULL;$/;" v typeref:struct:s_net @@ -6202,7 +4541,6 @@ vpr_alloc_and_load_output_file_names ./base/vpr_api.c /^void vpr_alloc_and_load_ vpr_check_arch ./base/vpr_api.c /^void vpr_check_arch(INP t_arch Arch, INP boolean TimingEnabled) {$/;" f vpr_check_options ./base/vpr_api.c /^void vpr_check_options(INP t_options Options, INP boolean TimingEnabled) {$/;" f vpr_check_setup ./base/vpr_api.c /^void vpr_check_setup(INP enum e_operation Operation,$/;" f -vpr_crit_path_delay ../../libarchfpga/fpga_spice_include/spice_types.h /^ float vpr_crit_path_delay; \/* Reference operation clock frequency *\/$/;" m struct:s_spice_stimulate_params vpr_fpga_bitstream_generator ./fpga_x2p/bitstream/fpga_bitstream.c /^void vpr_fpga_bitstream_generator(t_vpr_setup vpr_setup,$/;" f vpr_fpga_generate_bitstream ./fpga_x2p/bitstream/fpga_bitstream.c /^void vpr_fpga_generate_bitstream(t_vpr_setup vpr_setup,$/;" f vpr_fpga_spice ./fpga_x2p/spice/spice_api.c /^void vpr_fpga_spice(t_vpr_setup vpr_setup,$/;" f @@ -6221,7 +4559,6 @@ vpr_place_and_route_opts ./fpga_x2p/shell/cmd_vpr_place_and_route.h /^t_opt_info vpr_power_estimation ./base/vpr_api.c /^void vpr_power_estimation(t_vpr_setup vpr_setup, t_arch Arch) {$/;" f vpr_print_title ./base/vpr_api.c /^void vpr_print_title(void) {$/;" f vpr_print_usage ./base/vpr_api.c /^void vpr_print_usage(void) {$/;" f -vpr_printf ../../libarchfpga/util.c /^messagelogger vpr_printf = PrintHandlerMessage;$/;" v vpr_read_and_process_blif ./base/vpr_api.c /^void vpr_read_and_process_blif(INP char *blif_file,$/;" f vpr_read_options ./base/vpr_api.c /^void vpr_read_options(INP int argc, INP char **argv, OUTP t_options * options) {$/;" f vpr_resync_post_route_netlist_to_TI_CLAY_v1_architecture ./base/vpr_api.c /^t_trace* vpr_resync_post_route_netlist_to_TI_CLAY_v1_architecture($/;" f @@ -6236,33 +4573,20 @@ vpr_to_phy_track ./route/rr_graph2.c /^static int vpr_to_phy_track(INP int itrac vpr_versapower_opts ./fpga_x2p/shell/cmd_vpr_power.h /^t_opt_info vpr_versapower_opts[] = {$/;" v watch_edges ./route/rr_graph.c /^void watch_edges(int inode, t_linked_edge * edge_list_head) {$/;" f which_button ./base/graphics.c /^static int which_button (Window win) $/;" f file: -width ../../libarchfpga/include/physical_types.h /^ float width;$/;" m struct:s_chan width ./base/graphics.c /^ int width; $/;" m struct:__anon4 file: win ./base/graphics.c /^ Window win; $/;" m struct:__anon4 file: win32_colors ./base/graphics.c /^static const COLORREF win32_colors[NUM_COLOR] = { RGB(255, 255, 255),$/;" v file: win32_drain_message_queue ./base/graphics.c /^void win32_drain_message_queue () {$/;" f win32_line_styles ./base/graphics.c /^static const int win32_line_styles[2] = { PS_SOLID, PS_DASH };$/;" v file: windowAdjustFlag ./base/graphics.c /^static int windowAdjustFlag = 0, adjustButton = -1;$/;" v file: -wire ../../libarchfpga/include/physical_types.h /^ } wire;$/;" m struct:s_port_power typeref:union:s_port_power::__anon22 -wire_buffer_inf ../../libarchfpga/include/arch_types_mrfpga.h /^ t_buffer_inf wire_buffer_inf;$/;" m struct:s_arch_mrfpga wire_buffer_inf ./mrfpga/mrfpga_globals.c /^t_buffer_inf wire_buffer_inf;$/;" v -wire_param ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_wire_param* wire_param;$/;" m struct:s_spice_model -wire_switch ../../libarchfpga/include/physical_types.h /^ short wire_switch;$/;" m struct:s_segment_inf wire_switch ./base/vpr_types.h /^ short wire_switch;$/;" m struct:s_seg_details wire_to_ipin_switch ./base/vpr_types.h /^ short wire_to_ipin_switch;$/;" m struct:s_det_routing_arch -wire_type ../../libarchfpga/include/physical_types.h /^ e_power_wire_type wire_type;$/;" m struct:s_port_power -wire_variation ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params wire_variation;$/;" m struct:s_spice_mc_params wirelength ./base/place_and_route.h /^ int wirelength; \/* corresponding wirelength of successful routing at wneed *\/$/;" m struct:s_fmap_cell wires_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* wires_spice_file_name = "wires.sp";$/;" v wires_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* wires_verilog_file_name = "wires.v";$/;" v with_val ./fpga_x2p/shell/read_opt_types.h /^ enum opt_with_val with_val;$/;" m struct:s_opt_info typeref:enum:s_opt_info::opt_with_val -wl ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_conf_bit* wl;$/;" m struct:s_conf_bit_info wneed ./base/place_and_route.h /^ int wneed; \/* need wneed to route *\/$/;" m struct:s_fmap_cell -wprog_reset_nmos ../../libarchfpga/fpga_spice_include/spice_types.h /^ float wprog_reset_nmos;$/;" m struct:s_spice_model_rram -wprog_reset_pmos ../../libarchfpga/fpga_spice_include/spice_types.h /^ float wprog_reset_pmos;$/;" m struct:s_spice_model_rram -wprog_set_nmos ../../libarchfpga/fpga_spice_include/spice_types.h /^ float wprog_set_nmos;$/;" m struct:s_spice_model_rram -wprog_set_pmos ../../libarchfpga/fpga_spice_include/spice_types.h /^ float wprog_set_pmos;$/;" m struct:s_spice_model_rram -write ../../libarchfpga/ezxml.c 60;" d file: write_formality_script ./fpga_x2p/verilog/verilog_formality_autodeck.c /^void write_formality_script (t_syn_verilog_opts fpga_verilog_opts,$/;" f write_include_netlists ./fpga_x2p/verilog/verilog_include_netlists.c /^void write_include_netlists (char* src_dir_formatted,$/;" f x ./base/easygl_constants.h /^ float x; $/;" m struct:__anon1 @@ -6270,7 +4594,6 @@ x ./base/vpr_types.h /^ int x;$/;" m struct:s_block x ./base/vpr_types.h /^ int x;$/;" m struct:s_cb x ./base/vpr_types.h /^ int x;$/;" m struct:s_sb x ./place/place.c /^ int x;$/;" m struct:s_legal_pos file: -x_offset ../../libarchfpga/include/physical_types.h /^ int x_offset;$/;" m struct:s_direct_inf x_offset ./base/vpr_types.h /^ int x_offset;$/;" m struct:s_clb_to_clb_directs x_offset ./place/place_macro.h /^ int x_offset;$/;" m struct:s_pl_macro_member x_rr_node_left ./base/draw.c /^static float *x_rr_node_left = NULL;$/;" v file: @@ -6284,12 +4607,10 @@ xleft ./base/graphics.h /^ float xleft, xright, ytop, ybot;$/;" m struct:__anon6 xlow ./base/vpr_types.h /^ short xlow;$/;" m struct:s_rr_node xmax ./base/vpr_types.h /^ int xmax;$/;" m struct:s_bb xmin ./base/vpr_types.h /^ int xmin;$/;" m struct:s_bb -xml ../../libarchfpga/include/ezxml.h /^ struct ezxml xml; \/* is a super-struct built on top of ezxml struct *\/$/;" m struct:ezxml_root typeref:struct:ezxml_root::ezxml xmult ./base/graphics.c /^static float xmult, ymult; \/* Transformation factors *\/$/;" v file: xmult ./base/graphics.h /^ float xmult, ymult;$/;" m struct:__anon6 xnew ./place/place.c /^ int xnew;$/;" m struct:s_pl_moved_block file: xold ./place/place.c /^ int xold;$/;" m struct:s_pl_moved_block file: -xpeak ../../libarchfpga/include/physical_types.h /^ float xpeak;$/;" m struct:s_chan xright ./base/graphics.c /^static float xleft, xright, ytop, ybot; \/* world coordinates *\/$/;" v file: xright ./base/graphics.h /^ float xleft, xright, ytop, ybot;$/;" m struct:__anon6 y ./base/easygl_constants.h /^ float y;$/;" m struct:__anon1 @@ -6297,7 +4618,6 @@ y ./base/vpr_types.h /^ int y;$/;" m struct:s_block y ./base/vpr_types.h /^ int y;$/;" m struct:s_cb y ./base/vpr_types.h /^ int y;$/;" m struct:s_sb y ./place/place.c /^ int y;$/;" m struct:s_legal_pos file: -y_offset ../../libarchfpga/include/physical_types.h /^ int y_offset;$/;" m struct:s_direct_inf y_offset ./base/vpr_types.h /^ int y_offset;$/;" m struct:s_clb_to_clb_directs y_offset ./place/place_macro.h /^ int y_offset; $/;" m struct:s_pl_macro_member y_rr_node_bottom ./base/draw.c /^static float *y_rr_node_bottom = NULL;$/;" v file: @@ -6320,7 +4640,6 @@ ytop ./base/graphics.h /^ float xleft, xright, ytop, ybot;$/;" m struct:__anon6 z ./base/vpr_types.h /^ int z; \/* For IPIN, source, and sink nodes, helps identify which location this rr_node belongs to *\/$/;" m struct:s_rr_node z ./base/vpr_types.h /^ int z;$/;" m struct:s_block z ./place/place.c /^ int z;$/;" m struct:s_legal_pos file: -z_offset ../../libarchfpga/include/physical_types.h /^ int z_offset;$/;" m struct:s_direct_inf z_offset ./base/vpr_types.h /^ int z_offset;$/;" m struct:s_clb_to_clb_directs z_offset ./place/place_macro.h /^ int z_offset;$/;" m struct:s_pl_macro_member zero_one_spice_model_grid_index_low_high ./fpga_x2p/base/fpga_x2p_utils.c /^void zero_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) {$/;" f diff --git a/vpr7_x2p/vpr/go_fpga_verilog.sh b/vpr7_x2p/vpr/go_fpga_verilog.sh index cabfbd6d8..498e1e81a 100755 --- a/vpr7_x2p/vpr/go_fpga_verilog.sh +++ b/vpr7_x2p/vpr/go_fpga_verilog.sh @@ -36,7 +36,7 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname # Run VPR #valgrind -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis #--fpga_verilog_print_report_timing_tcl +echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl " From 5c646f5de7901dabe2dc45e59346ec03c8cc947c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 9 May 2019 21:40:06 -0600 Subject: [PATCH 3/4] fix bugs in routing identification --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c index a58207993..17d2986af 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c @@ -150,6 +150,11 @@ boolean is_two_sb_rr_nodes_mirror(t_sb* src_sb, t_sb* des_sb, int side, != des_rr_node->drive_rr_nodes[inode]->type) { return FALSE; } + /* switch type should be the same */ + if ( src_rr_node->drive_switches[inode] + != des_rr_node->drive_switches[inode]) { + return FALSE; + } int src_node_id, des_node_id; int src_node_side, des_node_side; get_rr_node_side_and_index_in_sb_info(src_rr_node->drive_rr_nodes[inode], *src_sb, OUT_PORT, &src_node_side, &src_node_id); @@ -185,6 +190,11 @@ boolean is_two_cb_rr_nodes_mirror(t_cb* src_cb, t_cb* des_cb, != des_rr_node->drive_rr_nodes[inode]->type) { return FALSE; } + /* switch type should be the same */ + if ( src_rr_node->drive_switches[inode] + != des_rr_node->drive_switches[inode]) { + return FALSE; + } int src_node_id, des_node_id; int src_node_side, des_node_side; get_rr_node_side_and_index_in_cb_info(src_rr_node->drive_rr_nodes[inode], *src_cb, OUT_PORT, &src_node_side, &src_node_id); From be4643b8a6e8f7f2895aedf9b3cb874abbe23ff5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 10 May 2019 10:21:06 -0600 Subject: [PATCH 4/4] updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated --- .../fpga_x2p/base/fpga_x2p_pbtypes_utils.h | 4 - .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 3 +- .../verilog/verilog_compact_netlist.c | 319 +++++++++++++++++- .../verilog/verilog_compact_netlist.h | 1 + .../SRC/fpga_x2p/verilog/verilog_routing.c | 70 ++-- .../SRC/fpga_x2p/verilog/verilog_routing.h | 9 +- 6 files changed, 377 insertions(+), 29 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index 67f6ac6ef..05bcd003b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -113,8 +113,6 @@ t_pb* get_child_pb_for_phy_pb_graph_node(t_pb* cur_pb, int ipb, int jpb); t_phy_pb* get_phy_child_pb_for_phy_pb_graph_node(t_phy_pb* cur_phy_pb, int ipb, int jpb); -enum e_interconnect find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin) ; - t_spice_model* find_pb_graph_pin_in_edges_interc_model(t_pb_graph_pin pb_graph_pin) ; void find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin, @@ -210,8 +208,6 @@ t_phy_pb* rec_get_phy_pb_by_name(t_phy_pb* cur_phy_pb, int get_pb_graph_node_wired_lut_logical_block_index(t_pb_graph_node* cur_pb_graph_node, t_rr_node* op_pb_rr_graph); -void rec_reset_pb_graph_node_rr_node_index_physical_pb(t_pb_graph_node* cur_pb_graph_node); - void sync_wired_lut_to_one_phy_pb(t_pb_graph_node* cur_pb_graph_node, t_phy_pb* cur_phy_pb, t_rr_node* op_pb_rr_graph); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index fd6641a1e..1d970690b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -253,7 +253,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, /* Dump routing resources: switch blocks, connection blocks and channel tracks */ dump_verilog_routing_resources(sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, &vpr_setup.RoutingArch, num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data, - vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); /* Dump logic blocks * Branches to go: @@ -274,6 +274,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, num_rr_nodes, rr_node, rr_node_indices, num_clocks, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, + vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy, *(Arch.spice)); /* Dump SDC constraints */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 5430be339..00aaa61f2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -35,6 +35,7 @@ #include "verilog_utils.h" #include "verilog_primitives.h" #include "verilog_pbtypes.h" +#include "verilog_routing.h" #include "verilog_top_netlist_utils.h" /* ONLY for compact Verilog netlists: @@ -739,6 +740,311 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, return; } +/* Call the defined switch box sub-circuit + * TODO: This function is also copied from + * spice_routing.c : dump_verilog_routing_switch_box_subckt + */ +static +void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, + FILE* fp, + t_sb cur_sb_info) { + int ix, iy, side, itrack, x, y, inode; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); + assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); + + x = cur_sb_info.x; + y = cur_sb_info.y; + + /* Comment lines */ + fprintf(fp, "//----- BEGIN call module Switch blocks [%d][%d] -----\n", + cur_sb_info.x, cur_sb_info.y); + /* Print module*/ + + /* If we have an mirror SB, we should the module name of the mirror !!! */ + if (NULL != cur_sb_info.mirror) { + fprintf(fp, "%s ", gen_verilog_one_sb_module_name(cur_sb_info.mirror)); + } else { + fprintf(fp, "%s ", gen_verilog_one_sb_module_name(&cur_sb_info)); + } + + fprintf(fp, "%s ", gen_verilog_one_sb_instance_name(&cur_sb_info)); + fprintf(fp, "("); + + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + + for (side = 0; side < cur_sb_info.num_sides; side++) { + determine_sb_port_coordinator(cur_sb_info, side, &ix, &iy); + + fprintf(fp, "//----- %s side channel ports-----\n", convert_side_index_to_string(side)); + for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { + fprintf(fp, "%s,\n", + gen_verilog_routing_channel_one_pin_name(cur_sb_info.chan_rr_node[side][itrack], + ix, iy, itrack, + cur_sb_info.chan_rr_node_direction[side][itrack])); + } + fprintf(fp, "//----- %s side inputs: CLB output pins -----\n", convert_side_index_to_string(side)); + /* Dump OPINs of adjacent CLBs */ + for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[side]; inode++) { + dump_verilog_grid_side_pin_with_given_index(fp, IPIN, + cur_sb_info.opin_rr_node[side][inode]->ptc_num, + cur_sb_info.opin_rr_node_grid_side[side][inode], + cur_sb_info.opin_rr_node[side][inode]->xlow, + cur_sb_info.opin_rr_node[side][inode]->ylow, + FALSE); /* Do not specify the direction of port */ + fprintf(fp, ", "); + } + fprintf(fp, "\n"); + } + + /* Configuration ports */ + /* output of each configuration bit */ + /* Reserved sram ports */ + if (0 < (cur_sb_info.num_reserved_conf_bits)) { + dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, + 0, cur_sb_info.num_reserved_conf_bits - 1, + VERILOG_PORT_CONKT); + fprintf(fp, ",\n"); + } + /* Normal sram ports */ + if (0 < (cur_sb_info.conf_bits_msb - cur_sb_info.conf_bits_lsb)) { + dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, + cur_sb_info.conf_bits_lsb, + cur_sb_info.conf_bits_msb - 1, + VERILOG_PORT_CONKT); + } + + /* Dump ports only visible during formal verification*/ + if (0 < (cur_sb_info.conf_bits_msb - 1 - cur_sb_info.conf_bits_lsb)) { + fprintf(fp, "\n"); + fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); + fprintf(fp, ",\n"); + dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, + cur_sb_info.conf_bits_lsb, + cur_sb_info.conf_bits_msb - 1, + VERILOG_PORT_CONKT); + fprintf(fp, "\n"); + fprintf(fp, "`endif\n"); + } + fprintf(fp, ");\n"); + + /* Comment lines */ + fprintf(fp, "//----- END call module Switch blocks [%d][%d] -----\n\n", x, y); + + /* Free */ + + return; +} + + +void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, + FILE* fp) { + int ix, iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, sb_info[ix][iy]); + } + } + + return; +} + +/* Call the defined sub-circuit of connection box + * TODO: actually most of this function is copied from + * spice_routing.c : dump_verilog_conneciton_box_interc + * Should be more clever to use the original function + */ +static +void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info, + FILE* fp, + t_cb cur_cb_info) { + int itrack, inode, side, x, y; + int side_cnt = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); + assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); + + x = cur_cb_info.x; + y = cur_cb_info.y; + + /* Comment lines */ + fprintf(fp, + "//----- BEGIN Call Connection Box for %s direction [%d][%d] module -----\n", + convert_chan_type_to_string(cur_cb_info.type), + x, y); + + /* Print module */ + /* If we have an mirror SB, we should the module name of the mirror !!! */ + if (NULL != cur_cb_info.mirror) { + fprintf(fp, "%s ", gen_verilog_one_cb_module_name(cur_cb_info.mirror)); + } else { + fprintf(fp, "%s ", gen_verilog_one_cb_module_name(&cur_cb_info)); + } + + fprintf(fp, "%s ", gen_verilog_one_cb_instance_name(&cur_cb_info)); + + fprintf(fp, "("); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + + /* Print the ports of channels*/ + /* connect to the mid point of a track*/ + side_cnt = 0; + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero channel width */ + if (0 == cur_cb_info.chan_width[side]) { + continue; + } + assert (0 < cur_cb_info.chan_width[side]); + side_cnt++; + fprintf(fp, "//----- %s side inputs: channel track middle outputs -----\n", convert_side_index_to_string(side)); + for (itrack = 0; itrack < cur_cb_info.chan_width[side]; itrack++) { + fprintf(fp, "%s, ", + gen_verilog_routing_channel_one_midout_name(&cur_cb_info, itrack)); + fprintf(fp, "\n"); + } + } + /*check side_cnt */ + assert(1 == side_cnt); + + side_cnt = 0; + /* Print the ports of grids*/ + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info.ipin_rr_node[side]); + fprintf(fp, "//----- %s side outputs: CLB input pins -----\n", convert_side_index_to_string(side)); + for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { + /* Print each INPUT Pins of a grid */ + dump_verilog_grid_side_pin_with_given_index(fp, OPIN, + cur_cb_info.ipin_rr_node[side][inode]->ptc_num, + cur_cb_info.ipin_rr_node_grid_side[side][inode], + cur_cb_info.ipin_rr_node[side][inode]->xlow, + cur_cb_info.ipin_rr_node[side][inode]->ylow, + FALSE); /* Do not specify direction of port */ + fprintf(fp, ", \n"); + } + } + /* Make sure only 2 sides of IPINs are printed */ + assert((1 == side_cnt)||(2 == side_cnt)); + + /* Configuration ports */ + /* Reserved sram ports */ + if (0 < (cur_cb_info.num_reserved_conf_bits)) { + dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, + 0, cur_cb_info.num_reserved_conf_bits - 1, + VERILOG_PORT_CONKT); + fprintf(fp, ",\n"); + } + /* Normal sram ports */ + if (0 < (cur_cb_info.conf_bits_msb - cur_cb_info.conf_bits_lsb)) { + dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, + cur_cb_info.conf_bits_lsb, cur_cb_info.conf_bits_msb - 1, + VERILOG_PORT_CONKT); + } + /* Dump ports only visible during formal verification*/ + if (0 < (cur_cb_info.conf_bits_msb - 1 - cur_cb_info.conf_bits_lsb)) { + fprintf(fp, "\n"); + fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); + fprintf(fp, ",\n"); + dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, + cur_cb_info.conf_bits_lsb, + cur_cb_info.conf_bits_msb - 1, + VERILOG_PORT_CONKT); + fprintf(fp, "\n"); + fprintf(fp, "`endif\n"); + } + fprintf(fp, ");\n"); + + /* Comment lines */ + switch(cur_cb_info.type) { + case CHANX: + fprintf(fp, "//----- END call Connection Box-X direction [%d][%d] module -----\n\n", x, y); + break; + case CHANY: + fprintf(fp, "//----- END call Connection Box-Y direction [%d][%d] module -----\n\n", x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((1 == side_cnt)||(2 == side_cnt)); + + return; +} + +/* Call the sub-circuits for connection boxes */ +void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, + FILE* fp) { + int ix, iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + if ((TRUE == is_cb_exist(CHANX, ix, iy)) + &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { + dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cbx_info[ix][iy]); + } + } + } + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + if ((TRUE == is_cb_exist(CHANY, ix, iy)) + &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { + dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cby_info[ix][iy]); + } + } + } + + return; +} + + + /** Print Top-level SPICE netlist in a compact way * Instance unique submodules (I/O, CLB, Heterogeneous block) for the full grids */ @@ -754,6 +1060,7 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, t_ivec*** LL_rr_node_indices, int num_clock, t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy, t_spice verilog) { FILE* fp = NULL; char* formatted_dir_path = NULL; @@ -809,10 +1116,18 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); /* Quote Routing structures: Switch Boxes */ - dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp); + if (TRUE == compact_routing_hierarchy ) { + dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp); + } else { + dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp); + } /* Quote Routing structures: Connection Boxes */ - dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp); + if (TRUE == compact_routing_hierarchy ) { + dump_compact_verilog_defined_connection_boxes(cur_sram_orgz_info, fp); + } else { + dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp); + } /* Quote defined Logic blocks subckts (Grids) */ dump_compact_verilog_defined_grids(cur_sram_orgz_info, fp); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h index e74cd8432..34d63b540 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h @@ -24,5 +24,6 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, t_ivec*** LL_rr_node_indices, int num_clock, t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy, t_spice verilog); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index c51e8ebaa..e198d751a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -1107,7 +1107,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info t_sb* cur_sb_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, - t_syn_verilog_opts fpga_verilog_opts) { + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy) { int itrack, inode, side, ix, iy, x, y; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; FILE* fp = NULL; @@ -1131,6 +1132,20 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info cur_sb_info->num_reserved_conf_bits = num_reserved_conf_bits; cur_sb_info->conf_bits_lsb = cur_num_sram; cur_sb_info->conf_bits_msb = cur_num_sram + num_conf_bits; + + /* Handle mirror switch blocks: + * For mirrors, no need to output a file + * Just update the counter + */ + if ( (TRUE == compact_routing_hierarchy) + && (NULL != cur_sb_info->mirror) ) { + /* Again ensure the conf_bits should match !!! */ + /* Count the number of configuration bits of the mirror */ + int mirror_num_conf_bits = count_verilog_switch_box_conf_bits(cur_sram_orgz_info, cur_sb_info->mirror); + assert( mirror_num_conf_bits == num_conf_bits ); + /* return directly */ + return; + } /* Create file handler */ fp = verilog_create_one_subckt_file(subckt_dir, "Switch Block ", sb_verilog_file_name_prefix, cur_sb_info->x, cur_sb_info->y, &fname); @@ -1755,7 +1770,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ t_cb* cur_cb_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, - t_syn_verilog_opts fpga_verilog_opts) { + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy) { int itrack, inode, side, x, y; int side_cnt = 0; FILE* fp = NULL; @@ -1768,7 +1784,34 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ x= cur_cb_info->x; y= cur_cb_info->y; - + + /* Count the number of configuration bits */ + /* Count the number of configuration bits to be consumed by this Switch block */ + num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, cur_cb_info); + /* Count the number of reserved configuration bits to be consumed by this Switch block */ + num_reserved_conf_bits = count_verilog_connection_box_reserved_conf_bits(cur_sram_orgz_info, cur_cb_info); + /* Estimate the sram_verilog_model->cnt */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + esti_sram_cnt = cur_num_sram + num_conf_bits; + /* Record index */ + cur_cb_info->num_reserved_conf_bits = num_reserved_conf_bits; + cur_cb_info->conf_bits_lsb = cur_num_sram; + cur_cb_info->conf_bits_msb = cur_num_sram + num_conf_bits; + + /* Handle mirror switch blocks: + * For mirrors, no need to output a file + * Just update the counter + */ + if ( (TRUE == compact_routing_hierarchy) + && (NULL != cur_cb_info->mirror) ) { + /* Again ensure the conf_bits should match !!! */ + /* Count the number of configuration bits of the mirror */ + int mirror_num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, cur_cb_info->mirror); + assert( mirror_num_conf_bits == num_conf_bits ); + /* return directly */ + return; + } + /* Print the definition of subckt*/ /* Identify the type of connection box */ switch(cur_cb_info->type) { @@ -1850,18 +1893,6 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ /* Make sure only 2 sides of IPINs are printed */ assert((1 == side_cnt)||(2 == side_cnt)); - /* Count the number of configuration bits */ - /* Count the number of configuration bits to be consumed by this Switch block */ - num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, cur_cb_info); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - num_reserved_conf_bits = count_verilog_connection_box_reserved_conf_bits(cur_sram_orgz_info, cur_cb_info); - /* Estimate the sram_verilog_model->cnt */ - cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - esti_sram_cnt = cur_num_sram + num_conf_bits; - /* Record index */ - cur_cb_info->num_reserved_conf_bits = num_reserved_conf_bits; - cur_cb_info->conf_bits_lsb = cur_num_sram; - cur_cb_info->conf_bits_msb = cur_num_sram + num_conf_bits; /* Put down configuration port */ /* output of each configuration bit */ @@ -1956,7 +1987,8 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - t_syn_verilog_opts fpga_verilog_opts) { + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy) { int ix, iy; assert(UNI_DIRECTIONAL == routing_arch->directionality); @@ -2005,7 +2037,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(sb_info[ix][iy]), LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - fpga_verilog_opts); + fpga_verilog_opts, compact_routing_hierarchy); update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); } } @@ -2020,7 +2052,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cbx_info[ix][iy]), LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - fpga_verilog_opts); + fpga_verilog_opts, compact_routing_hierarchy); } update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); } @@ -2034,7 +2066,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cby_info[ix][iy]), LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - fpga_verilog_opts); + fpga_verilog_opts, compact_routing_hierarchy); } update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index 6f02a5f88..d72953085 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -67,7 +67,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info t_sb* cur_sb_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, - t_syn_verilog_opts fpga_verilog_opts); + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy); void dump_verilog_connection_box_short_interc(t_sram_orgz_info* cur_sram_orgz_info, @@ -111,7 +112,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ t_cb* cur_cb_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, - t_syn_verilog_opts fpga_verilog_opts); + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy); void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, @@ -122,5 +124,6 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - t_syn_verilog_opts fpga_verilog_opts); + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy);