update tileable rr_graph generator to improve routability and also enable assoicated testing
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@ -150,7 +150,7 @@
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout auto="1.0" tileable_routing="off"/>
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<layout auto="1.0" tileable_routing="on"/>
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<spice_settings>
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<parameters>
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<options sim_temp="25" post="off" captab="off" fast="on"/>
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@ -1087,15 +1087,17 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph,
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(*track2ipin_map)[chan_side_index][track_index].push_back(ipin_index);
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track_cnt += 2;
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/* Stop when we have enough Fc */
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/* Stop when we have enough Fc: this may lead to some tracks have zero drivers.
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* So I comment it. And we just make sure its track_cnt >= actual_Fc
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if (actual_Fc == track_cnt) {
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break;
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}
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*/
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}
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/* Ensure the number of tracks is similar to Fc */
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//printf("Fc_in=%d, track_cnt=%d\n", actual_Fc, track_cnt);
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assert (actual_Fc == track_cnt);
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assert (actual_Fc <= track_cnt);
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}
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return;
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@ -1180,15 +1182,17 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph,
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(*opin2track_map)[opin_side_index][opin_node_id].push_back(track_rr_node_index);
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/* update track counter */
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track_cnt++;
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/* Stop when we have enough Fc */
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/* Stop when we have enough Fc: this may lead to some tracks have zero drivers.
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* So I comment it. And we just make sure its track_cnt >= actual_Fc
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if (actual_Fc == track_cnt) {
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break;
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}
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*/
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}
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/* Ensure the number of tracks is similar to Fc */
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//printf("Fc_out=%lu, scaled_Fc_out=%d, track_cnt=%d, actual_track_cnt=%lu/%lu\n", Fc, actual_Fc, track_cnt, actual_track_list.size(), chan_width);
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assert (actual_Fc == track_cnt);
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assert (actual_Fc <= track_cnt);
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}
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return;
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@ -1330,6 +1334,10 @@ t_pin2track_map build_gsb_opin_to_track_map(t_rr_graph* rr_graph,
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/* update offset: aim to rotate starting tracks by 1*/
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offset[side_manager.to_size_t()] += 1;
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}
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/* Check:
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* 1. We want to ensure that each OPIN will drive at least one track
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* 2. We want to ensure that each track will be driven by at least 1 OPIN */
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}
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return opin2track_map;
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@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
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cd -
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# Run VPR
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./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis #--fpga_x2p_compact_routing_hierarchy
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./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy
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cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
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