riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB

This commit is contained in:
tangxifan 2019-06-06 23:45:21 -06:00
parent ce9fc5696c
commit 472aff5acb
16 changed files with 1031 additions and 464 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

290
vpr7_x2p/vpr/SRC/fpga_x2p/base/device_port.cpp Normal file
View File

@ -0,0 +1,290 @@
#include <algorithm>
#include <limits>
#include <cassert>
#include "device_port.h"
/* Basic Port member functions */
/* Constructor */
/* Default constructor */
BasicPort::BasicPort() {
/* By default we set an invalid port, which size is 0 */
lsb_ = 1;
msb_ = 0;
}
/* Copy constructor */
BasicPort::BasicPort(const BasicPort& basic_port) {
set(basic_port);
}
/* Accessors */
/* get the port width */
size_t BasicPort::get_width() const {
if (true == is_valid()) {
return msb_ - lsb_ + 1;
}
return 0; /* invalid port has a zero width */
}
/* get the LSB */
size_t BasicPort::get_msb() const {
return msb_;
}
/* get the LSB */
size_t BasicPort::get_lsb() const {
return lsb_;
}
/* Mutators */
/* copy */
void BasicPort::set(const BasicPort& basic_port) {
lsb_ = basic_port.get_lsb();
msb_ = basic_port.get_msb();
return;
}
/* set the port LSB and MSB */
void BasicPort::set_width(size_t width) {
if (0 == width) {
make_invalid();
return;
}
lsb_ = 0;
msb_ = width - 1;
return;
}
/* set the port LSB and MSB */
void BasicPort::set_width(size_t lsb, size_t msb) {
/* If lsb and msb is invalid, we make a default port */
if (lsb > msb) {
make_invalid();
return;
}
set_lsb(lsb);
set_msb(msb);
return;
}
void BasicPort::set_lsb(size_t lsb) {
lsb_ = lsb;
return;
}
void BasicPort::set_msb(size_t msb) {
msb_ = msb;
return;
}
/* Increase the port width */
void BasicPort::expand(size_t width) {
if (0 == width) {
return; /* ignore zero-width port */
}
/* If current port is invalid, we do not combine */
if (0 == get_width()) {
lsb_ = 0;
msb_ = width;
return;
}
/* Increase MSB */
msb_ += width;
return;
}
/* Swap lsb and msb */
void BasicPort::revert() {
std::swap(lsb_, msb_);
return;
}
/* rotate: increase both lsb and msb by an offset */
bool BasicPort::rotate(size_t offset) {
/* If current port is invalid or offset is 0,
* we do nothing
*/
if ((0 == offset) || (0 == get_width())) {
return true;
}
/* check if leads to overflow:
* if limits - msb is larger than offset
*/
if ( (std::numeric_limits<size_t>::max() - msb_ < offset) ) {
return false;
}
/* Increase LSB and MSB */
lsb_ += offset;
msb_ += offset;
return true;
}
/* rotate: decrease both lsb and msb by an offset */
bool BasicPort::counter_rotate(size_t offset) {
/* If current port is invalid or offset is 0,
* we do nothing
*/
if ((0 == offset) || (0 == get_width())) {
return true;
}
/* check if leads to overflow:
* if limits is larger than offset
*/
if ( (std::numeric_limits<size_t>::min() + lsb_ < offset) ) {
return false;
}
/* decrease LSB and MSB */
lsb_ -= offset;
msb_ -= offset;
return true;
}
/* Reset to initial port */
void BasicPort::reset() {
make_invalid();
return;
}
/* Combine two ports */
void BasicPort::combine(const BasicPort& port) {
/* LSB follows the current LSB */
/* MSB increases */
assert( 0 < port.get_width() ); /* Make sure port is valid */
/* If current port is invalid, we do not combine */
if (0 == get_width()) {
return;
}
/* Increase MSB */
msb_ += port.get_width();
return;
}
/* Internal functions */
/* Make a port to be invalid: msb < lsb */
void BasicPort::make_invalid() {
/* set a default invalid port */
lsb_ = 1;
msb_ = 0;
return;
}
/* check if port size is valid > 0 */
bool BasicPort::is_valid() const {
/* msb should be equal or greater than lsb, if this is a valid port */
if ( msb_ < lsb_ ) {
return false;
}
return true;
}
/* ConfPorts member functions */
/* Constructor */
/* Default constructor */
ConfPorts::ConfPorts() {
/* default port */
reserved_.reset();
regular_.reset();
}
/* copy */
ConfPorts::ConfPorts(const ConfPorts& conf_ports) {
set(conf_ports);
}
/* Accessors */
size_t ConfPorts::get_reserved_port_width() const {
return reserved_.get_width();
}
size_t ConfPorts::get_reserved_port_lsb() const {
return reserved_.get_lsb();
}
size_t ConfPorts::get_reserved_port_msb() const {
return reserved_.get_msb();
}
size_t ConfPorts::get_regular_port_width() const {
return regular_.get_width();
}
size_t ConfPorts::get_regular_port_lsb() const {
return regular_.get_lsb();
}
size_t ConfPorts::get_regular_port_msb() const {
return regular_.get_msb();
}
/* Mutators */
void ConfPorts::set(const ConfPorts& conf_ports) {
set_reserved_port(conf_ports.get_reserved_port_width());
set_regular_port(conf_ports.get_regular_port_lsb(), conf_ports.get_regular_port_msb());
return;
}
void ConfPorts::set_reserved_port(size_t width) {
reserved_.set_width(width);
return;
}
void ConfPorts::set_regular_port(size_t width) {
regular_.set_width(width);
return;
}
void ConfPorts::set_regular_port(size_t lsb, size_t msb) {
regular_.set_width(lsb, msb);
return;
}
void ConfPorts::set_regular_port_lsb(size_t lsb) {
regular_.set_lsb(lsb);
return;
}
void ConfPorts::set_regular_port_msb(size_t msb) {
regular_.set_msb(msb);
return;
}
/* Increase the port width of reserved port */
void ConfPorts::expand_reserved_port(size_t width) {
reserved_.expand(width);
return;
}
/* Increase the port width of regular port */
void ConfPorts::expand_regular_port(size_t width) {
regular_.expand(width);
return;
}
/* Increase the port width of both ports */
void ConfPorts::expand(size_t width) {
expand_reserved_port(width);
expand_regular_port(width);
}
/* rotate */
bool ConfPorts::rotate_regular_port(size_t offset) {
return regular_.rotate(offset);
}
/* counter rotate */
bool ConfPorts::counter_rotate_regular_port(size_t offset) {
return regular_.counter_rotate(offset);
}
/* Reset to initial port */
void ConfPorts::reset() {
reserved_.reset();
regular_.reset();
return;
}

73
vpr7_x2p/vpr/SRC/fpga_x2p/base/device_port.h Normal file
View File

@ -0,0 +1,73 @@
/* IMPORTANT:
* The following preprocessing flags are added to
* avoid compilation error when this headers are included in more than 1 times
*/
#ifndef DEVICE_PORT_H
#define DEVICE_PORT_H
/* A basic port */
class BasicPort {
public: /* Constructors */
BasicPort();
BasicPort(const BasicPort& basic_port); /* Copy constructor */
public: /* Accessors */
size_t get_width() const; /* get the port width */
size_t get_msb() const; /* get the LSB */
size_t get_lsb() const; /* get the LSB */
public: /* Mutators */
void set(const BasicPort& basic_port); /* copy */
void set_width(size_t width); /* set the port LSB and MSB */
void set_width(size_t lsb, size_t msb); /* set the port LSB and MSB */
void set_lsb(size_t lsb);
void set_msb(size_t msb);
void expand(size_t width); /* Increase the port width */
void revert(); /* Swap lsb and msb */
bool rotate(size_t offset); /* rotate */
bool counter_rotate(size_t offset); /* counter rotate */
void reset(); /* Reset to initial port */
void combine(const BasicPort& port); /* Combine two ports */
private: /* internal functions */
void make_invalid(); /* Make a port invalid */
bool is_valid() const; /* check if port size is valid > 0 */
private: /* Internal Data */
size_t msb_; /* Most Significant Bit of this port */
size_t lsb_; /* Least Significant Bit of this port */
};
/* Configuration ports:
* 1. reserved configuration port, which is used by RRAM FPGA architecture
* 2. regular configuration port, which is used by any FPGA architecture
*/
class ConfPorts {
public: /* Constructors */
ConfPorts(); /* default port */
ConfPorts(const ConfPorts& conf_ports); /* copy */
public: /* Accessors */
size_t get_reserved_port_width() const;
size_t get_reserved_port_lsb() const;
size_t get_reserved_port_msb() const;
size_t get_regular_port_width() const;
size_t get_regular_port_lsb() const;
size_t get_regular_port_msb() const;
public: /* Mutators */
void set(const ConfPorts& conf_ports);
void set_reserved_port(size_t width);
void set_regular_port(size_t width);
void set_regular_port(size_t lsb, size_t msb);
void set_regular_port_lsb(size_t lsb);
void set_regular_port_msb(size_t msb);
void expand_reserved_port(size_t width); /* Increase the port width of reserved port */
void expand_regular_port(size_t width); /* Increase the port width of regular port */
void expand(size_t width); /* Increase the port width of both ports */
bool rotate_regular_port(size_t offset); /* rotate */
bool counter_rotate_regular_port(size_t offset); /* counter rotate */
void reset(); /* Reset to initial port */
private: /* Internal Data */
BasicPort reserved_;
BasicPort regular_;
};
/* TODO: create a class for BL and WL ports */
#endif

80
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
View File

@ -1031,8 +1031,8 @@ RRGSB rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
/* 1. BOTTOM-LEFT corner:
* nothing to do. This is the base we like
*/
if ( ( 0 == rotated_rr_switch_block.get_x())
&& ( 0 == rotated_rr_switch_block.get_y()) ) {
if ( ( 0 == rotated_rr_switch_block.get_sb_x())
&& ( 0 == rotated_rr_switch_block.get_sb_y()) ) {
return rotated_rr_switch_block;
}
@ -1040,8 +1040,8 @@ RRGSB rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
* swap the opin_node between TOP and BOTTOM,
* swap the chan_node between TOP and BOTTOM,
*/
if ( ( 0 == rotated_rr_switch_block.get_x())
&& (device_range.get_y() == rotated_rr_switch_block.get_y()) ) {
if ( ( 0 == rotated_rr_switch_block.get_sb_x())
&& (device_range.get_y() == rotated_rr_switch_block.get_sb_y()) ) {
rotated_rr_switch_block.swap_opin_node(TOP, BOTTOM);
rotated_rr_switch_block.swap_chan_node(TOP, BOTTOM);
return rotated_rr_switch_block;
@ -1053,8 +1053,8 @@ RRGSB rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
* swap the opin_node between LEFT and RIGHT,
* swap the chan_node between LEFT and RIGHT,
*/
if ( (device_range.get_x() == rotated_rr_switch_block.get_x())
&& (device_range.get_y() == rotated_rr_switch_block.get_y()) ) {
if ( (device_range.get_x() == rotated_rr_switch_block.get_sb_x())
&& (device_range.get_y() == rotated_rr_switch_block.get_sb_y()) ) {
rotated_rr_switch_block.swap_opin_node(TOP, BOTTOM);
rotated_rr_switch_block.swap_chan_node(TOP, BOTTOM);
rotated_rr_switch_block.swap_opin_node(LEFT, RIGHT);
@ -1065,8 +1065,8 @@ RRGSB rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
* swap the opin_node between LEFT and RIGHT,
* swap the chan_node between LEFT and RIGHT,
*/
if ( (device_range.get_x() == rotated_rr_switch_block.get_x())
&& (0 == rotated_rr_switch_block.get_y()) ) {
if ( (device_range.get_x() == rotated_rr_switch_block.get_sb_x())
&& (0 == rotated_rr_switch_block.get_sb_y()) ) {
rotated_rr_switch_block.swap_opin_node(LEFT, RIGHT);
rotated_rr_switch_block.swap_chan_node(LEFT, RIGHT);
return rotated_rr_switch_block;
@ -1076,24 +1076,24 @@ RRGSB rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
/* 1. BOTTOM side:
* nothing to do. This is the base we like
*/
if ( 0 == rotated_rr_switch_block.get_y()) {
if ( 0 == rotated_rr_switch_block.get_sb_y()) {
return rotated_rr_switch_block;
}
/* 2. TOP side:
* swap the opin_node between TOP and BOTTOM,
* swap the chan_node between TOP and BOTTOM,
*/
if (device_range.get_y() == rotated_rr_switch_block.get_y() ) {
if (device_range.get_y() == rotated_rr_switch_block.get_sb_y() ) {
/* For RIGHT SIDE: X-channel in INC_DIRECTION, rotate by an offset of its x-coordinator */
rotated_rr_switch_block.rotate_side_chan_node_by_direction(RIGHT, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_x() - 1));
rotated_rr_switch_block.rotate_side_chan_node_by_direction(RIGHT, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_x() - 1));
/* Rotate the same nodes on the opposite side */
rotated_rr_switch_block.rotate_side_chan_node_by_direction(LEFT, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_x() - 1));
rotated_rr_switch_block.rotate_side_chan_node_by_direction(LEFT, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_x() - 1));
/* For LEFT SIDE: X-channel in DEC_DIRECTION, rotate by an offset of its x-coordinator */
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(LEFT, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_x() - 1));
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(LEFT, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_x() - 1));
/* Rotate the same nodes on the opposite side */
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(RIGHT, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_x() - 1));
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(RIGHT, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_x() - 1));
//rotated_rr_switch_block.swap_opin_node(TOP, BOTTOM);
//rotated_rr_switch_block.swap_chan_node(TOP, BOTTOM);
@ -1106,17 +1106,17 @@ RRGSB rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
* swap the opin_node between LEFT and RIGHT,
* swap the chan_node between LEFT and RIGHT,
*/
if (device_range.get_x() == rotated_rr_switch_block.get_x() ) {
if (device_range.get_x() == rotated_rr_switch_block.get_sb_x() ) {
/* For TOP SIDE: Y-channel in INC_DIRECTION, rotate by an offset of its y-coordinator */
rotated_rr_switch_block.rotate_side_chan_node_by_direction(TOP, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_y() - 1));
rotated_rr_switch_block.rotate_side_chan_node_by_direction(TOP, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_y() - 1));
/* Rotate the same nodes on the opposite side */
rotated_rr_switch_block.rotate_side_chan_node_by_direction(BOTTOM, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_y() - 1));
rotated_rr_switch_block.rotate_side_chan_node_by_direction(BOTTOM, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_y() - 1));
/* For BOTTOM SIDE: Y-channel in DEC_DIRECTION, rotate by an offset of its y-coordinator */
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(BOTTOM, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_y() - 1));
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(BOTTOM, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_y() - 1));
/* Rotate the same nodes on the opposite side */
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(TOP, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_y() - 1));
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(TOP, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_y() - 1));
//rotated_rr_switch_block.swap_opin_node(LEFT, RIGHT);
//rotated_rr_switch_block.swap_chan_node(LEFT, RIGHT);
@ -1128,43 +1128,43 @@ RRGSB rotate_rr_switch_block_for_mirror(DeviceCoordinator& device_range,
/* 4. LEFT side:
* nothing to do. This is the base we like
*/
if (0 == rotated_rr_switch_block.get_x() ) {
if (0 == rotated_rr_switch_block.get_sb_x() ) {
return rotated_rr_switch_block;
}
/* SB[1][1] is the baseline, we do not modify */
if ( (1 == rotated_rr_switch_block.get_x())
&& (1 == rotated_rr_switch_block.get_y()) ) {
if ( (1 == rotated_rr_switch_block.get_sb_x())
&& (1 == rotated_rr_switch_block.get_sb_y()) ) {
return rotated_rr_switch_block;
}
/* Reach here, it means we have a SB at the center region */
/* For TOP SIDE: Y-channel in INC_DIRECTION, rotate by an offset of its y-coordinator */
if (1 < rotated_rr_switch_block.get_y()) {
rotated_rr_switch_block.rotate_side_chan_node_by_direction(TOP, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_y() - 1));
if (1 < rotated_rr_switch_block.get_sb_y()) {
rotated_rr_switch_block.rotate_side_chan_node_by_direction(TOP, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_y() - 1));
/* Rotate the same nodes on the opposite side */
rotated_rr_switch_block.rotate_side_chan_node_by_direction(BOTTOM, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_y() - 1));
rotated_rr_switch_block.rotate_side_chan_node_by_direction(BOTTOM, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_y() - 1));
}
/* For RIGHT SIDE: X-channel in INC_DIRECTION, rotate by an offset of its x-coordinator */
if (1 < rotated_rr_switch_block.get_x()) {
rotated_rr_switch_block.rotate_side_chan_node_by_direction(RIGHT, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_x() - 1));
if (1 < rotated_rr_switch_block.get_sb_x()) {
rotated_rr_switch_block.rotate_side_chan_node_by_direction(RIGHT, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_x() - 1));
/* Rotate the same nodes on the opposite side */
rotated_rr_switch_block.rotate_side_chan_node_by_direction(LEFT, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_x() - 1));
rotated_rr_switch_block.rotate_side_chan_node_by_direction(LEFT, INC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_x() - 1));
}
/* For BOTTOM SIDE: Y-channel in DEC_DIRECTION, rotate by an offset of its y-coordinator */
if ( 1 < rotated_rr_switch_block.get_y()) {
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(BOTTOM, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_y() - 1));
if ( 1 < rotated_rr_switch_block.get_sb_y()) {
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(BOTTOM, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_y() - 1));
/* Rotate the same nodes on the opposite side */
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(TOP, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_y() - 1));
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(TOP, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_y() - 1));
}
/* For LEFT SIDE: X-channel in DEC_DIRECTION, rotate by an offset of its x-coordinator */
if ( 1 < rotated_rr_switch_block.get_x()) {
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(LEFT, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_x() - 1));
if ( 1 < rotated_rr_switch_block.get_sb_x()) {
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(LEFT, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_x() - 1));
/* Rotate the same nodes on the opposite side */
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(RIGHT, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_x() - 1));
rotated_rr_switch_block.counter_rotate_side_chan_node_by_direction(RIGHT, DEC_DIRECTION, Fco_offset * (rotated_rr_switch_block.get_sb_x() - 1));
}
return rotated_rr_switch_block;
@ -1192,10 +1192,10 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) {
RRGSB rr_sb = build_rr_switch_block(sb_range, ix, iy,
LL_num_rr_nodes, LL_rr_node,
LL_rr_node_indices,
num_segments, LL_rr_indexed_data);
DeviceCoordinator sb_coordinator = rr_sb.get_coordinator();
LL_num_rr_nodes, LL_rr_node,
LL_rr_node_indices,
num_segments, LL_rr_indexed_data);
DeviceCoordinator sb_coordinator = rr_sb.get_sb_coordinator();
LL_drive_rr_gsb.add_rr_switch_block(sb_coordinator, rr_sb);
}
}
@ -1249,9 +1249,9 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) {
RRGSB rr_sb = LL_drive_rr_gsb.get_switch_block(ix, iy);
RRGSB rr_sb = LL_drive_rr_gsb.get_gsb(ix, iy);
RRGSB rotated_rr_sb = rotate_rr_switch_block_for_mirror(sb_range, rr_sb);
DeviceCoordinator sb_coordinator = rr_sb.get_coordinator();
DeviceCoordinator sb_coordinator = rr_sb.get_sb_coordinator();
LL_drive_rr_gsb.add_rotatable_mirror(sb_coordinator, rotated_rr_sb);
if (TRUE == output_sb_xml) {

47
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c
View File

@ -156,8 +156,8 @@ int create_dir_path(char* dir_path) {
}
/* Cat string2 to the end of string1 */
char* my_strcat(char* str1,
char* str2) {
char* my_strcat(const char* str1,
const char* str2) {
int len1 = strlen(str1);
int len2 = strlen(str2);
char* ret = (char*)my_malloc(sizeof(char) * (len1 + len2 + 1));
@ -897,49 +897,6 @@ char* convert_process_corner_to_string(enum e_process_corner process_corner) {
}
}
char* convert_cb_type_to_string(t_rr_type chan_type) {
switch(chan_type) {
case CHANX:
return "cbx";
break;
case CHANY:
return "cby";
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__);
exit(1);
}
}
char* convert_chan_type_to_string(t_rr_type chan_type) {
switch(chan_type) {
case CHANX:
return "chanx";
break;
case CHANY:
return "chany";
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__);
exit(1);
}
}
char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction) {
switch(chan_rr_node_direction) {
case IN_PORT:
return "in";
break;
case OUT_PORT:
return "out";
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of port!\n", __FILE__, __LINE__);
exit(1);
}
}
void init_spice_net_info(t_spice_net_info* spice_net_info) {
if (NULL == spice_net_info) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_net_info!\n", __FILE__, __LINE__);

11
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h
View File

@ -2,6 +2,7 @@
#define FPGA_X2P_UTILS_H
#include "my_free_fwd.h"
#include "rr_blocks_naming.h"
char* my_gettime();
@ -13,8 +14,8 @@ void my_remove_file(char* file_path);
int create_dir_path(char* dir_path);
char* my_strcat(char* str1,
char* str2);
char* my_strcat(const char* str1,
const char* str2);
int split_path_prog_name(char* prog_path,
char split_token,
@ -84,12 +85,6 @@ char* convert_side_index_to_string(int side);
char* convert_process_corner_to_string(enum e_process_corner process_corner);
char* convert_chan_type_to_string(t_rr_type chan_type);
char* convert_cb_type_to_string(t_rr_type chan_type);
char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction);
void init_spice_net_info(t_spice_net_info* spice_net_info);
t_spice_model* find_iopad_spice_model(int num_spice_model,

496
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp
View File

@ -2,6 +2,8 @@
#include <string>
#include <algorithm>
#include "rr_blocks_naming.h"
#include "rr_blocks.h"
@ -511,11 +513,9 @@ RRGSB::RRGSB() {
opin_node_.clear();
opin_node_grid_side_.clear();
reserved_conf_bits_lsb_ = 1;
reserved_conf_bits_msb_ = 0;
conf_bits_lsb_ = 1;
conf_bits_msb_ = 0;
sb_conf_port_.reset();
cbx_conf_port_.reset();
cby_conf_port_.reset();
return;
}
@ -529,21 +529,6 @@ RRGSB::RRGSB(const RRGSB& src) {
/* Accessors */
/* get the x coordinator of this switch block */
size_t RRGSB::get_x() const {
return coordinator_.get_x();
}
/* get the y coordinator of this switch block */
size_t RRGSB::get_y() const {
return coordinator_.get_y();
}
/* Get the number of sides of this SB */
DeviceCoordinator RRGSB::get_coordinator() const {
return coordinator_;
}
/* Get the number of sides of this SB */
size_t RRGSB::get_num_sides() const {
assert (validate_num_sides());
@ -718,8 +703,8 @@ enum e_side RRGSB::get_opin_node_grid_side(t_rr_node* opin_node) const {
/* Get the node index in the array, return -1 if not found */
int RRGSB::get_node_index(t_rr_node* node,
enum e_side node_side,
enum PORTS node_direction) const {
enum e_side node_side,
enum PORTS node_direction) const {
size_t cnt;
int ret;
Side side_manager(node_side);
@ -767,8 +752,8 @@ int RRGSB::get_node_index(t_rr_node* node,
}
/* Check if the node exist in the opposite side of this Switch Block */
bool RRGSB::is_node_exist_opposite_side(t_rr_node* node,
enum e_side node_side) const {
bool RRGSB::is_sb_node_exist_opposite_side(t_rr_node* node,
enum e_side node_side) const {
Side side_manager(node_side);
int index;
@ -788,9 +773,9 @@ bool RRGSB::is_node_exist_opposite_side(t_rr_node* node,
/* Get the side of a node in this SB */
void RRGSB::get_node_side_and_index(t_rr_node* node,
enum PORTS node_direction,
enum e_side* node_side,
int* node_index) const {
enum PORTS node_direction,
enum e_side* node_side,
int* node_index) const {
size_t side;
Side side_manager;
@ -822,50 +807,124 @@ void RRGSB::get_node_side_and_index(t_rr_node* node,
return;
}
size_t RRGSB::get_num_reserved_conf_bits() const {
if (false == validate_num_reserved_conf_bits()) {
return 0;
}
return reserved_conf_bits_msb_ - reserved_conf_bits_lsb_ + 1;
/* Get Switch Block configuration port information */
size_t RRGSB::get_sb_num_reserved_conf_bits() const {
return sb_conf_port_.get_reserved_port_width();
}
size_t RRGSB::get_reserved_conf_bits_lsb() const {
if (false == validate_num_reserved_conf_bits()) {
return 0;
}
return reserved_conf_bits_lsb_;
size_t RRGSB::get_sb_reserved_conf_bits_lsb() const {
return sb_conf_port_.get_reserved_port_lsb();
}
size_t RRGSB::get_reserved_conf_bits_msb() const {
if (false == validate_num_reserved_conf_bits()) {
return 0;
}
return reserved_conf_bits_msb_;
size_t RRGSB::get_sb_reserved_conf_bits_msb() const {
return sb_conf_port_.get_reserved_port_msb();
}
size_t RRGSB::get_num_conf_bits() const {
if (false == validate_num_conf_bits()) {
return 0;
}
return conf_bits_msb_ - conf_bits_lsb_ + 1;
size_t RRGSB::get_sb_num_conf_bits() const {
return sb_conf_port_.get_regular_port_width();
}
size_t RRGSB::get_conf_bits_lsb() const {
if (false == validate_num_conf_bits()) {
return 0;
}
return conf_bits_lsb_;
size_t RRGSB::get_sb_conf_bits_lsb() const {
return sb_conf_port_.get_regular_port_lsb();
}
size_t RRGSB::get_conf_bits_msb() const {
if (false == validate_num_conf_bits()) {
return 0;
size_t RRGSB::get_sb_conf_bits_msb() const {
return sb_conf_port_.get_regular_port_msb();
}
/* Get X-direction Connection Block configuration port information */
size_t RRGSB::get_cb_num_reserved_conf_bits(t_rr_type cb_type) const {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return cbx_conf_port_.get_reserved_port_width();
case CHANY:
return cby_conf_port_.get_reserved_port_width();
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
}
size_t RRGSB::get_cb_reserved_conf_bits_lsb(t_rr_type cb_type) const {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return cbx_conf_port_.get_reserved_port_lsb();
case CHANY:
return cby_conf_port_.get_reserved_port_lsb();
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
}
size_t RRGSB::get_cb_reserved_conf_bits_msb(t_rr_type cb_type) const {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return cbx_conf_port_.get_reserved_port_msb();
case CHANY:
return cby_conf_port_.get_reserved_port_msb();
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
}
size_t RRGSB::get_cb_num_conf_bits(t_rr_type cb_type) const {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return cbx_conf_port_.get_regular_port_width();
case CHANY:
return cby_conf_port_.get_regular_port_width();
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
}
size_t RRGSB::get_cb_conf_bits_lsb(t_rr_type cb_type) const {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return cbx_conf_port_.get_regular_port_lsb();
case CHANY:
return cby_conf_port_.get_regular_port_lsb();
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
}
size_t RRGSB::get_cb_conf_bits_msb(t_rr_type cb_type) const {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return cbx_conf_port_.get_regular_port_msb();
case CHANY:
return cby_conf_port_.get_regular_port_msb();
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
return conf_bits_msb_;
}
/* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */
bool RRGSB::is_node_imply_short_connection(t_rr_node* src_node) const {
bool RRGSB::is_sb_node_imply_short_connection(t_rr_node* src_node) const {
assert((CHANX == src_node->type) || (CHANY == src_node->type));
@ -889,7 +948,7 @@ bool RRGSB::is_node_imply_short_connection(t_rr_node* src_node) const {
* Number of channel/opin/ipin rr_nodes are same
* If all above are satisfied, the two switch blocks may be mirrors !
*/
bool RRGSB::is_mirrorable(RRGSB& cand) const {
bool RRGSB::is_sb_mirrorable(RRGSB& cand) const {
/* check the numbers of sides */
if (get_num_sides() != cand.get_num_sides()) {
return false;
@ -960,7 +1019,7 @@ size_t RRGSB::get_hint_rotate_offset(RRGSB& cand) const {
}
/* check if all the routing segments of a side of candidate SB is a mirror of the current one */
bool RRGSB::is_side_segment_mirror(RRGSB& cand, enum e_side side, size_t seg_id) const {
bool RRGSB::is_sb_side_segment_mirror(RRGSB& cand, enum e_side side, size_t seg_id) const {
/* Create a side manager */
Side side_manager(side);
@ -994,7 +1053,7 @@ bool RRGSB::is_side_segment_mirror(RRGSB& cand, enum e_side side, size_t seg_id)
continue; /* skip IN_PORT */
}
if (false == is_node_mirror(cand, side, itrack)) {
if (false == is_sb_node_mirror(cand, side, itrack)) {
return false;
}
}
@ -1023,13 +1082,13 @@ bool RRGSB::is_side_segment_mirror(RRGSB& cand, enum e_side side, size_t seg_id)
* 5. check if pin class id and pin id are same
* If all above are satisfied, the side of the two switch blocks are mirrors!
*/
bool RRGSB::is_side_mirror(RRGSB& cand, enum e_side side) const {
bool RRGSB::is_sb_side_mirror(RRGSB& cand, enum e_side side) const {
/* get a list of segments */
std::vector<size_t> seg_ids = get_chan(side).get_segment_ids();
for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) {
if (false == is_side_segment_mirror(cand, side, seg_ids[iseg])) {
if (false == is_sb_side_segment_mirror(cand, side, seg_ids[iseg])) {
return false;
}
}
@ -1050,7 +1109,7 @@ bool RRGSB::is_side_mirror(RRGSB& cand, enum e_side side) const {
* 5. check if pin class id and pin id are same
* If all above are satisfied, the two switch blocks are mirrors!
*/
bool RRGSB::is_mirror(RRGSB& cand) const {
bool RRGSB::is_sb_mirror(RRGSB& cand) const {
/* check the numbers of sides */
if (get_num_sides() != cand.get_num_sides()) {
return false;
@ -1059,27 +1118,89 @@ bool RRGSB::is_mirror(RRGSB& cand) const {
/* check the numbers/directionality of channel rr_nodes */
for (size_t side = 0; side < get_num_sides(); ++side) {
Side side_manager(side);
if (false == is_side_mirror(cand, side_manager.get_side())) {
if (false == is_sb_side_mirror(cand, side_manager.get_side())) {
return false;
}
}
/* Make sure the number of conf bits are the same */
/* TODO: the num conf bits will be fixed when allocate the SBs
if ( ( get_num_conf_bits() != cand.get_num_conf_bits() )
|| ( get_num_reserved_conf_bits() != cand.get_num_reserved_conf_bits() ) ) {
if ( ( get_sb_num_conf_bits() != cand.get_sb_num_conf_bits() )
|| ( get_sb_num_reserved_conf_bits() != cand.get_sb_num_reserved_conf_bits() ) ) {
return false;
}
*/
return true;
}
/* Public Accessors: Cooridinator conversion */
/* get the x coordinator of this switch block */
size_t RRGSB::get_sb_x() const {
return coordinator_.get_x();
}
/* get the y coordinator of this switch block */
size_t RRGSB::get_sb_y() const {
return coordinator_.get_y();
}
/* Get the number of sides of this SB */
DeviceCoordinator RRGSB::get_sb_coordinator() const {
return coordinator_;
}
/* get the x coordinator of this X/Y-direction block */
size_t RRGSB::get_cb_x(t_rr_type cb_type) const {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return get_side_block_coordinator(LEFT).get_x();
case CHANY:
return get_side_block_coordinator(TOP).get_x();
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
}
/* get the y coordinator of this X/Y-direction block */
size_t RRGSB::get_cb_y(t_rr_type cb_type) const {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return get_side_block_coordinator(LEFT).get_y();
case CHANY:
return get_side_block_coordinator(TOP).get_y();
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
}
/* Get the coordinator of the X/Y-direction CB */
DeviceCoordinator RRGSB::get_cb_coordinator(t_rr_type cb_type) const {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return get_side_block_coordinator(LEFT);
case CHANY:
return get_side_block_coordinator(TOP);
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
}
DeviceCoordinator RRGSB::get_side_block_coordinator(enum e_side side) const {
Side side_manager(side);
assert(side_manager.validate());
DeviceCoordinator ret(get_x(), get_y());
DeviceCoordinator ret(get_sb_x(), get_sb_y());
switch (side_manager.get_side()) {
case TOP:
@ -1111,77 +1232,76 @@ DeviceCoordinator RRGSB::get_side_block_coordinator(enum e_side side) const {
}
/* Public Accessors Verilog writer */
char* RRGSB::gen_verilog_module_name() const {
char* ret = NULL;
std::string x_str = std::to_string(get_x());
std::string y_str = std::to_string(get_y());
ret = (char*)my_malloc(2 + 1 + x_str.length()
+ 2 + y_str.length()
+ 1 + 1);
const char* RRGSB::gen_sb_verilog_module_name() const {
std::string x_str = std::to_string(get_sb_x());
std::string y_str = std::to_string(get_sb_y());
sprintf(ret, "sb_%lu__%lu_",
get_x(), get_y());
std::string ret = "sb_" + x_str + "__" + y_str + "_";
return ret;
return ret.c_str();
}
char* RRGSB::gen_verilog_instance_name() const {
char* ret = NULL;
std::string x_str = std::to_string(get_x());
std::string y_str = std::to_string(get_y());
const char* RRGSB::gen_sb_verilog_instance_name() const {
std::string x_str = std::to_string(get_sb_x());
std::string y_str = std::to_string(get_sb_y());
ret = (char*)my_malloc(2 + 1 + x_str.length()
+ 2 + y_str.length()
+ 4 + 1);
std::string ret = "sb_" + x_str + "__" + y_str + "__0_";
sprintf(ret, "sb_%lu__%lu__0_",
get_x(), get_y());
return ret;
return ret.c_str();
}
/* Public Accessors Verilog writer */
char* RRGSB::gen_verilog_side_module_name(enum e_side side, size_t seg_id) const {
char* ret = NULL;
const char* RRGSB::gen_sb_verilog_side_module_name(enum e_side side, size_t seg_id) const {
Side side_manager(side);
std::string x_str = std::to_string(get_x());
std::string y_str = std::to_string(get_y());
std::string x_str = std::to_string(get_sb_x());
std::string y_str = std::to_string(get_sb_y());
std::string seg_id_str = std::to_string(seg_id);
std::string side_str(side_manager.to_string());
ret = (char*)my_malloc(2 + 1 + x_str.length()
+ 2 + y_str.length()
+ 2 + side_str.length()
+ 2 + 3 + seg_id_str.length()
+ 1 + 1);
std::string ret = "sb_" + x_str + "__" + y_str + "__" + side_str + "_seg_" + seg_id_str + "_";
sprintf(ret, "sb_%lu__%lu__%s_seg%lu_",
get_x(), get_y(), side_manager.to_string(), seg_id);
return ret;
return ret.c_str();
}
char* RRGSB::gen_verilog_side_instance_name(enum e_side side, size_t seg_id) const {
char* ret = NULL;
const char* RRGSB::gen_sb_verilog_side_instance_name(enum e_side side, size_t seg_id) const {
Side side_manager(side);
std::string x_str = std::to_string(get_x());
std::string y_str = std::to_string(get_y());
std::string x_str = std::to_string(get_sb_x());
std::string y_str = std::to_string(get_sb_y());
std::string seg_id_str = std::to_string(seg_id);
std::string side_str(side_manager.to_string());
std::string ret = "sb_" + x_str + "__" + y_str + "__" + side_str + "_seg_" + seg_id_str + "__0_";
ret = (char*)my_malloc(2 + 1 + x_str.length()
+ 2 + y_str.length()
+ 2 + side_str.length()
+ 2 + 3 + seg_id_str.length()
+ 4 + 1);
return ret.c_str();
}
sprintf(ret, "sb_%lu__%lu__%s_seg%lu_0_",
get_x(), get_y(), side_manager.to_string(), seg_id);
/* Public Accessors Verilog writer */
const char* RRGSB::gen_cb_verilog_module_name(t_rr_type cb_type) const {
/* check */
assert (validate_cb_type(cb_type));
return ret;
std::string x_str = std::to_string(get_cb_x(cb_type));
std::string y_str = std::to_string(get_cb_y(cb_type));
std::string ret = convert_cb_type_to_string(cb_type);
ret = "_" + x_str + "__" + y_str + "_";
return ret.c_str();
}
const char* RRGSB::gen_cb_verilog_instance_name(t_rr_type cb_type) const {
/* check */
assert (validate_cb_type(cb_type));
std::string x_str = std::to_string(get_cb_x(cb_type));
std::string y_str = std::to_string(get_cb_y(cb_type));
std::string ret = convert_cb_type_to_string(cb_type);
ret = "_" + x_str + "__" + y_str + "__0_";
return ret.c_str();
}
/* Public mutators */
@ -1189,7 +1309,7 @@ char* RRGSB::gen_verilog_side_instance_name(enum e_side side, size_t seg_id) con
/* get a copy from a source */
void RRGSB::set(const RRGSB& src) {
/* Copy coordinator */
this->set_coordinator(src.get_coordinator().get_x(), src.get_coordinator().get_y());
this->set_coordinator(src.get_sb_coordinator().get_x(), src.get_sb_coordinator().get_y());
/* Initialize sides */
this->init_num_sides(src.get_num_sides());
@ -1224,14 +1344,21 @@ void RRGSB::set(const RRGSB& src) {
/* Copy conf_bits
*/
this->set_num_reserved_conf_bits(src.get_num_reserved_conf_bits());
this->set_conf_bits_lsb(src.get_conf_bits_lsb());
this->set_conf_bits_msb(src.get_conf_bits_msb());
this->set_sb_num_reserved_conf_bits(src.get_sb_num_reserved_conf_bits());
this->set_sb_conf_bits_lsb(src.get_sb_conf_bits_lsb());
this->set_sb_conf_bits_msb(src.get_sb_conf_bits_msb());
this->set_cb_num_reserved_conf_bits(CHANX, src.get_cb_num_reserved_conf_bits(CHANX));
this->set_cb_conf_bits_lsb(CHANX, src.get_cb_conf_bits_lsb(CHANX));
this->set_cb_conf_bits_msb(CHANX, src.get_cb_conf_bits_msb(CHANX));
this->set_cb_num_reserved_conf_bits(CHANY, src.get_cb_num_reserved_conf_bits(CHANY));
this->set_cb_conf_bits_lsb(CHANY, src.get_cb_conf_bits_lsb(CHANY));
this->set_cb_conf_bits_msb(CHANY, src.get_cb_conf_bits_msb(CHANY));
return;
}
/* Set the coordinator (x,y) for the switch block */
void RRGSB::set_coordinator(size_t x, size_t y) {
coordinator_.set(x, y);
@ -1288,27 +1415,61 @@ void RRGSB::add_opin_node(t_rr_node* node, enum e_side node_side, enum e_side gr
return;
}
void RRGSB::set_num_reserved_conf_bits(size_t num_reserved_conf_bits) {
/* For zero bits: make it invalid */
if ( 0 == num_reserved_conf_bits ) {
reserved_conf_bits_lsb_ = 1;
reserved_conf_bits_msb_ = 0;
return;
void RRGSB::set_sb_num_reserved_conf_bits(size_t num_reserved_conf_bits) {
return sb_conf_port_.set_reserved_port(num_reserved_conf_bits);
}
void RRGSB::set_sb_conf_bits_lsb(size_t conf_bits_lsb) {
return sb_conf_port_.set_regular_port_lsb(conf_bits_lsb);
}
void RRGSB::set_sb_conf_bits_msb(size_t conf_bits_msb) {
return sb_conf_port_.set_regular_port_msb(conf_bits_msb);
}
void RRGSB::set_cb_num_reserved_conf_bits(t_rr_type cb_type, size_t num_reserved_conf_bits) {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return cbx_conf_port_.set_reserved_port(num_reserved_conf_bits);
case CHANY:
return cby_conf_port_.set_reserved_port(num_reserved_conf_bits);
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
reserved_conf_bits_lsb_ = 0;
reserved_conf_bits_msb_ = num_reserved_conf_bits - 1;
return;
}
void RRGSB::set_conf_bits_lsb(size_t conf_bits_lsb) {
conf_bits_lsb_ = conf_bits_lsb;
return;
void RRGSB::set_cb_conf_bits_lsb(t_rr_type cb_type, size_t conf_bits_lsb) {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return cbx_conf_port_.set_regular_port_lsb(conf_bits_lsb);
case CHANY:
return cby_conf_port_.set_regular_port_lsb(conf_bits_lsb);
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
}
void RRGSB::set_conf_bits_msb(size_t conf_bits_msb) {
conf_bits_msb_ = conf_bits_msb;
return;
void RRGSB::set_cb_conf_bits_msb(t_rr_type cb_type, size_t conf_bits_msb) {
assert (validate_cb_type(cb_type));
switch(cb_type) {
case CHANX:
return cbx_conf_port_.set_regular_port_msb(conf_bits_msb);
case CHANY:
return cby_conf_port_.set_regular_port_msb(conf_bits_msb);
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of connection block!\n",
__FILE__, __LINE__);
exit(1);
}
}
/* rotate the channel nodes with the same direction on one side by a given offset */
@ -1576,11 +1737,9 @@ void RRGSB::clear() {
opin_node_grid_side_.clear();
/* Just to make the lsb and msb invalidate */
reserved_conf_bits_lsb_ = 1;
reserved_conf_bits_msb_ = 0;
/* Just to make the lsb and msb invalidate */
set_conf_bits_lsb(1);
set_conf_bits_msb(0);
sb_conf_port_.reset();
cbx_conf_port_.reset();
cby_conf_port_.reset();
return;
}
@ -1633,22 +1792,22 @@ void RRGSB::clear_one_side(enum e_side node_side) {
* 2. OPIN or IPIN: should have the same side and index
* 3. each drive_rr_switch should be the same
*/
bool RRGSB::is_node_mirror(RRGSB& cand,
enum e_side node_side,
size_t track_id) const {
bool RRGSB::is_sb_node_mirror(RRGSB& cand,
enum e_side node_side,
size_t track_id) const {
/* Ensure rr_nodes are either the output of short-connection or multiplexer */
t_rr_node* node = this->get_chan_node(node_side, track_id);
t_rr_node* cand_node = cand.get_chan_node(node_side, track_id);
bool is_short_conkt = this->is_node_imply_short_connection(node);
bool is_short_conkt = this->is_sb_node_imply_short_connection(node);
if (is_short_conkt != cand.is_node_imply_short_connection(cand_node)) {
if (is_short_conkt != cand.is_sb_node_imply_short_connection(cand_node)) {
return false;
}
/* Find the driving rr_node in this sb */
if (true == is_short_conkt) {
/* Ensure we have the same track id for the driving nodes */
if ( this->is_node_exist_opposite_side(node, node_side)
!= cand.is_node_exist_opposite_side(cand_node, node_side)) {
if ( this->is_sb_node_exist_opposite_side(node, node_side)
!= cand.is_sb_node_exist_opposite_side(cand_node, node_side)) {
return false;
}
} else { /* check driving rr_nodes */
@ -1687,7 +1846,7 @@ size_t RRGSB::get_track_id_first_short_connection(enum e_side node_side) const {
/* Walk through chan_nodes and find the first short connection */
for (size_t inode = 0; inode < get_chan_width(node_side); ++inode) {
if (true == is_node_imply_short_connection(get_chan_node(node_side, inode))) {
if (true == is_sb_node_imply_short_connection(get_chan_node(node_side, inode))) {
return inode;
}
}
@ -1776,17 +1935,8 @@ bool RRGSB::validate_ipin_node_id(enum e_side side, size_t node_id) const {
return false;
}
/* Validate the number of configuration bits, MSB should be no less than the LSB !!! */
bool RRGSB::validate_num_conf_bits() const {
if (conf_bits_msb_ >= conf_bits_lsb_) {
return true;
}
return false;
}
/* Validate the number of configuration bits, MSB should be no less than the LSB !!! */
bool RRGSB::validate_num_reserved_conf_bits() const {
if (reserved_conf_bits_msb_ >= reserved_conf_bits_lsb_) {
bool RRGSB::validate_cb_type(t_rr_type cb_type) const {
if ( (CHANX == cb_type) || (CHANY == cb_type) ) {
return true;
}
return false;
@ -1796,7 +1946,7 @@ bool RRGSB::validate_num_reserved_conf_bits() const {
/* Accessors */
/* get the max coordinator of the switch block array */
DeviceCoordinator DeviceRRGSB::get_switch_block_range() const {
DeviceCoordinator DeviceRRGSB::get_gsb_range() const {
size_t max_y = 0;
/* Get the largest size of sub-arrays */
for (size_t x = 0; x < rr_gsb.size(); ++x) {
@ -1808,7 +1958,7 @@ DeviceCoordinator DeviceRRGSB::get_switch_block_range() const {
}
/* Get a rr switch block in the array with a coordinator */
RRGSB DeviceRRGSB::get_switch_block(DeviceCoordinator& coordinator) const {
RRGSB DeviceRRGSB::get_gsb(DeviceCoordinator& coordinator) const {
assert(validate_coordinator(coordinator));
return rr_gsb[coordinator.get_x()][coordinator.get_y()];
}
@ -1822,9 +1972,9 @@ size_t DeviceRRGSB::get_num_unique_module(enum e_side side, size_t seg_index) co
}
/* Get a rr switch block in the array with a coordinator */
RRGSB DeviceRRGSB::get_switch_block(size_t x, size_t y) const {
RRGSB DeviceRRGSB::get_gsb(size_t x, size_t y) const {
DeviceCoordinator coordinator(x, y);
return get_switch_block(coordinator);
return get_gsb(coordinator);
}
/* get the number of unique mirrors of switch blocks */
@ -1895,21 +2045,21 @@ size_t DeviceRRGSB::get_segment_id(size_t index) const {
/* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
void DeviceRRGSB::set_sb_num_reserved_conf_bits(DeviceCoordinator& coordinator, size_t num_reserved_conf_bits) {
assert(validate_coordinator(coordinator));
rr_gsb[coordinator.get_x()][coordinator.get_y()].set_num_reserved_conf_bits(num_reserved_conf_bits);
rr_gsb[coordinator.get_x()][coordinator.get_y()].set_sb_num_reserved_conf_bits(num_reserved_conf_bits);
return;
}
/* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
void DeviceRRGSB::set_sb_conf_bits_lsb(DeviceCoordinator& coordinator, size_t conf_bits_lsb) {
assert(validate_coordinator(coordinator));
rr_gsb[coordinator.get_x()][coordinator.get_y()].set_conf_bits_lsb(conf_bits_lsb);
rr_gsb[coordinator.get_x()][coordinator.get_y()].set_sb_conf_bits_lsb(conf_bits_lsb);
return;
}
/* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
void DeviceRRGSB::set_sb_conf_bits_msb(DeviceCoordinator& coordinator, size_t conf_bits_msb) {
assert(validate_coordinator(coordinator));
rr_gsb[coordinator.get_x()][coordinator.get_y()].set_conf_bits_msb(conf_bits_msb);
rr_gsb[coordinator.get_x()][coordinator.get_y()].set_sb_conf_bits_msb(conf_bits_msb);
return;
}
@ -1934,7 +2084,7 @@ void DeviceRRGSB::reserve(DeviceCoordinator& coordinator) {
/* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */
void DeviceRRGSB::reserve_unique_module_id(DeviceCoordinator& coordinator) {
RRGSB rr_sb = get_switch_block(coordinator);
RRGSB rr_sb = get_gsb(coordinator);
rr_sb_unique_module_id_[coordinator.get_x()][coordinator.get_y()].resize(rr_sb.get_num_sides());
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
@ -1996,7 +2146,7 @@ void DeviceRRGSB::build_unique_mirror() {
is_unique_mirror = false;
break;
}
if (true == get_switch_block(unique_mirror_[mirror_id]).is_mirror(*rr_sb)) {
if (true == get_gsb(unique_mirror_[mirror_id]).is_sb_mirror(*rr_sb)) {
/* This is a mirror, raise the flag and we finish */
is_unique_mirror = false;
/* Record the id of unique mirror */
@ -2053,10 +2203,10 @@ void DeviceRRGSB::add_rotatable_mirror(DeviceCoordinator& coordinator,
/* add rotatable mirror support */
for (size_t mirror_id = 0; mirror_id < get_num_rotatable_mirror(); ++mirror_id) {
/* Skip if these may never match as a mirror (violation in basic requirements */
if (false == get_switch_block(rotatable_mirror_[mirror_id]).is_mirrorable(rotated_rr_sb)) {
if (false == get_gsb(rotatable_mirror_[mirror_id]).is_sb_mirrorable(rotated_rr_sb)) {
continue;
}
if (true == get_switch_block(rotatable_mirror_[mirror_id]).is_mirror(rotated_rr_sb)) {
if (true == get_gsb(rotatable_mirror_[mirror_id]).is_sb_mirror(rotated_rr_sb)) {
/* This is a mirror, raise the flag and we finish */
is_rotatable_mirror = false;
/* Record the id of unique mirror */
@ -2088,7 +2238,7 @@ void DeviceRRGSB::add_unique_side_segment_module(DeviceCoordinator& coordinator,
/* add rotatable mirror support */
for (size_t id = 0; id < get_num_unique_module(side, seg_id); ++id) {
/* Skip if these may never match as a mirror (violation in basic requirements */
if (true == get_switch_block(unique_module_[side_manager.to_size_t()][seg_id][id]).is_side_segment_mirror(rr_sb, side, segment_ids_[seg_id])) {
if (true == get_gsb(unique_module_[side_manager.to_size_t()][seg_id][id]).is_sb_side_segment_mirror(rr_sb, side, segment_ids_[seg_id])) {
/* This is a mirror, raise the flag and we finish */
is_unique_side_module = false;
/* Record the id of unique mirror */

131
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h
View File

@ -15,6 +15,7 @@
#include <vector>
#include "device_coordinator.h"
#include "device_port.h"
#include "vpr_types.h"
/* RRChan coordinator class */
@ -102,23 +103,34 @@ class DeviceRRChan {
std::vector<RRChan> chany_modules_; /* Detailed internal structure of each unique module */
};
/* Object Switch Block
/* Object Generic Switch Block
* This block contains
* 1. A switch block
* 2. A X-direction Connection block locates at the left side of the switch block
* 2. A Y-direction Connection block locates at the top side of the switch block
* This is a collection of rr_nodes, which may be replaced with RRNodeId in new RRGraph
* TOP SIDE
* ---------------------------------
* | OPIN_NODE CHAN_NODES OPIN_NODES |
* | |
* | OPIN_NODES OPIN_NODES |
* | |
* LEFT SIDE | Switch Block | RIGHT SIDE
* | |
* | CHAN_NODES CHAN_NODES |
* | |
* | OPIN_NODES OPIN_NODES |
* | |
* | OPIN_NODE CHAN_NODES OPIN_NODES |
* ---------------------------------
* BOTTOM SIDE
*
* +---------------------------------+
* | Y-direction CB |
* | [x][y + 1] |
* +---------------------------------+
*
* TOP SIDE
* +-------------+ +---------------------------------+
* | | | OPIN_NODE CHAN_NODES OPIN_NODES |
* | | | |
* | | | OPIN_NODES OPIN_NODES |
* | X-direction | | |
* | CB | LEFT SIDE | Switch Block | RIGHT SIDE
* | [x][y] | | [x][y] |
* | | | |
* | | | CHAN_NODES CHAN_NODES |
* | | | |
* | | | OPIN_NODES OPIN_NODES |
* | | | |
* | | | OPIN_NODE CHAN_NODES OPIN_NODES |
* +-------------+ +---------------------------------+
* BOTTOM SIDE
* num_sides: number of sides of this switch block
* chan_rr_node: a collection of rr_nodes as routing tracks locating at each side of the Switch block <0..num_sides-1><0..chan_width-1>
* chan_rr_node_direction: Indicate if this rr_node is an input or an output of the Switch block <0..num_sides-1><0..chan_width-1>
@ -134,9 +146,6 @@ class RRGSB {
RRGSB(const RRGSB&);/* Copy constructor */
RRGSB();/* Default constructor */
public: /* Accessors */
size_t get_x() const; /* get the x coordinator of this switch block */
size_t get_y() const; /* get the y coordinator of this switch block */
DeviceCoordinator get_coordinator() const; /* Get the number of sides of this SB */
size_t get_num_sides() const; /* Get the number of sides of this SB */
size_t get_chan_width(enum e_side side) const; /* Get the number of routing tracks on a side */
size_t get_max_chan_width() const; /* Get the maximum number of routing tracks on all sides */
@ -154,26 +163,41 @@ class RRGSB {
enum e_side get_opin_node_grid_side(t_rr_node* opin_node) const; /* get a rr_node at a given side and track_id */
int get_node_index(t_rr_node* node, enum e_side node_side, enum PORTS node_direction) const; /* Get the node index in the array, return -1 if not found */
void get_node_side_and_index(t_rr_node* node, enum PORTS node_direction, enum e_side* node_side, int* node_index) const; /* Given a rr_node, try to find its side and index in the Switch block */
bool is_node_exist_opposite_side(t_rr_node* node, enum e_side node_side) const; /* Check if the node exist in the opposite side of this Switch Block */
size_t get_num_reserved_conf_bits() const;
size_t get_reserved_conf_bits_lsb() const;
size_t get_reserved_conf_bits_msb() const;
size_t get_num_conf_bits() const;
size_t get_conf_bits_lsb() const;
size_t get_conf_bits_msb() const;
bool is_node_imply_short_connection(t_rr_node* src_node) const; /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */
bool is_side_mirror(RRGSB& cand, enum e_side side) const; /* check if a side of candidate SB is a mirror of the current one */
bool is_side_segment_mirror(RRGSB& cand, enum e_side side, size_t seg_id) const; /* check if all the routing segments of a side of candidate SB is a mirror of the current one */
bool is_mirror(RRGSB& cand) const; /* check if the candidate SB is a mirror of the current one */
bool is_mirrorable(RRGSB& cand) const; /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */
bool is_sb_node_exist_opposite_side(t_rr_node* node, enum e_side node_side) const; /* Check if the node exist in the opposite side of this Switch Block */
public: /* Accessors: get information about configuration ports */
size_t get_sb_num_reserved_conf_bits() const;
size_t get_sb_reserved_conf_bits_lsb() const;
size_t get_sb_reserved_conf_bits_msb() const;
size_t get_sb_num_conf_bits() const;
size_t get_sb_conf_bits_lsb() const;
size_t get_sb_conf_bits_msb() const;
size_t get_cb_num_reserved_conf_bits(t_rr_type cb_type) const;
size_t get_cb_reserved_conf_bits_lsb(t_rr_type cb_type) const;
size_t get_cb_reserved_conf_bits_msb(t_rr_type cb_type) const;
size_t get_cb_num_conf_bits(t_rr_type cb_type) const;
size_t get_cb_conf_bits_lsb(t_rr_type cb_type) const;
size_t get_cb_conf_bits_msb(t_rr_type cb_type) const;
bool is_sb_node_imply_short_connection(t_rr_node* src_node) const; /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */
bool is_sb_side_mirror(RRGSB& cand, enum e_side side) const; /* check if a side of candidate SB is a mirror of the current one */
bool is_sb_side_segment_mirror(RRGSB& cand, enum e_side side, size_t seg_id) const; /* check if all the routing segments of a side of candidate SB is a mirror of the current one */
bool is_sb_mirror(RRGSB& cand) const; /* check if the candidate SB is a mirror of the current one */
bool is_sb_mirrorable(RRGSB& cand) const; /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */
size_t get_hint_rotate_offset(RRGSB& cand) const; /* Determine an initial offset in rotating the candidate Switch Block to find a mirror matching*/
public: /* Cooridinator conversion */
public: /* Cooridinator conversion and output */
size_t get_sb_x() const; /* get the x coordinator of this switch block */
size_t get_sb_y() const; /* get the y coordinator of this switch block */
DeviceCoordinator get_sb_coordinator() const; /* Get the coordinator of the SB */
size_t get_cb_x(t_rr_type cb_type) const; /* get the x coordinator of this X/Y-direction block */
size_t get_cb_y(t_rr_type cb_type) const; /* get the y coordinator of this X/Y-direction block */
DeviceCoordinator get_cb_coordinator(t_rr_type cb_type) const; /* Get the coordinator of the X/Y-direction CB */
DeviceCoordinator get_side_block_coordinator(enum e_side side) const;
public: /* Verilog writer */
char* gen_verilog_module_name() const;
char* gen_verilog_instance_name() const;
char* gen_verilog_side_module_name(enum e_side side, size_t seg_id) const;
char* gen_verilog_side_instance_name(enum e_side side, size_t seg_id) const;
const char* gen_sb_verilog_module_name() const;
const char* gen_sb_verilog_instance_name() const;
const char* gen_sb_verilog_side_module_name(enum e_side side, size_t seg_id) const;
const char* gen_sb_verilog_side_instance_name(enum e_side side, size_t seg_id) const;
const char* gen_cb_verilog_module_name(t_rr_type cb_type) const;
const char* gen_cb_verilog_instance_name(t_rr_type cb_type) const;
public: /* Mutators */
void set(const RRGSB& src); /* get a copy from a source */
void set_coordinator(size_t x, size_t y);
@ -181,9 +205,12 @@ class RRGSB {
void add_chan_node(enum e_side node_side, RRChan& rr_chan, std::vector<enum PORTS> rr_chan_dir); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
void add_ipin_node(t_rr_node* node, enum e_side node_side, enum e_side grid_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
void add_opin_node(t_rr_node* node, enum e_side node_side, enum e_side grid_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
void set_num_reserved_conf_bits(size_t num_reserved_conf_bits);
void set_conf_bits_lsb(size_t conf_bits_lsb);
void set_conf_bits_msb(size_t conf_bits_msb);
void set_sb_num_reserved_conf_bits(size_t num_reserved_conf_bits);
void set_sb_conf_bits_lsb(size_t conf_bits_lsb);
void set_sb_conf_bits_msb(size_t conf_bits_msb);
void set_cb_num_reserved_conf_bits(t_rr_type cb_type, size_t num_reserved_conf_bits);
void set_cb_conf_bits_lsb(t_rr_type cb_type, size_t conf_bits_lsb);
void set_cb_conf_bits_msb(t_rr_type cb_type, size_t conf_bits_msb);
void rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset); /* rotate all the channel nodes by a given offset */
void counter_rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset); /* rotate all the channel nodes by a given offset */
void rotate_side_chan_node(enum e_side side, size_t offset); /* rotate all the channel nodes by a given offset */
@ -206,27 +233,33 @@ class RRGSB {
private: /* Internal Mutators */
void mirror_side_chan_node_direction(enum e_side side); /* Mirror the node direction and port direction of routing track nodes on a side */
private: /* internal functions */
bool is_node_mirror (RRGSB& cand, enum e_side node_side, size_t track_id) const;
bool is_sb_node_mirror (RRGSB& cand, enum e_side node_side, size_t track_id) const;
size_t get_track_id_first_short_connection(enum e_side node_side) const;
bool validate_num_sides() const;
bool validate_side(enum e_side side) const;
bool validate_track_id(enum e_side side, size_t track_id) const;
bool validate_opin_node_id(enum e_side side, size_t node_id) const;
bool validate_ipin_node_id(enum e_side side, size_t node_id) const;
bool validate_num_reserved_conf_bits() const;
bool validate_num_conf_bits() const;
bool validate_cb_type(t_rr_type cb_type) const;
private: /* Internal Data */
/* Coordinator */
DeviceCoordinator coordinator_;
/* Routing channel data */
std::vector<RRChan> chan_node_;
std::vector< std::vector<enum PORTS> > chan_node_direction_;
/* Logic Block Inputs data */
std::vector< std::vector<t_rr_node*> > ipin_node_;
std::vector< std::vector<enum e_side> > ipin_node_grid_side_;
/* Logic Block Outputs data */
std::vector< std::vector<t_rr_node*> > opin_node_;
std::vector< std::vector<enum e_side> > opin_node_grid_side_;
size_t reserved_conf_bits_lsb_;
size_t reserved_conf_bits_msb_;
size_t conf_bits_lsb_; /* Least Significant Bit (LSB) of configuration port*/
size_t conf_bits_msb_; /* Most Significant Bit (MSB) of configuration port*/
/* Configuration bits */
ConfPorts sb_conf_port_;
ConfPorts cbx_conf_port_;
ConfPorts cby_conf_port_;
};
/* Object Device Routing Resource Switch Block
@ -240,9 +273,9 @@ class RRGSB {
class DeviceRRGSB {
public: /* Contructors */
public: /* Accessors */
DeviceCoordinator get_switch_block_range() const; /* get the max coordinator of the switch block array */
RRGSB get_switch_block(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */
RRGSB get_switch_block(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */
DeviceCoordinator get_gsb_range() const; /* get the max coordinator of the switch block array */
RRGSB get_gsb(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */
RRGSB get_gsb(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */
size_t get_num_unique_module(enum e_side side, size_t seg_index) const; /* get the number of unique mirrors of switch blocks */
size_t get_num_unique_mirror() const; /* get the number of unique mirrors of switch blocks */
size_t get_num_rotatable_mirror() const; /* get the number of rotatable mirrors of switch blocks */

55
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.cpp Normal file
View File

@ -0,0 +1,55 @@
/***********************************/
/* SPICE Modeling for VPR */
/* Xifan TANG, EPFL/LSI */
/***********************************/
#include <string.h>
#include "rr_blocks_naming.h"
char* convert_cb_type_to_string(t_rr_type chan_type) {
switch(chan_type) {
case CHANX:
return "cbx";
break;
case CHANY:
return "cby";
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of channel!\n",
__FILE__, __LINE__);
exit(1);
}
}
char* convert_chan_type_to_string(t_rr_type chan_type) {
switch(chan_type) {
case CHANX:
return "chanx";
break;
case CHANY:
return "chany";
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Invalid type of channel!\n",
__FILE__, __LINE__);
exit(1);
}
}
char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction) {
switch(chan_rr_node_direction) {
case IN_PORT:
return "in";
break;
case OUT_PORT:
return "out";
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of port!\n", __FILE__, __LINE__);
exit(1);
}
}

14
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.h Normal file
View File

@ -0,0 +1,14 @@
#ifndef RR_BLOCKS_NAMING
#define RR_BLOCKS_NAMING
#include "vpr_types.h"
char* convert_chan_type_to_string(t_rr_type chan_type);
char* convert_cb_type_to_string(t_rr_type chan_type);
char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction);
#endif

16
vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.cpp
View File

@ -6,14 +6,14 @@
#include <assert.h>
#include "rr_blocks.h"
#include "write_rr_blocks.h"
#include "rr_blocks_naming.h"
#include "fpga_x2p_utils.h"
#include "write_rr_blocks.h"
void write_rr_switch_block_to_xml(std::string fname_prefix, RRGSB& rr_sb) {
/* Prepare file name */
std::string fname(fname_prefix);
fname += rr_sb.gen_verilog_module_name();
fname += rr_sb.gen_sb_verilog_module_name();
fname += ".xml";
vpr_printf(TIO_MESSAGE_INFO, "Output SB XML: %s\r", fname.c_str());
@ -24,7 +24,7 @@ void write_rr_switch_block_to_xml(std::string fname_prefix, RRGSB& rr_sb) {
fp.open(fname, std::fstream::out | std::fstream::trunc);
/* Output location of the Switch Block */
fp << "<rr_sb x=\"" << rr_sb.get_x() << "\" y=\"" << rr_sb.get_y() << "\""
fp << "<rr_sb x=\"" << rr_sb.get_sb_x() << "\" y=\"" << rr_sb.get_sb_y() << "\""
<< " num_sides=\"" << rr_sb.get_num_sides() << "\">" << std::endl;
/* Output each side */
@ -45,9 +45,9 @@ void write_rr_switch_block_to_xml(std::string fname_prefix, RRGSB& rr_sb) {
size_t src_segment_id = rr_sb.get_chan_node_segment(side_manager.get_side(), inode);
/* Check if this node is directly connected to the node on the opposite side */
if (true == rr_sb.is_node_imply_short_connection(cur_rr_node)) {
if (true == rr_sb.is_sb_node_imply_short_connection(cur_rr_node)) {
/* Double check if the interc lies inside a channel wire, that is interc between segments */
assert(true == rr_sb.is_node_exist_opposite_side(cur_rr_node, side_manager.get_side()));
assert(true == rr_sb.is_sb_node_exist_opposite_side(cur_rr_node, side_manager.get_side()));
num_drive_rr_nodes = 0;
drive_rr_nodes = NULL;
} else {
@ -124,12 +124,12 @@ void write_device_rr_gsb_to_xml(char* sb_xml_dir,
fname_prefix += '/';
}
DeviceCoordinator sb_range = LL_device_rr_gsb.get_switch_block_range();
DeviceCoordinator sb_range = LL_device_rr_gsb.get_gsb_range();
/* For each switch block, an XML file will be outputted */
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = LL_device_rr_gsb.get_switch_block(ix, iy);
RRGSB rr_sb = LL_device_rr_gsb.get_gsb(ix, iy);
write_rr_switch_block_to_xml(fname_prefix, rr_sb);
}
}

10
vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c
View File

@ -93,7 +93,7 @@ void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp,
/* Print the encoding in SPICE netlist for debugging */
fprintf(fp, "***** Switch Block [%lu][%lu] *****\n",
rr_sb.get_x(), rr_sb.get_y());
rr_sb.get_sb_x(), rr_sb.get_sb_y());
fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n",
verilog_model->cnt, mux_level, path_id);
fprintf(fp, "*****");
@ -228,9 +228,9 @@ void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp,
/* Determine if the interc lies inside a channel wire, that is interc between segments */
/* Check each num_drive_rr_nodes, see if they appear in the cur_sb_info */
if (true == rr_sb.is_node_imply_short_connection(cur_rr_node)) {
if (true == rr_sb.is_sb_node_imply_short_connection(cur_rr_node)) {
/* Double check if the interc lies inside a channel wire, that is interc between segments */
assert(true == rr_sb.is_node_exist_opposite_side(cur_rr_node, chan_side));
assert(true == rr_sb.is_sb_node_exist_opposite_side(cur_rr_node, chan_side));
num_drive_rr_nodes = 0;
drive_rr_nodes = NULL;
} else {
@ -675,10 +675,10 @@ void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log
/* Switch Boxes*/
vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Switch blocks...\n");
if (TRUE == compact_routing_hierarchy) {
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
fpga_spice_generate_bitstream_routing_switch_box_subckt(fp,
rr_sb, cur_sram_orgz_info);
}

34
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -761,14 +761,14 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
/* Comment lines */
fprintf(fp, "//----- BEGIN call module Switch blocks [%lu][%lu] -----\n",
rr_sb.get_x(), rr_sb.get_y());
rr_sb.get_sb_x(), rr_sb.get_sb_y());
/* Print module*/
/* If we have an mirror SB, we should the module name of the mirror !!! */
DeviceCoordinator coordinator = rr_sb.get_coordinator();
DeviceCoordinator coordinator = rr_sb.get_sb_coordinator();
RRGSB unique_mirror = device_rr_gsb.get_unique_mirror(coordinator);
fprintf(fp, "%s ", unique_mirror.gen_verilog_module_name());
fprintf(fp, "%s ", rr_sb.gen_verilog_instance_name());
fprintf(fp, "%s ", unique_mirror.gen_sb_verilog_module_name());
fprintf(fp, "%s ", rr_sb.gen_sb_verilog_instance_name());
fprintf(fp, "(");
fprintf(fp, "\n");
@ -781,7 +781,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
Side side_manager(side);
DeviceCoordinator chan_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side());
fprintf(fp, "//----- %s side channel ports-----\n", convert_side_index_to_string(side));
fprintf(fp, "//----- %s side channel ports-----\n", side_manager.to_string());
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {
fprintf(fp, "%s,\n",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
@ -806,31 +806,31 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
/* output of each configuration bit */
/* Reserved sram ports */
fprintf(fp, "//----- Reserved SRAM ports-----\n");
if (0 < (rr_sb.get_num_reserved_conf_bits())) {
if (0 < (rr_sb.get_sb_num_reserved_conf_bits())) {
dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_reserved_conf_bits_lsb(),
rr_sb.get_reserved_conf_bits_msb(),
rr_sb.get_sb_reserved_conf_bits_lsb(),
rr_sb.get_sb_reserved_conf_bits_msb(),
VERILOG_PORT_CONKT);
fprintf(fp, ",\n");
}
/* Normal sram ports */
if (0 < rr_sb.get_num_conf_bits()) {
if (0 < rr_sb.get_sb_num_conf_bits()) {
fprintf(fp, "//----- Regular SRAM ports-----\n");
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
rr_sb.get_conf_bits_lsb(),
rr_sb.get_conf_bits_msb(),
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
VERILOG_PORT_CONKT);
}
/* Dump ports only visible during formal verification*/
if (0 < rr_sb.get_num_conf_bits()) {
if (0 < rr_sb.get_sb_num_conf_bits()) {
fprintf(fp, "\n");
fprintf(fp, "//----- SRAM ports for formal verification -----\n");
fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
fprintf(fp, ",\n");
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_conf_bits_lsb(),
rr_sb.get_conf_bits_msb(),
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
VERILOG_PORT_CONKT);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
@ -840,7 +840,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
/* Comment lines */
fprintf(fp,
"//----- END call module Switch blocks [%lu][%lu] -----\n\n",
rr_sb.get_x(), rr_sb.get_y());
rr_sb.get_sb_x(), rr_sb.get_sb_y());
/* Free */
@ -850,7 +850,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
static
void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
/* Check the file handler*/
if (NULL == fp) {
@ -861,7 +861,7 @@ void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_i
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, rr_sb);
}
}

110
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c
View File

@ -264,7 +264,7 @@ void verilog_generate_one_report_timing_within_sb(FILE* fp,
/* output instance name */
fprintf(fp, "%s/",
rr_sb.gen_verilog_instance_name());
rr_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_routing_pin(fp, rr_sb, src_rr_node);
@ -272,7 +272,7 @@ void verilog_generate_one_report_timing_within_sb(FILE* fp,
/* output instance name */
fprintf(fp, "%s/",
rr_sb.gen_verilog_instance_name());
rr_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_chan_pin(fp, rr_sb, des_rr_node, OUT_PORT);
@ -390,7 +390,7 @@ void verilog_generate_one_report_timing_sb_to_cb(FILE* fp,
fprintf(fp, "report_timing -from ");
/* output instance name */
fprintf(fp, "%s/",
src_sb.gen_verilog_instance_name());
src_sb.gen_sb_verilog_instance_name());
/* output pin name */
dump_verilog_one_sb_chan_pin(fp, src_sb,
src_rr_node, OUT_PORT);
@ -433,7 +433,7 @@ void verilog_generate_one_report_timing_sb_to_sb(FILE* fp,
/* output instance name */
fprintf(fp, "%s/",
src_sb.gen_verilog_instance_name());
src_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_chan_pin(fp, src_sb, src_rr_node, OUT_PORT);
@ -441,7 +441,7 @@ void verilog_generate_one_report_timing_sb_to_sb(FILE* fp,
/* output instance name */
fprintf(fp, "%s/",
des_sb.gen_verilog_instance_name());
des_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_chan_pin(fp, des_sb, des_rr_node, IN_PORT);
@ -719,7 +719,7 @@ void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp,
case CHANY:
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
verilog_generate_one_report_timing_sb_to_sb(fp, src_sb, src_rr_node,
next_sb, src_rr_node);
break;
@ -947,9 +947,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
case CHANY:
/* Get the coordinate of ending CB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator);
end_sb_x = next_sb.get_x();
end_sb_y = next_sb.get_y();
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
end_sb_x = next_sb.get_sb_x();
end_sb_y = next_sb.get_sb_y();
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n",
@ -958,15 +958,15 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
}
/* Get the base coordinate of src_sb */
cur_sb_x = src_sb.get_x();
cur_sb_y = src_sb.get_y();
cur_sb_x = src_sb.get_sb_x();
cur_sb_y = src_sb.get_sb_y();
/* 4 cases: */
if ((INC_DIRECTION == src_rr_node->direction)
&&(CHANX == src_rr_node->type)) {
/* Follow the graph above, go through X channel */
for (int ix = src_sb.get_x(); ix < end_sb_x; ix++) {
for (int ix = src_sb.get_sb_x(); ix < end_sb_x; ix++) {
DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y);
RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator);
RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator);
/* If this is the ending point, we add a ending segment */
if (ix == end_sb_x - 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
@ -978,7 +978,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
DeviceCoordinator end_sb_coordinator(ix + 1, cur_sb_y);
RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator);
RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator);
verilog_generate_report_timing_one_sb_thru_segments(fp,
begin_sb, src_rr_node,
end_sb, src_rr_node,
@ -987,9 +987,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
} else if ((INC_DIRECTION == src_rr_node->direction)
&&(CHANY == src_rr_node->type)) {
/* Follow the graph above, go through Y channel */
for (int iy = src_sb.get_y(); iy < end_sb_y; iy++) {
for (int iy = src_sb.get_sb_y(); iy < end_sb_y; iy++) {
DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy);
RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator);
RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator);
/* If this is the ending point, we add a ending segment */
if (iy == end_sb_y - 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
@ -1000,7 +1000,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
DeviceCoordinator end_sb_coordinator(cur_sb_x, iy + 1);
RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator);
RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator);
verilog_generate_report_timing_one_sb_thru_segments(fp,
begin_sb, src_rr_node,
end_sb, src_rr_node,
@ -1009,9 +1009,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
} else if ((DEC_DIRECTION == src_rr_node->direction)
&&(CHANX == src_rr_node->type)) {
/* Follow the graph above, go through X channel */
for (int ix = src_sb.get_x() - 1; ix > end_sb_x; ix--) {
for (int ix = src_sb.get_sb_x() - 1; ix > end_sb_x; ix--) {
DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y);
RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator);
RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator);
/* If this is the ending point, we add a ending segment */
if (ix == end_sb_x + 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
@ -1022,7 +1022,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
DeviceCoordinator end_sb_coordinator(ix - 1, cur_sb_y);
RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator);
RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator);
verilog_generate_report_timing_one_sb_thru_segments(fp,
begin_sb, src_rr_node,
end_sb, src_rr_node,
@ -1031,9 +1031,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
} else if ((DEC_DIRECTION == src_rr_node->direction)
&&(CHANY == src_rr_node->type)) {
/* Follow the graph above, go through Y channel */
for (int iy = src_sb.get_y() - 1; iy > end_sb_y; iy--) {
for (int iy = src_sb.get_sb_y() - 1; iy > end_sb_y; iy--) {
DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy);
RRGSB begin_sb = device_rr_gsb.get_switch_block(begin_sb_coordinator);
RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator);
/* If this is the ending point, we add a ending segment */
if (iy == end_sb_y + 1) {
verilog_generate_report_timing_one_sb_ending_segments(fp,
@ -1044,7 +1044,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
}
/* Report timing for the downstream segements, from a SB output to an adjacent CB input */
DeviceCoordinator end_sb_coordinator(cur_sb_x, iy - 1);
RRGSB end_sb = device_rr_gsb.get_switch_block(end_sb_coordinator);
RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator);
verilog_generate_report_timing_one_sb_thru_segments(fp,
begin_sb, src_rr_node,
end_sb, src_rr_node,
@ -1432,9 +1432,9 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
case CHANY:
/* Get the coordinate of ending CB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator);
end_sb_x = next_sb.get_x();
end_sb_y = next_sb.get_y();
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
end_sb_x = next_sb.get_sb_x();
end_sb_y = next_sb.get_sb_y();
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n",
@ -1443,83 +1443,83 @@ void dump_verilog_sb_through_routing_pins(FILE* fp,
}
/* Get the base coordinate of src_sb */
cur_sb_x = src_rr_sb.get_x();
cur_sb_y = src_rr_sb.get_y();
cur_sb_x = src_rr_sb.get_sb_x();
cur_sb_y = src_rr_sb.get_sb_y();
/* 4 cases: */
if ((INC_DIRECTION == src_rr_node->direction)
&&(CHANX == src_rr_node->type)) {
/* Follow the graph above, go through X channel */
for (size_t ix = src_rr_sb.get_x() + 1; ix < end_sb_x; ++ix) {
for (size_t ix = src_rr_sb.get_sb_x() + 1; ix < end_sb_x; ++ix) {
/* Print an IN_PORT*/
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(ix, cur_sb_y);
RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
/* Print an OUT_PORT*/
fprintf(fp, " ");
/* output instance name */
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, OUT_PORT);
}
} else if ((INC_DIRECTION == src_rr_node->direction)
&&(CHANY == src_rr_node->type)) {
/* Follow the graph above, go through Y channel */
for (size_t iy = src_rr_sb.get_y() + 1; iy < end_sb_y; ++iy) {
for (size_t iy = src_rr_sb.get_sb_y() + 1; iy < end_sb_y; ++iy) {
/* Print an IN_PORT*/
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(cur_sb_x, iy);
RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
/* Print an OUT_PORT*/
fprintf(fp, " ");
/* output instance name */
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, OUT_PORT);
}
} else if ((DEC_DIRECTION == src_rr_node->direction)
&&(CHANX == src_rr_node->type)) {
/* Follow the graph above, go through X channel */
for (size_t ix = src_rr_sb.get_x() - 1; ix > end_sb_x; --ix) {
for (size_t ix = src_rr_sb.get_sb_x() - 1; ix > end_sb_x; --ix) {
/* Print an IN_PORT*/
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(ix, cur_sb_y);
RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
/* Print an OUT_PORT*/
fprintf(fp, " ");
/* output instance name */
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, OUT_PORT);
}
} else if ((DEC_DIRECTION == src_rr_node->direction)
&&(CHANY == src_rr_node->type)) {
/* Follow the graph above, go through Y channel */
for (size_t iy = src_rr_sb.get_y() - 1; iy > end_sb_y; --iy) {
for (size_t iy = src_rr_sb.get_sb_y() - 1; iy > end_sb_y; --iy) {
/* Print an IN_PORT*/
fprintf(fp, " ");
/* output instance name */
DeviceCoordinator inter_sb_coordinator(cur_sb_x, iy);
RRGSB inter_sb = device_rr_gsb.get_switch_block(inter_sb_coordinator);
RRGSB inter_sb = device_rr_gsb.get_gsb(inter_sb_coordinator);
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, IN_PORT);
/* Print an OUT_PORT*/
fprintf(fp, " ");
/* output instance name */
fprintf(fp, "%s/",
inter_sb.gen_verilog_instance_name());
inter_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, inter_sb, src_rr_node, OUT_PORT);
}
}
@ -1805,7 +1805,7 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
path_cnt);
fprintf(fp, "report_timing -from ");
/* output instance name */
fprintf(fp, "%s/", rr_sb.gen_verilog_instance_name());
fprintf(fp, "%s/", rr_sb.gen_sb_verilog_instance_name());
/* output pin name */
dump_verilog_one_sb_routing_pin(fp, rr_sb,
wire_rr_node->drive_rr_nodes[iedge]);
@ -1831,10 +1831,10 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
case CHANY:
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(wire_rr_node, &(LL_rr_node[inode]));
next_sb = device_rr_gsb.get_switch_block(next_sb_coordinator);
next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
/* This will not be the longest path unless the cb is close to the ending SB */
if ((TRUE == sdc_opts.longest_path_only)
&& ((next_sb.get_x() != (size_t)x_end) || (next_sb.get_y() != (size_t)y_end))) {
&& ((next_sb.get_sb_x() != (size_t)x_end) || (next_sb.get_sb_y() != (size_t)y_end))) {
continue;
}
if (TRUE == sb_dumped) {
@ -1850,14 +1850,14 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
fprintf(fp, "report_timing -from ");
/* output instance name */
fprintf(fp, "%s/",
rr_sb.gen_verilog_instance_name());
rr_sb.gen_sb_verilog_instance_name());
/* output pin name */
dump_verilog_one_sb_routing_pin(fp, rr_sb,
wire_rr_node->drive_rr_nodes[iedge]);
fprintf(fp, " -to ");
/* output instance name */
fprintf(fp, "%s/",
next_sb.gen_verilog_instance_name());
next_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_routing_pin(fp, next_sb,
wire_rr_node);
@ -2055,10 +2055,10 @@ void verilog_generate_routing_wires_report_timing(FILE* fp,
}
if (TRUE == sdc_opts.compact_routing_hierarchy) {
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
for (size_t side = 0; side < rr_sb.get_num_sides(); side++) {
Side side_manager(side);
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {
@ -2066,7 +2066,7 @@ void verilog_generate_routing_wires_report_timing(FILE* fp,
||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type));
/* We only care the output port and it should indicate a SB mux */
if ( (OUT_PORT != rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))
|| (true == rr_sb.is_node_imply_short_connection(rr_sb.get_chan_node(side_manager.get_side(), itrack)))) {
|| (true == rr_sb.is_sb_node_imply_short_connection(rr_sb.get_chan_node(side_manager.get_side(), itrack)))) {
continue;
}
/* Bypass if we have only 1 driving node */
@ -2386,10 +2386,10 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts,
"Generating TCL script to report timing for routing wires\n");
/* We start from a SB[x][y] */
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
Side side_manager(side);
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {
@ -2397,7 +2397,7 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts,
||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type));
/* We only care the output port and it should indicate a SB mux */
if ( (OUT_PORT != rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))
|| (false != rr_sb.is_node_imply_short_connection(rr_sb.get_chan_node(side_manager.get_side(), itrack)))) {
|| (false != rr_sb.is_sb_node_imply_short_connection(rr_sb.get_chan_node(side_manager.get_side(), itrack)))) {
continue;
}
/* Bypass if we have only 1 driving node */

110
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -725,7 +725,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp,
char* des_chan_port_name = "out";
fprintf(fp, "//----- Short connection %s[%lu][%lu]_%s[%d] -----\n",
chan_name, rr_sb.get_coordinator().get_x(), rr_sb.get_coordinator().get_y(), des_chan_port_name, cur_rr_node->ptc_num);
chan_name, rr_sb.get_sb_coordinator().get_x(), rr_sb.get_sb_coordinator().get_y(), des_chan_port_name, cur_rr_node->ptc_num);
fprintf(fp, "assign ");
/* Output port */
@ -738,7 +738,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp,
} else {
Side side_manager(chan_side);
/* drive_rr_node = &(rr_node[cur_rr_node->prev_node]); */
assert(1 == rr_node_drive_switch_box(drive_rr_node, cur_rr_node, rr_sb.get_coordinator().get_x(), rr_sb.get_coordinator().get_y(), side_manager.get_side()));
assert(1 == rr_node_drive_switch_box(drive_rr_node, cur_rr_node, rr_sb.get_sb_coordinator().get_x(), rr_sb.get_sb_coordinator().get_y(), side_manager.get_side()));
}
int grid_x = drive_rr_node->xlow;
@ -1177,7 +1177,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
+ strlen(my_itoa(verilog_model->cnt)) + 5));
sprintf(name_mux, "/%s_size%d_%d_/in", verilog_model->prefix, mux_size, verilog_model->cnt);
char* path_hierarchy = rr_sb.gen_verilog_instance_name();
const char* path_hierarchy = rr_sb.gen_sb_verilog_instance_name();
cur_rr_node->name_mux = my_strcat(path_hierarchy, name_mux);
/* Input ports*/
@ -1425,7 +1425,7 @@ size_t count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz
}
/* Determine if the interc lies inside a channel wire, that is interc between segments */
if (true == rr_sb.is_node_exist_opposite_side(cur_rr_node, chan_side)) {
if (true == rr_sb.is_sb_node_exist_opposite_side(cur_rr_node, chan_side)) {
num_drive_rr_nodes = 0;
} else {
num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes;
@ -1499,7 +1499,7 @@ size_t count_verilog_switch_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_
}
/* Determine if the interc lies inside a channel wire, that is interc between segments */
if (1 == rr_sb.is_node_exist_opposite_side(cur_rr_node, chan_side)) {
if (1 == rr_sb.is_sb_node_exist_opposite_side(cur_rr_node, chan_side)) {
num_drive_rr_nodes = 0;
} else {
num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes;
@ -1593,9 +1593,9 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
/* Determine if the interc lies inside a channel wire, that is interc between segments */
/* Check each num_drive_rr_nodes, see if they appear in the cur_sb_info */
if (true == rr_sb.is_node_imply_short_connection(cur_rr_node)) {
if (true == rr_sb.is_sb_node_imply_short_connection(cur_rr_node)) {
/* Double check if the interc lies inside a channel wire, that is interc between segments */
assert(true == rr_sb.is_node_exist_opposite_side(cur_rr_node, chan_side));
assert(true == rr_sb.is_sb_node_exist_opposite_side(cur_rr_node, chan_side));
num_drive_rr_nodes = 0;
drive_rr_nodes = NULL;
} else {
@ -1798,7 +1798,7 @@ void update_routing_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_num_bl, &cur_num_wl);
/* Record the index: TODO: clean this mess, move to FPGA_X2P_SETUP !!!*/
DeviceCoordinator sb_coordinator(rr_sb.get_x(), rr_sb.get_y());
DeviceCoordinator sb_coordinator(rr_sb.get_sb_x(), rr_sb.get_sb_y());
/* Count the number of configuration bits to be consumed by this Switch block */
int num_conf_bits = count_verilog_switch_box_conf_bits(cur_sram_orgz_info, rr_sb);
@ -1882,7 +1882,7 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp,
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n",
__FILE__, __LINE__, rr_sb.get_x(), rr_sb.get_y(), itrack);
__FILE__, __LINE__, rr_sb.get_sb_x(), rr_sb.get_sb_y(), itrack);
exit(1);
}
}
@ -1983,9 +1983,9 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
/* Comment lines */
fprintf(fp,
"//----- Verilog Module of Unique Switch Box[%lu][%lu] at Side %s, Segment id: %lu -----\n",
rr_sb.get_x(), rr_sb.get_y(), side_manager.to_string(), seg_id);
rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.to_string(), seg_id);
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_sb.gen_verilog_side_module_name(side, seg_id));
fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_side_module_name(side, seg_id));
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
fprintf(fp, ",\n");
@ -2051,7 +2051,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
/* Comment lines */
fprintf(fp,
"//----- END Verilog Module of Switch Box[%lu][%lu] Side %s -----\n\n",
rr_sb.get_x(), rr_sb.get_y(), side_manager.to_string());
rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.to_string());
/* Check */
assert(esti_sram_cnt == get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info));
@ -2102,21 +2102,21 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
int num_reserved_conf_bits = count_verilog_switch_box_reserved_conf_bits(cur_sram_orgz_info, rr_sb);
/* Estimate the sram_verilog_model->cnt */
int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
rr_sb.set_num_reserved_conf_bits(num_reserved_conf_bits);
rr_sb.set_conf_bits_lsb(cur_num_sram);
rr_sb.set_conf_bits_msb(cur_num_sram + num_conf_bits - 1);
rr_sb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits);
rr_sb.set_sb_conf_bits_lsb(cur_num_sram);
rr_sb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1);
/* Create file handler */
fp = verilog_create_one_subckt_file(subckt_dir, "Unique Switch Block ",
sb_verilog_file_name_prefix, rr_sb.get_x(), rr_sb.get_y(), &fname);
sb_verilog_file_name_prefix, rr_sb.get_sb_x(), rr_sb.get_sb_y(), &fname);
/* Print preprocessing flags */
verilog_include_defines_preproc_file(fp, verilog_dir);
/* Comment lines */
fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_sb.get_x(), rr_sb.get_y());
fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_sb.get_sb_x(), rr_sb.get_sb_y());
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_sb.gen_verilog_module_name());
fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_module_name());
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
fprintf(fp, ",\n");
@ -2145,7 +2145,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n",
__FILE__, __LINE__, rr_sb.get_x(), rr_sb.get_y(), itrack);
__FILE__, __LINE__, rr_sb.get_sb_x(), rr_sb.get_sb_y(), itrack);
exit(1);
}
}
@ -2166,29 +2166,29 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
/* output of each configuration bit */
/* Reserved sram ports */
fprintf(fp, "//----- Reserved SRAM Ports -----\n");
if (0 < rr_sb.get_num_reserved_conf_bits()) {
if (0 < rr_sb.get_sb_num_reserved_conf_bits()) {
dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_reserved_conf_bits_lsb(),
rr_sb.get_reserved_conf_bits_msb(),
rr_sb.get_sb_reserved_conf_bits_lsb(),
rr_sb.get_sb_reserved_conf_bits_msb(),
VERILOG_PORT_INPUT);
fprintf(fp, ",\n");
}
/* Normal sram ports */
fprintf(fp, "//----- Regular SRAM Ports -----\n");
dump_verilog_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_conf_bits_lsb(),
rr_sb.get_conf_bits_msb(),
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
VERILOG_PORT_INPUT);
/* Dump ports only visible during formal verification*/
if (0 < rr_sb.get_num_conf_bits()) {
if (0 < rr_sb.get_sb_num_conf_bits()) {
fprintf(fp, "\n");
fprintf(fp, "//----- SRAM Ports for formal verification -----\n");
fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
fprintf(fp, ",\n");
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_conf_bits_lsb(),
rr_sb.get_conf_bits_msb(),
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
VERILOG_PORT_OUTPUT);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
@ -2197,8 +2197,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
/* Local wires for memory configurations */
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
rr_sb.get_conf_bits_lsb(),
rr_sb.get_conf_bits_msb());
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb());
/* Call submodules */
int cur_sram_lsb = cur_num_sram;
@ -2227,13 +2227,13 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
int side_num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_sb, side_manager.get_side(), seg_ids[iseg]);
/* Cache the sram counter */
cur_sram_msb = cur_sram_lsb + side_num_conf_bits - 1;
cur_sram_msb = cur_sram_lsb + side_num_conf_bits - 1;
/* Instanciate the subckt*/
fprintf(fp,
"%s %s ( \n",
rr_sb.gen_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]),
rr_sb.gen_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg]));
rr_sb.gen_sb_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]),
rr_sb.gen_sb_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg]));
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
fprintf(fp, ",\n");
@ -2281,7 +2281,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
fprintf(fp, "endmodule\n");
/* Comment lines */
fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_sb.get_x(), rr_sb.get_y());
fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_sb.get_sb_x(), rr_sb.get_sb_y());
/* Close file handler */
fclose(fp);
@ -2344,21 +2344,21 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
/* Estimate the sram_verilog_model->cnt */
int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
int esti_sram_cnt = cur_num_sram + num_conf_bits;
rr_sb.set_num_reserved_conf_bits(num_reserved_conf_bits);
rr_sb.set_conf_bits_lsb(cur_num_sram);
rr_sb.set_conf_bits_msb(cur_num_sram + num_conf_bits - 1);
rr_sb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits);
rr_sb.set_sb_conf_bits_lsb(cur_num_sram);
rr_sb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1);
/* Create file handler */
fp = verilog_create_one_subckt_file(subckt_dir, "Unique Switch Block ",
sb_verilog_file_name_prefix, rr_sb.get_x(), rr_sb.get_y(), &fname);
sb_verilog_file_name_prefix, rr_sb.get_sb_x(), rr_sb.get_sb_y(), &fname);
/* Print preprocessing flags */
verilog_include_defines_preproc_file(fp, verilog_dir);
/* Comment lines */
fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_sb.get_x(), rr_sb.get_y());
fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_sb.get_sb_x(), rr_sb.get_sb_y());
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_sb.gen_verilog_module_name());
fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_module_name());
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
fprintf(fp, ",\n");
@ -2387,7 +2387,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n",
__FILE__, __LINE__, rr_sb.get_x(), rr_sb.get_y(), itrack);
__FILE__, __LINE__, rr_sb.get_sb_x(), rr_sb.get_sb_y(), itrack);
exit(1);
}
}
@ -2406,27 +2406,27 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
/* Put down configuration port */
/* output of each configuration bit */
/* Reserved sram ports */
dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_reserved_conf_bits_lsb(),
rr_sb.get_reserved_conf_bits_msb(),
VERILOG_PORT_INPUT);
if (0 < rr_sb.get_num_reserved_conf_bits()) {
if (0 < rr_sb.get_sb_num_reserved_conf_bits()) {
dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_sb_reserved_conf_bits_lsb(),
rr_sb.get_sb_reserved_conf_bits_msb(),
VERILOG_PORT_INPUT);
fprintf(fp, ",\n");
}
/* Normal sram ports */
dump_verilog_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_conf_bits_lsb(),
rr_sb.get_conf_bits_msb(),
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
VERILOG_PORT_INPUT);
/* Dump ports only visible during formal verification*/
if (0 < rr_sb.get_num_conf_bits()) {
if (0 < rr_sb.get_sb_num_conf_bits()) {
fprintf(fp, "\n");
fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
fprintf(fp, ",\n");
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_conf_bits_lsb(),
rr_sb.get_conf_bits_msb(),
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
VERILOG_PORT_OUTPUT);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
@ -2435,8 +2435,8 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
/* Local wires for memory configurations */
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
rr_sb.get_conf_bits_lsb(),
rr_sb.get_conf_bits_msb());
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb());
/* Put down all the multiplexers */
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
@ -2458,7 +2458,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
fprintf(fp, "endmodule\n");
/* Comment lines */
fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_sb.get_x(), rr_sb.get_y());
fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_sb.get_sb_x(), rr_sb.get_sb_y());
/* Check */
assert(esti_sram_cnt == get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info));
@ -3473,10 +3473,10 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
/* Restore sram_orgz_info to the base */
copy_sram_orgz_info (cur_sram_orgz_info, stamped_sram_orgz_info);
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
update_routing_switch_box_conf_bits(cur_sram_orgz_info, rr_sb);
}
}

12
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -1011,11 +1011,11 @@ void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp) {
exit(1);
}
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
/* Print comments */
fprintf(fp,
"########################################################\n");
@ -1167,11 +1167,11 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp) {
exit(1);
}
DeviceCoordinator sb_range = device_rr_gsb.get_switch_block_range();
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
/* We start from a SB[x][y] */
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
RRGSB rr_sb = device_rr_gsb.get_switch_block(ix, iy);
RRGSB rr_sb = device_rr_gsb.get_gsb(ix, iy);
/* Print comments */
fprintf(fp,
"##################################################\n");
@ -1191,7 +1191,7 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp) {
}
fprintf(fp, "set_disable_timing ");
fprintf(fp, "%s/",
rr_sb.gen_verilog_instance_name());
rr_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, rr_sb,
rr_sb.get_chan_node(side_manager.get_side(), itrack),
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack));
@ -1205,7 +1205,7 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp) {
}
fprintf(fp, "set_disable_timing ");
fprintf(fp, "%s/",
rr_sb.gen_verilog_instance_name());
rr_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_routing_pin(fp, rr_sb,
rr_sb.get_opin_node(side_manager.get_side(), inode));
fprintf(fp, "\n");

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c
View File

@ -398,7 +398,7 @@ DeviceCoordinator get_chan_node_ending_sb_coordinator(t_rr_node* src_rr_node,
}
DeviceCoordinator sb_coordinator(next_sb_x, next_sb_y);
RRGSB rr_sb = device_rr_gsb.get_switch_block(sb_coordinator);
RRGSB rr_sb = device_rr_gsb.get_gsb(sb_coordinator);
/* Double check if src_rr_node is in the list */
enum e_side side;
int index;
@ -569,7 +569,7 @@ void restore_disable_timing_one_sb_output(FILE* fp,
fprintf(fp, "reset_disable_timing ");
/* output instance name */
fprintf(fp, "%s/",
rr_sb.gen_verilog_instance_name());
rr_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, rr_sb, wire_rr_node, OUT_PORT);
fprintf(fp, "\n");
@ -621,7 +621,7 @@ void set_disable_timing_one_sb_output(FILE* fp,
fprintf(fp, "set_disable_timing ");
/* output instance name */
fprintf(fp, "%s/",
rr_sb.gen_verilog_instance_name());
rr_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_chan_pin(fp, rr_sb, wire_rr_node, OUT_PORT);
fprintf(fp, "\n");