ReadMe modifications to add the beginning of the FPGA-SPICE tutorial

Modifications on the addresses aswell and the different commands when they were not working.
To do still:
-create a script to change the addresses when needed
-continue the tutorial

README.md

@@ -12,10 +12,12 @@ There is a submodule in the repository so move to the OpenFPGA directory and clo
 
 `git submodule update`
 
-Go to the `VPR` dirctory and build the tool:
-`cd ./vpr7_rram/vpr/`
+Go to the `VPR` directory and build the tool:
+`cd ./vpr7_x2p/vpr/`
 `make `
 
+Note: if you are using macOS, the graphical interface might not be usable since it requires the X11 library. In this case, open the Makefile and change the line 10 "ENABLE_GRAPHICS = true" to false.
+
 VPR requires a minimum of one XML file that specifies the architecture of the FPGA, and one BLIF file that specifies the logic circuit to be put on the FPGA. 
 
 [//todo]: # (make sure the circuits are available)
@@ -29,4 +31,12 @@ To run VPR without the display, use the command `-nodisp`
 
 VPR creates a number of files in the same location as the BLIF file when it is run. The `place` file shows how the circuit was placed on the FPGA; the `route` file shows how the logic was routed on the FPGA; the `net` file shows the wiring.
 
+Now that we know that VPR is working, we can move on to FPGA-SPICE. 
 
+The first example we want to run is go.sh in the same folder as we already are.
+
+'./go.sh'
+
+By calling this script (if not modified), we call FPGA-SPICE on an architecture built on TSMC 40 nm node in typical conditions. By modifying the script, we can do different corners at the same time.
+
+This script creates the folder verily_test containing the bitstream and other informations on the circuit we implemented. 

abc_with_bb_support/Makefile

@@ -1,7 +1,7 @@
 
-CC   := gcc-4.9
-CXX  := g++-4.9
-LD   := g++-4.9
+CC   := gcc
+CXX  := g++
+LD   := g++
 CP   := cp
 
 PROG := abc

vpr7_x2p/vpr/go.sh

@@ -3,7 +3,7 @@
 
 # Pack, place, and route a heterogeneous FPGA
 # Packing uses the AAPack algorithm
-./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --spice_dir ./spice_test --spice_print_top_testbench --spice_print_grid_testbench --spice_print_cb_testbench --spice_print_sb_testbench --spice_print_lut_testbench --spice_print_hardlogic_testbench --spice_print_pb_mux_testbench --spice_print_cb_mux_testbench --spice_print_sb_mux_testbench --fpga_syn_verilog --fpga_syn_verilog_dir ./verilog_test
+./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test