Adds titles and WiP tags for new parts. Tutorials included

Added title and WiP tags for comprehension and also to see what is missing and what is going to happen in the near future in the documentation
2018-09-25 14:53:04 -06:00 · 2018-09-25 14:53:04 -06:00 · 16c0c4656e
parent 70d303dfb5
commit 16c0c4656e
10 changed files with 28 additions and 4 deletions
--- a/docs/source/arch_lang/index.rst
+++ b/docs/source/arch_lang/index.rst
@ -1,3 +1,6 @@
+Extended Architecture Description Language 
+====================================
+
 .. _arch_lang:
   Extended FPGA Architecture Description Language
 
--- a/docs/source/fpga_bitstream/command_line_usage.rst
+++ b/docs/source/fpga_bitstream/command_line_usage.rst
@ -1,2 +1,4 @@
 Command-line Options for FPGA Bitstream Generator
 =================================================
+
+**Under Construction**
--- a/docs/source/fpga_bitstream/file_organization.rst
+++ b/docs/source/fpga_bitstream/file_organization.rst
@ -1,2 +1,4 @@
 Bistream Output File Format
 ============================
+
+**Under Construction**
--- a/docs/source/fpga_verilog/command_line_usage.rst
+++ b/docs/source/fpga_verilog/command_line_usage.rst
@ -1,2 +1,4 @@
 Command-line Options for FPGA Bitstream Generator
 =================================================
+
+**Under Construction**
--- a/docs/source/fpga_verilog/file_organization.rst
+++ b/docs/source/fpga_verilog/file_organization.rst
@ -1,2 +1,4 @@
 Verilog Output File Format
 ============================
+
+**Under Construction**
--- a/docs/source/fpga_verilog/func_verify.rst
+++ b/docs/source/fpga_verilog/func_verify.rst
@ -1,2 +1,4 @@
 Perform Functionality Verification
 ==================================
+
+**Under Construction**
--- a/docs/source/fpga_verilog/sc_flow.rst
+++ b/docs/source/fpga_verilog/sc_flow.rst
@ -1,2 +1,4 @@
 From Verilog to Layout
 ======================
+
+**Under Construction**
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@ -26,10 +26,6 @@ For more information on the original FPGA architecture description language see

   arch_lang/index

-.. toctree::
-   :maxdepth: 2
-   :caption: OpenFPGA VPR Usage
-
 .. toctree::
   :caption: FPGA-SPICE: SPICE Auto-Generation

--- a/docs/source/tutorials/getting_started.rtf
+++ b/docs/source/tutorials/getting_started.rtf
@ -0,0 +1,11 @@
+{\rtf1\ansi\ansicpg1252\cocoartf1561\cocoasubrtf400
+{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
+{\colortbl;\red255\green255\blue255;}
+{\*\expandedcolortbl;;}
+\margl1440\margr1440\vieww10800\viewh8400\viewkind0
+\pard\tx566\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\pardirnatural\partightenfactor0
+
+\f0\fs24 \cf0 01 Getting Started\
+=================================================\
+\
+**Under Construction**}
--- a/docs/source/tutorials/index.rst
+++ b/docs/source/tutorials/index.rst
@ -3,6 +3,8 @@
 
 .. toctree::
   :maxdepth: 2
+
+   getting_started