diff --git a/docs/source/arch_lang/index.rst b/docs/source/arch_lang/index.rst
index 2cc864ced..db214b454 100644
--- a/docs/source/arch_lang/index.rst
+++ b/docs/source/arch_lang/index.rst
@@ -1,3 +1,6 @@
+Extended Architecture Description Language 
+====================================
+
 .. _arch_lang:
    Extended FPGA Architecture Description Language
  
diff --git a/docs/source/fpga_bitstream/command_line_usage.rst b/docs/source/fpga_bitstream/command_line_usage.rst
index c4b297d28..839ac7fa9 100644
--- a/docs/source/fpga_bitstream/command_line_usage.rst
+++ b/docs/source/fpga_bitstream/command_line_usage.rst
@@ -1,2 +1,4 @@
 Command-line Options for FPGA Bitstream Generator
 =================================================
+
+**Under Construction**
\ No newline at end of file
diff --git a/docs/source/fpga_bitstream/file_organization.rst b/docs/source/fpga_bitstream/file_organization.rst
index 5a538703e..a07f54a41 100644
--- a/docs/source/fpga_bitstream/file_organization.rst
+++ b/docs/source/fpga_bitstream/file_organization.rst
@@ -1,2 +1,4 @@
 Bistream Output File Format
 ============================
+
+**Under Construction**
\ No newline at end of file
diff --git a/docs/source/fpga_verilog/command_line_usage.rst b/docs/source/fpga_verilog/command_line_usage.rst
index c4b297d28..839ac7fa9 100644
--- a/docs/source/fpga_verilog/command_line_usage.rst
+++ b/docs/source/fpga_verilog/command_line_usage.rst
@@ -1,2 +1,4 @@
 Command-line Options for FPGA Bitstream Generator
 =================================================
+
+**Under Construction**
\ No newline at end of file
diff --git a/docs/source/fpga_verilog/file_organization.rst b/docs/source/fpga_verilog/file_organization.rst
index 2e4d912f3..bf2591e28 100644
--- a/docs/source/fpga_verilog/file_organization.rst
+++ b/docs/source/fpga_verilog/file_organization.rst
@@ -1,2 +1,4 @@
 Verilog Output File Format
 ============================
+
+**Under Construction**
\ No newline at end of file
diff --git a/docs/source/fpga_verilog/func_verify.rst b/docs/source/fpga_verilog/func_verify.rst
index 67b0c8808..174a9efff 100644
--- a/docs/source/fpga_verilog/func_verify.rst
+++ b/docs/source/fpga_verilog/func_verify.rst
@@ -1,2 +1,4 @@
 Perform Functionality Verification
 ==================================
+
+**Under Construction**
\ No newline at end of file
diff --git a/docs/source/fpga_verilog/sc_flow.rst b/docs/source/fpga_verilog/sc_flow.rst
index 04fc2f658..9a21f8744 100644
--- a/docs/source/fpga_verilog/sc_flow.rst
+++ b/docs/source/fpga_verilog/sc_flow.rst
@@ -1,2 +1,4 @@
 From Verilog to Layout
 ======================
+
+**Under Construction**
\ No newline at end of file
diff --git a/docs/source/index.rst b/docs/source/index.rst
index 7904c0fa6..68c5cf8a0 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -26,10 +26,6 @@ For more information on the original FPGA architecture description language see
 
    arch_lang/index
 
-.. toctree::
-   :maxdepth: 2
-   :caption: OpenFPGA VPR Usage
-
 .. toctree::
    :caption: FPGA-SPICE: SPICE Auto-Generation
 
diff --git a/docs/source/tutorials/getting_started.rtf b/docs/source/tutorials/getting_started.rtf
new file mode 100644
index 000000000..f094182ef
--- /dev/null
+++ b/docs/source/tutorials/getting_started.rtf
@@ -0,0 +1,11 @@
+{\rtf1\ansi\ansicpg1252\cocoartf1561\cocoasubrtf400
+{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
+{\colortbl;\red255\green255\blue255;}
+{\*\expandedcolortbl;;}
+\margl1440\margr1440\vieww10800\viewh8400\viewkind0
+\pard\tx566\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\pardirnatural\partightenfactor0
+
+\f0\fs24 \cf0 01 Getting Started\
+=================================================\
+\
+**Under Construction**}
\ No newline at end of file
diff --git a/docs/source/tutorials/index.rst b/docs/source/tutorials/index.rst
index 667328646..562a00bbb 100644
--- a/docs/source/tutorials/index.rst
+++ b/docs/source/tutorials/index.rst
@@ -3,6 +3,8 @@
  
 .. toctree::
    :maxdepth: 2
+
+   getting_started