add a section for picorv generation through the flow
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@ -3,7 +3,7 @@
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# Pack, place, and route a heterogeneous FPGA
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# Packing uses the AAPack algorithm
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echo "./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test --fpga_verilog_print_top_testbench"
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./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_go --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_go --fpga_verilog_print_top_testbench
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@ -175,6 +175,19 @@
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<port type="blb" prefix="blb" size="1" default_val="1" inv_circuit_model_name="INVTX1"/>
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<port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="sff" name="sc_ff" prefix="scff" spice_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="INVTX1"/>
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<output_buffer exist="on" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="pset" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="preset" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" size="2"/>
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<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/io.v">
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="INVTX1"/>
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@ -195,7 +208,7 @@
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<area grid_logic_tile_area="0"/>
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<sram area="6">
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<!--<verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>-->
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<verilog organization="scan-chain" circuit_model_name="static_dff" />
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<verilog organization="scan-chain" circuit_model_name="sc_ff" />
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<spice organization="standalone" circuit_model_name="sram6T" />
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</sram>
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<chan_width_distr>
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