diff --git a/vpr7_x2p/vpr/go.sh b/vpr7_x2p/vpr/go.sh
index 1eec39a78..b8d77c26e 100755
--- a/vpr7_x2p/vpr/go.sh
+++ b/vpr7_x2p/vpr/go.sh
@@ -3,7 +3,7 @@
 
 # Pack, place, and route a heterogeneous FPGA
 # Packing uses the AAPack algorithm
-echo "./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test --fpga_verilog_print_top_testbench"
+./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_go --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_go --fpga_verilog_print_top_testbench
 
 
 
diff --git a/vpr7_x2p/vpr/arch.xml b/vpr7_x2p/vpr/picorv/arch.xml
similarity index 94%
rename from vpr7_x2p/vpr/arch.xml
rename to vpr7_x2p/vpr/picorv/arch.xml
index c39197281..e2d3abe3d 100644
--- a/vpr7_x2p/vpr/arch.xml
+++ b/vpr7_x2p/vpr/picorv/arch.xml
@@ -175,6 +175,19 @@
         <port type="blb" prefix="blb" size="1" default_val="1" inv_circuit_model_name="INVTX1"/>
         <port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
       </circuit_model>
+
+      <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+      <circuit_model type="sff" name="sc_ff" prefix="scff" spice_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v">
+         <design_technology type="cmos"/>
+         <input_buffer exist="on" circuit_model_name="INVTX1"/>
+         <output_buffer exist="on" circuit_model_name="INVTX1"/>
+         <pass_gate_logic circuit_model_name="TGATE"/>
+         <port type="input" prefix="D" size="1"/>
+         <port type="input" prefix="pset" size="1" is_global="true" default_val="0" is_set="true"/>
+         <port type="input" prefix="preset" size="1" is_global="true" default_val="0" is_reset="true"/>
+         <port type="output" prefix="Q" size="2"/>
+         <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+      </circuit_model>
       <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/io.v">
         <design_technology type="cmos"/>
         <input_buffer exist="on" circuit_model_name="INVTX1"/>
@@ -195,7 +208,7 @@
     <area grid_logic_tile_area="0"/> 
     <sram area="6">
       <!--<verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>-->
-      <verilog organization="scan-chain" circuit_model_name="static_dff" />
+      <verilog organization="scan-chain" circuit_model_name="sc_ff" />
 	  <spice organization="standalone" circuit_model_name="sram6T" />
     </sram>
     <chan_width_distr>
diff --git a/vpr7_x2p/vpr/picorv_ace.act b/vpr7_x2p/vpr/picorv/picorv_ace.act
similarity index 100%
rename from vpr7_x2p/vpr/picorv_ace.act
rename to vpr7_x2p/vpr/picorv/picorv_ace.act
diff --git a/vpr7_x2p/vpr/picorv_ace.blif b/vpr7_x2p/vpr/picorv/picorv_ace.blif
similarity index 100%
rename from vpr7_x2p/vpr/picorv_ace.blif
rename to vpr7_x2p/vpr/picorv/picorv_ace.blif