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bug fixing in SDC generator

This commit is contained in:
tangxifan 2019-07-11 17:10:08 -06:00
parent 1848771e54
commit 9c203ca4d2
2 changed files with 32 additions and 3 deletions
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22
fpga_flow/scripts/fpga_flow.pl
View File

@ -761,6 +761,8 @@ sub run_abc_fpgamap($ $ $)
# Run ABC by FPGA-oriented synthesis
sub run_abc_bb_fpgamap($ $ $) {
my ($bm,$blif_out,$log) = @_;
my ($cmd_log) = ($log."cmd");
# Get ABC path
my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_with_bb_support_path}->{val});
my ($lut_num) = $opt_ptr->{K_val};
@ -777,9 +779,26 @@ sub run_abc_bb_fpgamap($ $ $) {
$dump_verilog = "write_verilog $bm.v";
}
#
# Create a local copy for the commands
#
my ($ABC_CMD_FH) = (FileHandle->new);
if ($ABC_CMD_FH->open("> $cmd_log")) {
print "INFO: auto generating cmds for ABC ($cmd_log) ...\n";
} else {
die "ERROR: fail to auto generating cmds for ABC ($cmd_log) ...\n";
}
# Output the standard format (refer to VTR_flow script)
print $ABC_CMD_FH "read $bm; resyn; resyn2; $fpga_synthesis_method -K $lut_num; $abc_seq_optimize sweep; write_hie $bm $blif_out; $dump_verilog; quit;\n";
close($ABC_CMD_FH);
# Go to ABC directory and run FPGA with commands
print "Entering $abc_dir\n";
chdir $abc_dir;
# Run FPGA ABC
system("./$abc_name -c \"read $bm; resyn; resyn2; $fpga_synthesis_method -K $lut_num; $abc_seq_optimize sweep; write_hie $bm $blif_out; $dump_verilog; quit;\" > $log");
system("./$abc_name -F $cmd_log > $log");
if (!(-e $blif_out)) {
die "ERROR: Fail ABC_with_bb_support for benchmark $bm.\n";
@ -789,6 +808,7 @@ sub run_abc_bb_fpgamap($ $ $) {
die "ERROR: ABC verilog rewrite failed for benchmark $bm!\n";
}
print "Leaving $abc_dir\n";
chdir $cwd;
}

13
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -667,10 +667,12 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp,
}
/* Check */
assert ((INC_DIRECTION == src_rr_node->direction)
||(DEC_DIRECTION == src_rr_node->direction));
if (! ((CHANX == src_rr_node->type) ||(CHANY == src_rr_node->type)))
assert ((CHANX == src_rr_node->type)
||(CHANY == src_rr_node->type));
assert ((INC_DIRECTION == src_rr_node->direction)
||(DEC_DIRECTION == src_rr_node->direction));
assert (IPIN == des_rr_node->type);
fprintf(fp, "set_max_delay");
@ -928,6 +930,13 @@ void verilog_generate_sdc_constrain_one_cb(FILE* fp,
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
t_rr_node* cur_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
for (int iedge = 0; iedge < cur_ipin_node->num_drive_rr_nodes; iedge++) {
/* Skip the drivers that are not CHANX or CHANY.
* OPINs should be handled by directlist
*/
if ( (CHANX != cur_ipin_node->drive_rr_nodes[iedge]->type)
&& (CHANY != cur_ipin_node->drive_rr_nodes[iedge]->type) ) {
continue;
}
/* Get the switch delay */
int switch_id = cur_ipin_node->drive_switches[iedge];
float switch_delay = get_switch_sdc_tmax (&(switch_inf[switch_id]));