riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add explicit mapping option into fpga_flow

This commit is contained in:
AurelienUoU 2019-07-11 14:44:30 -06:00
parent ad0b4b3acd
commit 1848771e54
2 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
fpga_flow/scripts/fpga_flow.pl
View File

@ -189,6 +189,7 @@ sub print_usage()
print " \t-vpr_fpga_verilog_print_top_tb : turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE\n";
print " \t-vpr_fpga_verilog_print_input_blif_tb : turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE\n";
print " \t-vpr_fpga_verilog_print_modelsim_autodeck <modelsim.ini_path>: turn on printing modelsim simulation script\n";
print " \t-vpr_fpga_verilog_explicit_mapping\n";
print " [ VPR - FPGA-Bitstream Extension ] \n";
print " \t-vpr_fpga_bitstream_generator: turn on FPGA-SPICE bitstream generator\n";
exit(1);
@ -373,6 +374,7 @@ sub opts_read()
&read_opt_into_hash("vpr_fpga_verilog_print_sdc_pnr","off","off");
&read_opt_into_hash("vpr_fpga_verilog_print_sdc_analysis","off","off");
&read_opt_into_hash("vpr_fpga_verilog_print_user_defined_template","off","off");
&read_opt_into_hash("vpr_fpga_verilog_explicit_mapping","off","off");
# Regression test option
&read_opt_into_hash("end_flow_with_test","off","off");
@ -1420,6 +1422,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_sdc_analysis}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_sdc_analysis";
}
if ("on" eq $opt_ptr->{vpr_fpga_verilog_explicit_mapping}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_explicit_mapping";
}
}
# FPGA Bitstream Generator Options

2
fpga_flow/tuto_fpga_flow.sh
View File

@ -28,6 +28,6 @@ perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the
# SRAM FPGA
# TT case
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping
echo "Netlists successfully generated and tested"