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Merge remote-tracking branch 'origin/dev' into documentation

This commit is contained in:
AurelienUoU 2019-07-11 10:15:26 -06:00
parent 346b6f3e8e 31749fe62b
commit ad0b4b3acd
40 changed files with 2832 additions and 1762 deletions
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4
fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
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@ -336,8 +336,8 @@
<output_buffer exist="on" spice_model_name="INV1X"/>
<pass_gate_logic spice_model_name="TGATEX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</spice_model>

4
fpga_flow/scripts/fpga_flow.pl
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@ -1318,7 +1318,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
my ($chan_width_opt) = ("");
if (($fix_chan_width > 0)||($fix_chan_width == 0)) {
$chan_width_opt = "-route_chan_width $fix_chan_width";
$chan_width_opt = "--route_chan_width $fix_chan_width";
}
if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) {
$chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width";
@ -1569,7 +1569,7 @@ sub run_mpack2_vpr($ $ $ $ $ $ $)
if (0 != $min_chan_width%2) {
$min_chan_width += 1;
}
$chan_width_opt = "-route_chan_width $min_chan_width";
$chan_width_opt = "--route_chan_width $min_chan_width";
}
chdir $vpr_dir;

2507
vpr7_x2p/libarchfpga/tags
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File diff suppressed because it is too large Load Diff

1
vpr7_x2p/vpr/SRC/base/OptionTokens.c
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@ -86,6 +86,7 @@ struct s_TokenPair OptionBaseTokenList[] = {
/* Xifan TANG: Synthsizable Verilog */
{ "fpga_verilog", OT_FPGA_VERILOG_SYN },
{ "fpga_verilog_dir", OT_FPGA_VERILOG_SYN_DIR },
{ "fpga_verilog_explicit_mapping", OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING },
{ "fpga_verilog_print_top_testbench", OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH },
{ "fpga_verilog_print_autocheck_top_testbench", OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH },
{ "fpga_verilog_print_input_blif_testbench", OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH },

1
vpr7_x2p/vpr/SRC/base/OptionTokens.h
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@ -103,6 +103,7 @@ enum e_OptionBaseToken {
/* Xifan TANG: Verilog Generation */
OT_FPGA_VERILOG_SYN, /* Xifan TANG: Synthesizable Verilog Dump */
OT_FPGA_VERILOG_SYN_DIR, /* Xifan TANG: Synthesizable Verilog Dump */
OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING, /* Baudouin Chauviere: explicit pin mapping during verilog generation */
OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist */
OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist */
OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for the orignial input blif */

2
vpr7_x2p/vpr/SRC/base/ReadOptions.c
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@ -531,6 +531,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
return Args;
case OT_FPGA_VERILOG_SYN_DIR:
return ReadString(Args, &Options->fpga_syn_verilog_dir);
case OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING:
return Args;
case OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH:
return Args;
case OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH:

5
vpr7_x2p/vpr/SRC/base/SetupVPR.c
View File

@ -1098,6 +1098,7 @@ static void SetupSynVerilogOpts(t_options Options,
/* Initialize */
syn_verilog_opts->dump_syn_verilog = FALSE;
syn_verilog_opts->syn_verilog_dump_dir = NULL;
syn_verilog_opts->dump_explicit_verilog = FALSE;
syn_verilog_opts->print_top_testbench = FALSE;
syn_verilog_opts->print_autocheck_top_testbench = FALSE;
syn_verilog_opts->reference_verilog_benchmark_file = NULL;
@ -1124,6 +1125,10 @@ static void SetupSynVerilogOpts(t_options Options,
syn_verilog_opts->syn_verilog_dump_dir = my_strdup(Options.fpga_syn_verilog_dir);
}
if (Options.Count[OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING]) {
syn_verilog_opts->dump_explicit_verilog = TRUE;
}
if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH]) {
syn_verilog_opts->print_top_testbench = TRUE;
}

37
vpr7_x2p/vpr/SRC/base/vpr_api.c
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@ -197,6 +197,7 @@ void vpr_print_usage(void) {
vpr_printf(TIO_MESSAGE_INFO, "Synthesizable Verilog Generator Options:\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_dir <string>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_explicit_mapping\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_top_testbench\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_autocheck_top_testbench <reference_verilog_file_path>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_input_blif_testbench\n");
@ -364,16 +365,16 @@ void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) {
alloc_and_load_grid(num_instances_type);
freeGrid();
/* Xifan TANG: We need consider the length of carry-chain CLBs into account! */
num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros);
/* find length of longest carry-chain logic blocks */
max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros);
/* Free all the allocated structs */
free_placement_macros_structs();
for (imacro = 0; imacro < num_pl_macros; imacro ++) {
free(pl_macros[imacro].members);
}
free(pl_macros);
/* Xifan TANG: We need consider the length of carry-chain CLBs into account! */
num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros);
/* find length of longest carry-chain logic blocks */
max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros);
/* Free all the allocated structs */
free_placement_macros_structs();
for (imacro = 0; imacro < num_pl_macros; imacro ++) {
free(pl_macros[imacro].members);
}
free(pl_macros);
/* Test if netlist fits in grid */
fit = TRUE;
@ -383,14 +384,14 @@ void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) {
break;
}
}
/* If the length of macros is longer than ny - 2, fitting should fail.
* Note: carry-chain logic blocks are placed only vertically in FPGA.
*/
if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) {
fit = FALSE;
vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d)!\n",
max_len_chain_blocks, ny);
}
/* If the length of macros is longer than ny - 2, fitting should fail.
* Note: carry-chain logic blocks are placed only vertically in FPGA.
*/
if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) {
fit = FALSE;
vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d)!\n",
max_len_chain_blocks, ny);
}
/* get next value */
if (!fit) {

1
vpr7_x2p/vpr/SRC/base/vpr_types.h
View File

@ -1258,6 +1258,7 @@ struct s_spice_opts {
typedef struct s_syn_verilog_opts t_syn_verilog_opts;
struct s_syn_verilog_opts {
boolean dump_syn_verilog;
boolean dump_explicit_verilog;
char* syn_verilog_dump_dir;
boolean print_top_testbench;
boolean print_input_blif_testbench;

13
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp
View File

@ -687,10 +687,15 @@ void alloc_rr_graph_fast_lookup(const DeviceCoordinator& device_size,
if ((SOURCE == type) || (OPIN == type) ) {
continue;
}
rr_graph->rr_node_indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * device_size.get_x());
for (size_t i = 0; i < device_size.get_x(); ++i) {
rr_graph->rr_node_indices[type][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * device_size.get_y());
for (size_t j = 0; j < device_size.get_y(); ++j) {
DeviceCoordinator actual_device_size(device_size);
/* Special for CHANX: we use (y,x) in allocation */
if (CHANX == type) {
actual_device_size.rotate();
}
rr_graph->rr_node_indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * actual_device_size.get_x());
for (size_t i = 0; i < actual_device_size.get_x(); ++i) {
rr_graph->rr_node_indices[type][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * actual_device_size.get_y());
for (size_t j = 0; j < actual_device_size.get_y(); ++j) {
rr_graph->rr_node_indices[type][i][j].nelem = 0;
rr_graph->rr_node_indices[type][i][j].list = NULL;
}

60
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp
View File

@ -1062,52 +1062,53 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph,
assert (0 == actual_track_list.size() % 2);
/* Scale Fc */
int actual_Fc = Fc * actual_track_list.size() / chan_width;
int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width);
/* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */
actual_Fc = std::max(2, actual_Fc);
actual_Fc = std::max(1, actual_Fc);
/* Compute the step between two connection from this IPIN to tracks:
* step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in
*/
size_t track_step = actual_track_list.size() / actual_Fc;
/* Track step mush be a multiple of 2!!!*/
if (0 != track_step % 2) {
track_step--; /* minus 1 to increase connectivity */
}
*/
size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc);
/* Make sure step should be at least 2 */
track_step = std::max(2, (int)track_step);
track_step = std::max(1, (int)track_step);
/* Adapt offset to the range of actual_track_list */
size_t actual_offset = offset % actual_track_list.size();
/* rotate the track list by an offset */
std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end());
if (0 < actual_offset) {
std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end());
}
/* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step */
int track_cnt = 0;
/* Keep assigning until we meet the Fc requirement */
for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + 2 * track_step) {
/* Update pin2track map */
size_t chan_side_index = chan_side_manager.to_size_t();
size_t ipin_index = ipin_node - rr_graph->rr_node;
/* itrack may exceed the size of actual_track_list, adapt it */
size_t actual_itrack = itrack % actual_track_list.size();
/* track_index may exceed the chan_width(), adapt it */
size_t track_index = actual_track_list[itrack] % chan_width;
size_t track_index = actual_track_list[actual_itrack] % chan_width;
(*track2ipin_map)[chan_side_index][track_index].push_back(ipin_index);
/* track_index may exceed the chan_width(), adapt it */
track_index = (actual_track_list[itrack] + 1) % chan_width;
track_index = (actual_track_list[actual_itrack] + 1) % chan_width;
(*track2ipin_map)[chan_side_index][track_index].push_back(ipin_index);
track_cnt += 2;
/* Stop when we have enough Fc: this may lead to some tracks have zero drivers.
* So I comment it. And we just make sure its track_cnt >= actual_Fc
if (actual_Fc == track_cnt) {
break;
}
*/
}
/* Ensure the number of tracks is similar to Fc */
//printf("Fc_in=%d, track_cnt=%d\n", actual_Fc, track_cnt);
assert (actual_Fc <= track_cnt);
/* Give a warning if Fc is < track_cnt */
/*
if (actual_Fc != track_cnt) {
vpr_printf(TIO_MESSAGE_INFO,
"IPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n",
ipin_node - rr_graph->rr_node, track_cnt, actual_Fc);
}
*/
}
return;
@ -1163,13 +1164,13 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph,
}
/* Scale Fc */
int actual_Fc = Fc * actual_track_list.size() / chan_width;
int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width);
/* Minimum Fc should be 1 : ensure we will drive 1 routing track */
actual_Fc = std::max(1, actual_Fc);
/* Compute the step between two connection from this IPIN to tracks:
* step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in
*/
size_t track_step = actual_track_list.size() / actual_Fc;
size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc);
/* Track step mush be a multiple of 2!!!*/
/* Make sure step should be at least 1 */
track_step = std::max(1, (int)track_step);
@ -1184,10 +1185,13 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph,
/* Assign tracks */
int track_cnt = 0;
/* Keep assigning until we meet the Fc requirement */
for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + track_step) {
/* Update pin2track map */
size_t opin_side_index = opin_side_manager.to_size_t();
size_t track_index = actual_track_list[itrack];
/* itrack may exceed the size of actual_track_list, adapt it */
size_t actual_itrack = itrack % actual_track_list.size();
size_t track_index = actual_track_list[actual_itrack];
size_t track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index) - rr_graph->rr_node;
(*opin2track_map)[opin_side_index][opin_node_id].push_back(track_rr_node_index);
/* update track counter */
@ -1201,8 +1205,14 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph,
}
/* Ensure the number of tracks is similar to Fc */
//printf("Fc_out=%lu, scaled_Fc_out=%d, track_cnt=%d, actual_track_cnt=%lu/%lu\n", Fc, actual_Fc, track_cnt, actual_track_list.size(), chan_width);
assert (actual_Fc <= track_cnt);
/* Give a warning if Fc is < track_cnt */
/*
if (actual_Fc != track_cnt) {
vpr_printf(TIO_MESSAGE_INFO,
"OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n",
opin_node_id, track_cnt, actual_Fc);
}
*/
}
return;

40
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
View File

@ -1324,6 +1324,10 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
clock_t t_end;
float run_time_sec;
clock_t t_start_profiling;
clock_t t_end_profiling;
float run_time_sec_profiling = 0.;
/* Start time count */
t_start = clock();
@ -1338,12 +1342,19 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
/* For each switch block, determine the size of array */
for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) {
RRGSB rr_gsb = build_rr_gsb(sb_range, ix, iy,
LL_num_rr_nodes, LL_rr_node,
LL_rr_node_indices,
num_segments, LL_rr_indexed_data);
const RRGSB& rr_gsb = build_rr_gsb(sb_range, ix, iy,
LL_num_rr_nodes, LL_rr_node,
LL_rr_node_indices,
num_segments, LL_rr_indexed_data);
/* For profiling */
t_start_profiling = clock();
/* sort drive_rr_nodes */
sort_rr_gsb_drive_rr_nodes(rr_gsb);
/* End time count */
t_end_profiling = clock();
run_time_sec_profiling += (float)(t_end_profiling - t_start_profiling) / CLOCKS_PER_SEC;
/* Add to device_rr_gsb */
DeviceCoordinator sb_coordinator = rr_gsb.get_sb_coordinator();
LL_device_rr_gsb.add_rr_gsb(sb_coordinator, rr_gsb);
@ -1354,6 +1365,14 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
"Backannotated %d switch blocks.\n",
(nx + 1) * (ny + 1) );
/* End time count */
t_end = clock();
run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
vpr_printf(TIO_MESSAGE_INFO, "Backannotation of Switch Block took %g seconds\n\n", run_time_sec);
vpr_printf(TIO_MESSAGE_INFO, "Edge sorting for Switch Block took %g seconds\n\n", run_time_sec_profiling);
if (TRUE == output_sb_xml) {
create_dir_path(sb_xml_dir);
@ -1376,17 +1395,22 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
/* Report number of unique CB Modules */
vpr_printf(TIO_MESSAGE_INFO,
"Detect %d independent connection blocks from %d X-channel connection blocks.\n",
"Detect %d unique connection blocks from %d X-channel connection blocks.\n",
LL_device_rr_gsb.get_num_cb_unique_module(CHANX), (nx + 0) * (ny + 1) );
vpr_printf(TIO_MESSAGE_INFO,
"Detect %d independent connection blocks from %d Y-channel connection blocks.\n",
"Detect %d unique connection blocks from %d Y-channel connection blocks.\n",
LL_device_rr_gsb.get_num_cb_unique_module(CHANY), (nx + 1) * (ny + 0) );
/* Report number of unique SB modules */
vpr_printf(TIO_MESSAGE_INFO,
"Detect %d independent switch blocks from %d switch blocks.\n",
"Detect %d unique switch blocks from %d switch blocks.\n",
LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) );
/* Report number of unique GSB modules */
vpr_printf(TIO_MESSAGE_INFO,
"Detect %d unique GSBs from %d GSBs.\n",
LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) );
/* Report number of unique mirrors */
@ -1406,7 +1430,7 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
t_end = clock();
run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniqifying took %g seconds\n", run_time_sec);
vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniqifying took %g seconds\n\n", run_time_sec);
return LL_device_rr_gsb;
}

10
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c
View File

@ -3476,3 +3476,13 @@ int my_strlen_int(int input_int) {
return length_input;
}
boolean my_bool_to_boolean(bool my_bool) {
if(true == my_bool)
return TRUE;
if(false == my_bool)
return FALSE;
vpr_printf(TIO_MESSAGE_ERROR,"Failure to convert bool to boolean. Parameter is neither true nor false.\n");
exit(1);
}

1
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h
View File

@ -406,4 +406,5 @@ void get_fpga_x2p_global_all_clock_ports(t_llist* head,
int my_strlen_int(int input_int);
boolean my_bool_to_boolean(bool my_bool);
#endif

79
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp
View File

@ -2379,6 +2379,11 @@ size_t DeviceRRGSB::get_num_sb_unique_module() const {
return sb_unique_module_.size();
}
/* get the number of unique mirrors of switch blocks */
size_t DeviceRRGSB::get_num_gsb_unique_module() const {
return gsb_unique_module_.size();
}
/* Get the submodule id of a SB */
size_t DeviceRRGSB::get_sb_unique_submodule_id(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const {
@ -2565,6 +2570,8 @@ void DeviceRRGSB::set_sb_conf_bits_msb(DeviceCoordinator& coordinator, size_t co
void DeviceRRGSB::reserve(DeviceCoordinator& coordinator) {
rr_gsb_.resize(coordinator.get_x());
gsb_unique_module_id_.resize(coordinator.get_x());
sb_unique_submodule_id_.resize(coordinator.get_x());
sb_unique_module_id_.resize(coordinator.get_x());
@ -2574,6 +2581,8 @@ void DeviceRRGSB::reserve(DeviceCoordinator& coordinator) {
for (size_t x = 0; x < coordinator.get_x(); ++x) {
rr_gsb_[x].resize(coordinator.get_y());
gsb_unique_module_id_[x].resize(coordinator.get_y());
sb_unique_submodule_id_[x].resize(coordinator.get_y());
sb_unique_module_id_[x].resize(coordinator.get_y());
@ -2598,7 +2607,7 @@ void DeviceRRGSB::reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator)
}
/* Resize rr_switch_block array is needed*/
void DeviceRRGSB::resize_upon_need(DeviceCoordinator& coordinator) {
void DeviceRRGSB::resize_upon_need(const DeviceCoordinator& coordinator) {
if (coordinator.get_x() + 1 > rr_gsb_.size()) {
rr_gsb_.resize(coordinator.get_x() + 1);
@ -2622,7 +2631,7 @@ void DeviceRRGSB::resize_upon_need(DeviceCoordinator& coordinator) {
}
/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void DeviceRRGSB::add_rr_gsb(DeviceCoordinator& coordinator,
void DeviceRRGSB::add_rr_gsb(const DeviceCoordinator& coordinator,
const RRGSB& rr_gsb) {
/* Resize upon needs*/
resize_upon_need(coordinator);
@ -2769,6 +2778,45 @@ void DeviceRRGSB::add_sb_unique_side_segment_submodule(DeviceCoordinator& coordi
return;
}
/* Find repeatable GSB block in the array */
void DeviceRRGSB::build_gsb_unique_module() {
/* Make sure a clean start */
clear_gsb_unique_module();
for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) {
for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) {
bool is_unique_module = true;
DeviceCoordinator gsb_coordinator(ix, iy);
/* Traverse the unique_mirror list and check it is an mirror of another */
for (size_t id = 0; id < get_num_gsb_unique_module(); ++id) {
/* We have alreay built sb and cb unique module list
* We just need to check if the unique module id of SBs, CBX and CBY are the same or not
*/
const DeviceCoordinator& gsb_unique_module_coordinator = gsb_unique_module_[id];
if ((sb_unique_module_id_[ix][iy] == sb_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()])
&& (cbx_unique_module_id_[ix][iy] == cbx_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()])
&& (cby_unique_module_id_[ix][iy] == cby_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()])) {
/* This is a mirror, raise the flag and we finish */
is_unique_module = false;
/* Record the id of unique mirror */
gsb_unique_module_id_[ix][iy] = id;
break;
}
}
/* Add to list if this is a unique mirror*/
if (true == is_unique_module) {
add_gsb_unique_module(gsb_coordinator);
/* Record the id of unique mirror */
gsb_unique_module_id_[ix][iy] = get_num_gsb_unique_module() - 1;
}
}
}
return;
}
void DeviceRRGSB::build_unique_module() {
build_segment_ids();
@ -2777,6 +2825,8 @@ void DeviceRRGSB::build_unique_module() {
build_cb_unique_module(CHANX);
build_cb_unique_module(CHANY);
build_gsb_unique_module();
return;
}
@ -2797,6 +2847,11 @@ void DeviceRRGSB::add_sb_unique_side_submodule(DeviceCoordinator& coordinator,
return;
}
void DeviceRRGSB::add_gsb_unique_module(const DeviceCoordinator& coordinator) {
gsb_unique_module_.push_back(coordinator);
return;
}
void DeviceRRGSB::add_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator) {
assert (validate_cb_type(cb_type));
switch(cb_type) {
@ -2868,6 +2923,9 @@ void DeviceRRGSB::build_segment_ids() {
void DeviceRRGSB::clear() {
clear_gsb();
clear_gsb_unique_module();
clear_gsb_unique_module_id();
/* clean unique module lists */
clear_cb_unique_module(CHANX);
clear_cb_unique_module_id(CHANX);
@ -2893,6 +2951,15 @@ void DeviceRRGSB::clear_gsb() {
return;
}
void DeviceRRGSB::clear_gsb_unique_module_id() {
/* clean rr_switch_block array */
for (size_t x = 0; x < rr_gsb_.size(); ++x) {
gsb_unique_module_id_[x].clear();
}
return;
}
void DeviceRRGSB::clear_sb_unique_module_id() {
/* clean rr_switch_block array */
for (size_t x = 0; x < rr_gsb_.size(); ++x) {
@ -2950,6 +3017,14 @@ void DeviceRRGSB::clear_sb_unique_submodule() {
return;
}
/* clean the content related to unique_mirrors */
void DeviceRRGSB::clear_gsb_unique_module() {
/* clean unique mirror */
gsb_unique_module_.clear();
return;
}
/* clean the content related to unique_mirrors */
void DeviceRRGSB::clear_sb_unique_module() {
/* clean unique mirror */

12
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h
View File

@ -330,6 +330,7 @@ class DeviceRRGSB {
DeviceCoordinator get_gsb_range() const; /* get the max coordinator of the switch block array */
const RRGSB get_gsb(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */
const RRGSB get_gsb(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */
size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */
size_t get_num_sb_unique_submodule(enum e_side side, size_t seg_index) const; /* get the number of unique mirrors of switch blocks */
size_t get_num_sb_unique_module() const; /* get the number of unique mirrors of switch blocks */
size_t get_num_cb_unique_module(t_rr_type cb_type) const; /* get the number of unique mirrors of CBs */
@ -353,8 +354,8 @@ class DeviceRRGSB {
void set_cb_conf_bits_msb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
void reserve(DeviceCoordinator& coordinator); /* Pre-allocate the rr_switch_block array that the device requires */
void reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */
void resize_upon_need(DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */
void add_rr_gsb(DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void resize_upon_need(const DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */
void add_rr_gsb(const DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void build_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void clear(); /* clean the content */
private: /* Internal cleaners */
@ -365,6 +366,8 @@ class DeviceRRGSB {
void clear_sb_unique_module_id(); /* clean the content */
void clear_sb_unique_submodule(); /* clean the content */
void clear_sb_unique_submodule_id(); /* clean the content */
void clear_gsb_unique_module(); /* clean the content */
void clear_gsb_unique_module_id(); /* clean the content */
void clear_segment_ids();
private: /* Validators */
bool validate_coordinator(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device */
@ -376,6 +379,7 @@ class DeviceRRGSB {
bool validate_cb_type(t_rr_type cb_type) const;
private: /* Internal builders */
void build_segment_ids(); /* build a map of segment_ids */
void add_gsb_unique_module(const DeviceCoordinator& coordinator);
void add_sb_unique_side_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side);
void add_sb_unique_side_segment_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side, size_t seg_id);
void add_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator);
@ -383,9 +387,13 @@ class DeviceRRGSB {
void build_sb_unique_submodule(); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */
void build_sb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void build_cb_unique_module(t_rr_type cb_type); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */
void build_gsb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
private: /* Internal Data */
std::vector< std::vector<RRGSB> > rr_gsb_;
std::vector< std::vector<size_t> > gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */
std::vector<DeviceCoordinator> gsb_unique_module_;
std::vector< std::vector<size_t> > sb_unique_module_id_; /* A map from rr_gsb to its unique mirror */
std::vector<DeviceCoordinator> sb_unique_module_;

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
View File

@ -255,14 +255,16 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
/* Dump routing resources: switch blocks, connection blocks and channel tracks */
dump_verilog_routing_resources(sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, &vpr_setup.RoutingArch,
num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data,
vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
vpr_setup.FPGA_SPICE_Opts);
/* Dump logic blocks
* Branches to go:
* 1. a compact output
* 2. a full-size output
*/
dump_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path, lb_dir_path, &Arch);
dump_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path,
lb_dir_path, &Arch,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
/* Dump internal structures of submodules */
dump_verilog_submodules(sram_verilog_orgz_info, src_dir_path, submodule_dir_path,
@ -275,7 +277,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
num_rr_nodes, rr_node, rr_node_indices,
num_clocks,
vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy,
*(Arch.spice));
*(Arch.spice), vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
/* Dump SDC constraints */
/* Output SDC to contrain the P&R flow
@ -288,8 +290,6 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
}
/* dump_verilog_sdc_file(); */
/* dump verilog testbench only for input blif */
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_input_blif_testbench) {
blif_testbench_file_name = my_strcat(chomped_circuit_name, blif_testbench_verilog_file_postfix);

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c
View File

@ -354,6 +354,7 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
t_spice verilog) {
FILE* fp = NULL;
char* title = my_strcat("FPGA Verilog Testbench for Top-level netlist of Design: ", circuit_name);
bool is_explicit_mapping = fpga_verilog_opts.dump_explicit_verilog;
/* Check if the path exists*/
fp = fopen(top_netlist_name,"w");
@ -379,7 +380,8 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_top_auto_testbench_ports(fp, cur_sram_orgz_info, circuit_name, fpga_verilog_opts);
/* Call defined top-level module */
dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name);
dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp,
circuit_name, is_explicit_mapping);
/* Call defined benchmark */
dump_verilog_top_auto_testbench_call_benchmark(fp, circuit_name);

224
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -281,7 +281,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
char* verilog_dir_path,
char* subckt_dir_path,
t_type_ptr phy_block_type,
int border_side) {
int border_side,
bool is_explicit_mapping) {
int iz;
int temp_reserved_conf_bits_msb;
int temp_iopad_lsb, temp_iopad_msb;
@ -343,7 +344,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, "//----- Submodule of type_descriptor: %s -----\n", phy_block_type->name);
/* Print a NULL logic block...*/
dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name_prefix,
phy_block_type->pb_graph_head, iz);
phy_block_type->pb_graph_head, iz,
is_explicit_mapping);
fprintf(fp, "//----- END -----\n\n");
/* Switch Flag on dumping verilog module */
verilog_module_dumped = TRUE;
@ -359,7 +361,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, "module %s ( \n", subckt_name);
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
@ -376,7 +378,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
/* I/O PAD */
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
0, phy_block_type->capacity * phy_block_type->pb_type->physical_mode_num_iopads - 1,
VERILOG_PORT_INOUT);
VERILOG_PORT_INOUT, false);
/* Print configuration ports */
/* Reserved configuration ports */
@ -404,7 +406,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
0,
temp_conf_bits_msb - 1,
VERILOG_PORT_INPUT); // Should be modified to be VERILOG_PORT_INPUT
VERILOG_PORT_INPUT, false); // Should be modified to be VERILOG_PORT_INPUT
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -428,15 +430,15 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, " %s (", gen_verilog_one_phy_block_instance_name(phy_block_type, iz));
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
/* Print all the pins */
/* Special Care for I/O grid */
if (IO_TYPE == phy_block_type) {
dump_compact_verilog_io_grid_block_subckt_pins(fp, phy_block_type, border_side, iz);
dump_compact_verilog_io_grid_block_subckt_pins(fp, phy_block_type, border_side, iz, is_explicit_mapping);
} else {
dump_verilog_grid_block_subckt_pins(fp, iz, phy_block_type);
dump_verilog_grid_block_subckt_pins(fp, iz, phy_block_type, is_explicit_mapping);
}
/* Print configuration ports */
@ -448,7 +450,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, "\n//---- IOPAD ----\n");
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
temp_iopad_lsb, temp_iopad_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
/* Reserved configuration ports */
if (0 < temp_reserved_conf_bits_msb) {
fprintf(fp, ",\n");
@ -462,7 +464,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, "//---- SRAM ----\n");
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
temp_conf_bits_lsb, temp_conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
@ -473,7 +475,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
temp_conf_bits_lsb,
temp_conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -512,7 +514,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir,
char* subckt_dir,
t_arch* arch) {
t_arch* arch,
bool is_explicit_mapping) {
int itype, iside, num_sides;
int* stamped_spice_model_cnt = NULL;
t_sram_orgz_info* stamped_sram_orgz_info = NULL;
@ -534,20 +537,23 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
for (iside = 0; iside < num_sides; iside++) {
dump_compact_verilog_one_physical_block(cur_sram_orgz_info,
verilog_dir, subckt_dir,
&type_descriptors[itype], iside);
&type_descriptors[itype], iside,
is_explicit_mapping);
}
continue;
} else if (FILL_TYPE == &type_descriptors[itype]) {
/* For CLB */
dump_compact_verilog_one_physical_block(cur_sram_orgz_info,
verilog_dir, subckt_dir,
&type_descriptors[itype], -1);
&type_descriptors[itype], -1,
is_explicit_mapping);
continue;
} else {
/* For heterogenenous blocks */
dump_compact_verilog_one_physical_block(cur_sram_orgz_info,
verilog_dir, subckt_dir,
&type_descriptors[itype], -1);
&type_descriptors[itype], -1,
is_explicit_mapping);
}
}
@ -586,7 +592,8 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
static
void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int ix, int iy, int border_side) {
int ix, int iy, int border_side,
bool is_explicit_mapping) {
char* subckt_name = NULL;
if (NULL == fp) {
@ -610,21 +617,21 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
if (IO_TYPE == grid[ix][iy].type) {
dump_verilog_io_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE);
dump_verilog_io_grid_pins(fp, ix, iy, TRUE, border_side, FALSE, FALSE, is_explicit_mapping);
} else {
dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE);
dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE, is_explicit_mapping);
}
/* IO PAD */
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
iopad_verilog_model->grid_index_low[ix][iy],
iopad_verilog_model->grid_index_high[ix][iy] - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
/* Print configuration ports */
/* Reserved configuration ports */
@ -642,7 +649,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
cur_sram_orgz_info->grid_conf_bits_lsb[ix][iy],
cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
@ -654,7 +661,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sram_orgz_info->grid_conf_bits_lsb[ix][iy],
cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -670,7 +677,8 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
*/
static
void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
FILE* fp,
bool is_explicit_mapping) {
int ix, iy;
if (NULL == fp) {
@ -686,7 +694,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
continue;
}
assert(IO_TYPE != grid[ix][iy].type);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, -1);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp,
ix, iy, -1, is_explicit_mapping);
}
}
@ -699,7 +708,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
continue;
}
assert(IO_TYPE == grid[ix][iy].type);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 0);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp,
ix, iy, 0, is_explicit_mapping);
}
/* RIGHT side */
ix = nx + 1;
@ -709,7 +719,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
continue;
}
assert(IO_TYPE == grid[ix][iy].type);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 1);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp,
ix, iy, 1, is_explicit_mapping);
}
/* BOTTOM side */
@ -720,7 +731,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
continue;
}
assert(IO_TYPE == grid[ix][iy].type);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 2);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp,
ix, iy, 2, is_explicit_mapping);
}
/* LEFT side */
ix = 0;
@ -730,7 +742,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
continue;
}
assert(IO_TYPE == grid[ix][iy].type);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 3);
dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix,
iy, 3, is_explicit_mapping);
}
@ -744,7 +757,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,
static
void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
const RRGSB& rr_sb) {
const RRGSB& rr_sb,
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -768,7 +782,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -778,10 +792,20 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
fprintf(fp, "//----- %s side channel ports-----\n", side_manager.c_str());
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {
fprintf(fp, "%s,\n",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
chan_coordinator.get_x(), chan_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
}
fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
chan_coordinator.get_x(), chan_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
if (true == is_explicit_mapping) {
fprintf(fp, ")",itrack);
}
fprintf(fp, ",\n",itrack);
}
fprintf(fp, "//----- %s side inputs: CLB output pins -----\n", convert_side_index_to_string(side));
/* Dump OPINs of adjacent CLBs */
@ -791,7 +815,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode),
rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow,
rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow,
FALSE); /* Do not specify the direction of port */
FALSE, is_explicit_mapping); /* Do not specify the direction of port */
fprintf(fp, ",\n");
}
fprintf(fp, "\n");
@ -814,7 +838,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
@ -826,7 +850,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_sb.get_sb_conf_bits_lsb(),
rr_sb.get_sb_conf_bits_msb(),
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -844,7 +868,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz
static
void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
FILE* fp, bool is_explicit_mapping) {
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
/* Check the file handler*/
@ -857,7 +881,7 @@ void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_i
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy);
dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, rr_sb);
dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, rr_sb, is_explicit_mapping);
}
}
@ -872,7 +896,8 @@ void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_i
static
void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
const RRGSB& rr_gsb, t_rr_type cb_type) {
const RRGSB& rr_gsb, t_rr_type cb_type,
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -893,7 +918,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -902,9 +927,15 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
fprintf(fp, "//----- %s side inputs: channel track middle outputs -----\n",
convert_side_index_to_string(rr_gsb.get_cb_chan_side(cb_type)));
for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
fprintf(fp, "%s, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(", unique_mirror.gen_cb_verilog_routing_track_name(cb_type, itrack));
}
fprintf(fp, "%s",
rr_gsb.gen_cb_verilog_routing_track_name(cb_type, itrack));
fprintf(fp, "\n");
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
}
std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
@ -917,12 +948,26 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
t_rr_node* cur_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
/* Print each INPUT Pins of a grid */
if (true == is_explicit_mapping) {
if (RIGHT == side_manager.get_side()) {
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x() + 1, unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
} else if (TOP == side_manager.get_side()) {
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
} else if (LEFT == side_manager.get_side()) {
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
} else if (BOTTOM == side_manager.get_side()) {
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y(), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
}
}
dump_verilog_grid_side_pin_with_given_index(fp, OPIN,
cur_ipin_node->ptc_num,
rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode),
cur_ipin_node->xlow,
cur_ipin_node->ylow,
FALSE); /* Do not specify direction of port */
FALSE, false); /* Do not specify direction of port */
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", \n");
}
}
@ -941,7 +986,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
rr_gsb.get_cb_conf_bits_lsb(cb_type),
rr_gsb.get_cb_conf_bits_msb(cb_type),
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
if (0 < rr_gsb.get_cb_num_conf_bits(cb_type)) {
@ -951,7 +996,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_gsb.get_cb_conf_bits_lsb(cb_type),
rr_gsb.get_cb_conf_bits_msb(cb_type),
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -968,7 +1013,8 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
/* Call the sub-circuits for connection boxes */
static
void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
FILE* fp,
bool is_explicit_mapping) {
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
/* Check the file handler*/
@ -986,17 +1032,17 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
/* Get X-channel CB coordinator */
const DeviceCoordinator cbx_coordinator = rr_gsb.get_cb_coordinator(CHANX);
/* X - channels [1...nx][0..ny]*/
if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_x()))
if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_y()))
&&(true == rr_gsb.is_cb_exist(CHANX))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX);
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX, is_explicit_mapping);
}
/* Get X-channel CB coordinator */
const DeviceCoordinator cby_coordinator = rr_gsb.get_cb_coordinator(CHANY);
/* Y - channels [1...ny][0..nx]*/
if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_x()))
if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_y()))
&&(true == rr_gsb.is_cb_exist(CHANY))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY);
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY, is_explicit_mapping);
}
}
}
@ -1010,7 +1056,9 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
static
void dump_compact_verilog_defined_one_channel(FILE* fp,
int x, int y,
const RRChan& rr_chan, size_t subckt_id) {
const RRChan& rr_chan,
size_t subckt_id,
bool is_explicit_mapping) {
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__);
exit(1);
@ -1044,7 +1092,7 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -1057,16 +1105,28 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) {
switch (rr_chan.get_node(itrack)->direction) {
case INC_DIRECTION:
fprintf(fp, "%s, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".in%d (",itrack);
}
fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
x, y, itrack, OUT_PORT));
fprintf(fp, "\n");
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
break;
case DEC_DIRECTION:
fprintf(fp, "%s, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".out%d (",itrack);
}
fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
x, y, itrack, IN_PORT));
fprintf(fp, "\n");
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%u]!\n",
@ -1085,16 +1145,28 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) {
switch (rr_chan.get_node(itrack)->direction) {
case INC_DIRECTION:
fprintf(fp, "%s, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".out%d (",itrack);
}
fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
x, y, itrack, IN_PORT));
fprintf(fp, "\n");
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
break;
case DEC_DIRECTION:
fprintf(fp, "%s, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".in%d (",itrack);
}
fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
x, y, itrack, OUT_PORT));
fprintf(fp, "\n");
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%u]!\n",
@ -1107,9 +1179,16 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
/* output at middle point */
for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) {
if (true == is_explicit_mapping) {
fprintf(fp, ".mid_out%d (",
itrack);
}
fprintf(fp, "%s_%d__%d__midout_%lu_ ",
convert_chan_type_to_string(rr_chan.get_type()),
x, y, itrack);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
if (itrack < rr_chan.get_chan_width() - 1) {
fprintf(fp, ",");
}
@ -1131,7 +1210,8 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
/* Call the sub-circuits for channels : Channel X and Channel Y*/
static
void dump_compact_verilog_defined_channels(FILE* fp) {
void dump_compact_verilog_defined_channels(FILE* fp,
bool is_explicit_mapping) {
int ix, iy;
if (NULL == fp) {
@ -1144,7 +1224,8 @@ void dump_compact_verilog_defined_channels(FILE* fp) {
for (ix = 1; ix < (nx + 1); ix++) {
dump_compact_verilog_defined_one_channel(fp, ix, iy,
device_rr_chan.get_module_with_coordinator(CHANX, ix, iy),
device_rr_chan.get_module_id(CHANX, ix, iy));
device_rr_chan.get_module_id(CHANX, ix, iy),
is_explicit_mapping);
}
}
@ -1153,7 +1234,8 @@ void dump_compact_verilog_defined_channels(FILE* fp) {
for (iy = 1; iy < (ny + 1); iy++) {
dump_compact_verilog_defined_one_channel(fp, ix, iy,
device_rr_chan.get_module_with_coordinator(CHANY, ix, iy),
device_rr_chan.get_module_id(CHANY, ix, iy));
device_rr_chan.get_module_id(CHANY, ix, iy),
is_explicit_mapping);
}
}
@ -1177,7 +1259,8 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
t_ivec*** LL_rr_node_indices,
int num_clock,
boolean compact_routing_hierarchy,
t_spice verilog) {
t_spice verilog,
bool is_explicit_mapping) {
FILE* fp = NULL;
char* formatted_dir_path = NULL;
char* temp_include_file_path = NULL;
@ -1224,33 +1307,34 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
my_free(temp_include_file_path);
/* Print all global wires*/
dump_verilog_top_netlist_ports(cur_sram_orgz_info, fp, num_clock, circuit_name, verilog);
dump_verilog_top_netlist_ports(cur_sram_orgz_info, fp, num_clock,
circuit_name, verilog, is_explicit_mapping);
dump_verilog_top_netlist_internal_wires(cur_sram_orgz_info, fp);
/* Quote Routing structures: Channels */
if (TRUE == compact_routing_hierarchy ) {
dump_compact_verilog_defined_channels(fp);
dump_compact_verilog_defined_channels(fp, is_explicit_mapping);
} else {
dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices);
dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping);
}
/* Quote Routing structures: Switch Boxes */
if (TRUE == compact_routing_hierarchy ) {
dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp);
dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping);
} else {
dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp);
dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); /* BC: Explicit mapping not done because we will erase this in the future*/
}
/* Quote Routing structures: Connection Boxes */
if (TRUE == compact_routing_hierarchy ) {
dump_compact_verilog_defined_connection_boxes(cur_sram_orgz_info, fp);
dump_compact_verilog_defined_connection_boxes(cur_sram_orgz_info, fp, is_explicit_mapping);
} else {
dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp);
dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp, is_explicit_mapping);
}
/* Quote defined Logic blocks subckts (Grids) */
dump_compact_verilog_defined_grids(cur_sram_orgz_info, fp);
dump_compact_verilog_defined_grids(cur_sram_orgz_info, fp, is_explicit_mapping);
/* Apply CLB to CLB direct connections */
dump_verilog_clb2clb_directs(fp, num_clb2clb_directs, clb2clb_direct);

9
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h
View File

@ -5,12 +5,14 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
char* verilog_dir_path,
char* subckt_dir_path,
t_type_ptr phy_block_type,
int border_side);
int border_side,
bool is_explicit_mapping);
void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir,
char* subckt_dir,
t_arch* arch);
t_arch* arch,
bool is_explicit_mapping);
void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name,
@ -24,5 +26,6 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
t_ivec*** LL_rr_node_indices,
int num_clock,
boolean compact_routing_hierarchy,
t_spice verilog);
t_spice verilog,
bool is_explicit_verilog);
#endif

269
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -369,9 +369,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
pb_type_port->num_pins - 1,
port_prefix, pb_type_port->name);
} else {
if ((NULL != cur_pb_type->spice_model)
&& (TRUE == dump_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
if (TRUE == dump_explicit_port_map) {
fprintf(fp, ".%s(",
pb_type_port->spice_model_port->lib_name);
}
@ -384,9 +382,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin));
}
fprintf(fp, "}");
if ((NULL != cur_pb_type->spice_model)
&& (TRUE == dump_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
if (TRUE == dump_explicit_port_map) {
fprintf(fp, ")");
}
}
@ -539,7 +535,8 @@ void dump_verilog_pb_type_ports(FILE* fp,
t_pb_type* cur_pb_type,
boolean dump_port_type,
boolean dump_last_comma,
boolean require_explicit_port_map) {
boolean require_explicit_port_map,
bool is_full_name) {
int iport, ipin;
int num_pb_type_input_port = 0;
t_port** pb_type_input_ports = NULL;
@ -590,18 +587,21 @@ void dump_verilog_pb_type_ports(FILE* fp,
}
if (TRUE == dump_port_type) {
fprintf(fp, "inout wire ");
} else if ((NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
} else if (TRUE == require_explicit_port_map) {
if (false == is_full_name && NULL != cur_pb_type->spice_model) {
fprintf(fp, ".%s(",
pb_type_inout_ports[iport]->spice_model_port->lib_name);
} else {
/* fprintf(fp, ".%s(",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_inout_ports[iport], ipin)); */
fprintf(fp, ".%s__%s_%d_(",
cur_pb_type->name, pb_type_inout_ports[iport]->name, ipin);
}
}
fprintf(fp, "%s",
fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_inout_ports[iport], ipin));
if ((FALSE == dump_port_type)
&& (NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
if ((FALSE == dump_port_type)
&& TRUE == require_explicit_port_map) {
fprintf(fp, ") ");
}
/* Update the counter */
@ -633,18 +633,21 @@ void dump_verilog_pb_type_ports(FILE* fp,
}
if (TRUE == dump_port_type) {
fprintf(fp, "input wire ");
} else if ((NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
} else if (TRUE == require_explicit_port_map) {
if (false == is_full_name && NULL != cur_pb_type->spice_model) {
fprintf(fp, ".%s(",
pb_type_input_ports[iport]->spice_model_port->lib_name);
} else {
/* fprintf(fp, ".%s(",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_input_ports[iport], ipin)); */
fprintf(fp, ".%s__%s_%d_(",
cur_pb_type->name, pb_type_input_ports[iport]->name, ipin);
}
}
fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_input_ports[iport], ipin));
if ((FALSE == dump_port_type)
&& (NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
&& TRUE == require_explicit_port_map) {
fprintf(fp, ") ");
}
/* Update the counter */
@ -675,18 +678,21 @@ void dump_verilog_pb_type_ports(FILE* fp,
}
if (TRUE == dump_port_type) {
fprintf(fp, "output wire ");
} else if ((NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
} else if (TRUE == require_explicit_port_map) {
if (false == is_full_name && NULL != cur_pb_type->spice_model) {
fprintf(fp, ".%s(",
pb_type_output_ports[iport]->spice_model_port->lib_name);
} else {
/* fprintf(fp, ".%s(",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_output_ports[iport], ipin));*/
fprintf(fp, ".%s__%s_%d_(",
cur_pb_type->name, pb_type_output_ports[iport]->name, ipin);
}
}
fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_output_ports[iport], ipin));
if ((FALSE == dump_port_type)
&& (NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
&& TRUE == require_explicit_port_map) {
fprintf(fp, ") ");
}
/* Update the counter */
@ -720,18 +726,19 @@ void dump_verilog_pb_type_ports(FILE* fp,
}
if (TRUE == dump_port_type) {
fprintf(fp, "input wire ");
} else if ((NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
} else if (TRUE == require_explicit_port_map) {
if (false == is_full_name && NULL != cur_pb_type->spice_model) {
fprintf(fp, ".%s(",
pb_type_clk_ports[iport]->spice_model_port->lib_name);
} else {
fprintf(fp, ".%s__%s_%d_(",
cur_pb_type->name, pb_type_clk_ports[iport]->name, ipin);
}
}
fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_clk_ports[iport], ipin));
if ((FALSE == dump_port_type)
&& (NULL != cur_pb_type->spice_model)
&& (TRUE == require_explicit_port_map)
&& (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) {
&& TRUE == require_explicit_port_map) {
fprintf(fp, ") ");
}
/* Update the counter */
@ -1037,7 +1044,8 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
char* parent_pin_prefix,
enum e_spice_pin2pin_interc_type pin2pin_interc_type,
t_pb_graph_pin* des_pb_graph_pin,
t_mode* cur_mode) {
t_mode* cur_mode,
bool is_explicit_mapping) {
int iedge, ipin;
int fan_in = 0;
t_interconnect* cur_interc = NULL;
@ -1261,7 +1269,8 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
/* Different design technology requires different configuration bus! */
dump_verilog_mux_config_bus_ports(fp, cur_interc->spice_model, cur_sram_orgz_info,
fan_in, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits);
fan_in, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits,
is_explicit_mapping);
fprintf(fp, ");\n");
@ -1274,7 +1283,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, cur_interc->spice_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, cur_interc->spice_model, fan_in,
mem_model, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1);
mem_model, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, is_explicit_mapping);
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits);
@ -1318,7 +1327,8 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info,
char* formatted_pin_prefix,
t_pb_graph_node* cur_pb_graph_node,
enum e_spice_pb_port_type pb_port_type,
t_mode* cur_mode) {
t_mode* cur_mode,
bool is_explicit_mapping) {
int iport, ipin;
/* Check the file handler*/
@ -1339,7 +1349,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info,
formatted_pin_prefix, /* parent_pin_prefix */
INPUT2INPUT_INTERC,
&(cur_pb_graph_node->input_pins[iport][ipin]),
cur_mode);
cur_mode, is_explicit_mapping);
}
}
break;
@ -1351,7 +1361,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info,
formatted_pin_prefix, /* parent_pin_prefix */
OUTPUT2OUTPUT_INTERC,
&(cur_pb_graph_node->output_pins[iport][ipin]),
cur_mode);
cur_mode, is_explicit_mapping);
}
}
break;
@ -1363,7 +1373,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info,
formatted_pin_prefix, /* parent_pin_prefix */
INPUT2INPUT_INTERC,
&(cur_pb_graph_node->clock_pins[iport][ipin]),
cur_mode);
cur_mode, is_explicit_mapping);
}
}
break;
@ -1382,7 +1392,8 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* pin_prefix,
t_pb_graph_node* cur_pb_graph_node,
int select_mode_index) {
int select_mode_index,
bool is_explicit_mapping) {
int ipb, jpb;
t_mode* cur_mode = NULL;
t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type;
@ -1416,7 +1427,7 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix,
cur_pb_graph_node,
SPICE_PB_PORT_OUTPUT,
cur_mode);
cur_mode, is_explicit_mapping);
/* We check input_pins of child_pb_graph_node and its the input_edges
* Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node
@ -1432,12 +1443,12 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix,
child_pb_graph_node,
SPICE_PB_PORT_INPUT,
cur_mode);
cur_mode, is_explicit_mapping);
/* TODO: for clock pins, we should do the same work */
dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix,
child_pb_graph_node,
SPICE_PB_PORT_CLOCK,
cur_mode);
cur_mode, is_explicit_mapping);
}
}
@ -1499,7 +1510,7 @@ void dump_verilog_pb_graph_primitive_node(FILE* fp,
fprintf(fp, "module %s (", subckt_name);
/* subckt_port_name = format_verilog_node_prefix(subckt_name); */
/* Inputs, outputs, inouts, clocks */
dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, TRUE, FALSE, FALSE);
dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, TRUE, FALSE, FALSE, false);
/* SRAM ports */
fprintf(fp, ");\n");
/* Include the spice_model*/
@ -1507,7 +1518,7 @@ void dump_verilog_pb_graph_primitive_node(FILE* fp,
verilog_model->cnt++; /* Stats the number of verilog_model used*/
/* Make input, output, inout, clocks connected*/
/* IMPORTANT: (sequence of these ports should be changed!) */
dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, FALSE, FALSE, TRUE);
dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, FALSE, FALSE, TRUE, true);
fprintf(fp, ");");
/* Print end of subckt*/
fprintf(fp, "endmodule\n");
@ -1523,7 +1534,8 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int pb_index,
t_spice_model* verilog_model) {
t_spice_model* verilog_model,
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -1547,23 +1559,27 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf
case SPICE_MODEL_LUT:
/* If this is a idle block we should set sram_bits to zero*/
dump_verilog_pb_primitive_lut(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node,
pb_index, verilog_model);
pb_index, verilog_model,
my_bool_to_boolean(is_explicit_mapping));
break;
case SPICE_MODEL_FF:
assert(NULL != verilog_model->model_netlist);
/* TODO : We should learn trigger type and initial value!!! and how to apply them!!! */
dump_verilog_pb_generic_primitive(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node,
pb_index, verilog_model);
pb_index, verilog_model,
my_bool_to_boolean(is_explicit_mapping));
break;
case SPICE_MODEL_IOPAD:
assert(NULL != verilog_model->model_netlist);
dump_verilog_pb_generic_primitive (cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node,
pb_index, verilog_model);
pb_index, verilog_model,
my_bool_to_boolean(is_explicit_mapping));
break;
case SPICE_MODEL_HARDLOGIC:
assert(NULL != verilog_model->model_netlist);
dump_verilog_pb_generic_primitive(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node,
pb_index, verilog_model);
pb_index, verilog_model,
my_bool_to_boolean(is_explicit_mapping));
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of verilog_model(%s), should be [LUT|FF|HARD_LOGIC|IO]!\n",
@ -1582,7 +1598,8 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* subckt_prefix,
t_pb_graph_node* cur_pb_graph_node,
int pb_type_index) {
int pb_type_index,
bool is_explicit_mapping) {
int mode_index, ipb, jpb, child_mode_index;
t_pb_type* cur_pb_type = NULL;
char* subckt_name = NULL;
@ -1645,8 +1662,10 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* Recursive*/
/* Refer to pack/output_clustering.c [LINE 392] */
/* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */
dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, pass_on_prefix,
&(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), jpb);
dump_verilog_phy_pb_graph_node_rec(
cur_sram_orgz_info, fp, pass_on_prefix,
&(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]),
jpb, is_explicit_mapping);
/* Free */
my_free(pass_on_prefix);
/* Make the current module has been dumped */
@ -1661,21 +1680,24 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
case LUT_CLASS:
dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix,
cur_pb_graph_node, pb_type_index,
cur_pb_type->spice_model); /* last param means idle */
cur_pb_type->spice_model,
my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */
break;
case LATCH_CLASS:
assert(0 == cur_pb_type->num_modes);
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix,
cur_pb_graph_node, pb_type_index,
cur_pb_type->spice_model); /* last param means idle */
cur_pb_type->spice_model,
my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */
break;
case UNKNOWN_CLASS:
case MEMORY_CLASS:
/* Consider the num_pb, create all the subckts*/
dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix,
cur_pb_graph_node , pb_type_index,
cur_pb_type->spice_model); /* last param means idle */
cur_pb_type->spice_model,
my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n",
@ -1718,16 +1740,16 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
*/
fprintf(fp, "\n");
/* dump global ports */
if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
/* Simplify the port prefix, make SPICE netlist readable */
dump_verilog_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type, TRUE, FALSE, FALSE);
dump_verilog_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type, TRUE, FALSE, FALSE, false);
/* Print Input Pad and Output Pad */
dump_verilog_grid_common_port(fp, iopad_verilog_model,
gio_inout_prefix,
stamped_iopad_cnt, iopad_verilog_model->cnt - 1,
VERILOG_PORT_INOUT);
VERILOG_PORT_INOUT, false);
/* Print Configuration ports */
/* sram_verilog_model->cnt should be updated because all the child pbs have been dumped
* stamped_sram_cnt remains the old sram_verilog_model->cnt before all the child pbs are dumped
@ -1757,7 +1779,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
stamped_sram_cnt,
stamped_sram_cnt + num_conf_bits - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -1804,13 +1826,13 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* dump global ports */
/* If the child node is a primitive, we only dump global ports belonging to this primitive */
if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
} else {
if (0 < rec_dump_verilog_spice_model_global_ports(fp,
cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model,
FALSE, TRUE, FALSE)) {
FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
}
@ -1827,13 +1849,19 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* Print inputs, outputs, inouts, clocks
* NO SRAMs !!! They have already been fixed in the bottom level
*/
dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, FALSE);
bool is_explicit_full_name = true;
if (NULL != cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model){
/*if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){
is_explicit_full_name = false;
}TEST*/
}
dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), is_explicit_full_name);
/* Print I/O pads */
dump_verilog_grid_common_port(fp, iopad_verilog_model,
gio_inout_prefix,
stamped_iopad_cnt,
stamped_iopad_cnt + child_pb_num_iopads - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
/* update stamped outpad counter */
stamped_iopad_cnt += child_pb_num_iopads;
/* Print configuration ports */
@ -1848,7 +1876,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
stamped_sram_cnt,
stamped_sram_cnt + child_pb_num_conf_bits - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
if (0 < child_pb_num_conf_bits) {
@ -1858,7 +1886,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
stamped_sram_cnt,
stamped_sram_cnt + child_pb_num_conf_bits - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -1872,7 +1900,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
}
}
/* Print interconnections, set is_idle as TRUE*/
dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, cur_pb_graph_node, mode_index);
dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name,
cur_pb_graph_node, mode_index,
false);
/* Check each pins of pb_graph_node */
/* Check and update stamped_sram_cnt */
/* Now we only dump one Verilog for each pb_type, and instance them when num_pb > 1
@ -1951,7 +1981,8 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info,
int x,
int y,
int z,
t_type_ptr type_descriptor) {
t_type_ptr type_descriptor,
bool is_explicit_mapping) {
t_pb_graph_node* top_pb_graph_node = NULL;
t_block* mapped_block = NULL;
t_pb* top_pb = NULL;
@ -1978,7 +2009,8 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info,
}
/* Recursively find all idle mode and print netlist*/
dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name, top_pb_graph_node, z);
dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name,
top_pb_graph_node, z, is_explicit_mapping);
return;
}
@ -1991,7 +2023,8 @@ void dump_verilog_grid_pins(FILE* fp,
int y,
boolean top_level,
boolean dump_port_type,
boolean dump_last_comma) {
boolean dump_last_comma,
bool is_explicit_mapping) {
int iheight, side, ipin, class_id;
int side_pin_index;
t_type_ptr type_descriptor = grid[x][y].type;
@ -2046,7 +2079,14 @@ void dump_verilog_grid_pins(FILE* fp,
}
}
/* This pin appear at this side! */
if (true == is_explicit_mapping) {
fprintf(fp, ".%s_height_%d__pin_%d_(",
convert_side_index_to_string(side), iheight, ipin);
}
fprintf(fp, " %s", gen_verilog_grid_one_pin_name(x, y, iheight, side, ipin, top_level));
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Update counter */
num_dumped_port++;
side_pin_index++;
@ -2076,8 +2116,10 @@ void dump_verilog_grid_pins(FILE* fp,
void dump_verilog_io_grid_pins(FILE* fp,
int x, int y,
boolean top_level,
int border_side,
boolean dump_port_type,
boolean dump_last_comma) {
boolean dump_last_comma,
bool is_explicit_mapping) {
int iheight, side, ipin;
int side_pin_index;
t_type_ptr type_descriptor = grid[x][y].type;
@ -2139,7 +2181,14 @@ void dump_verilog_io_grid_pins(FILE* fp,
}
}
/* This pin appear at this side! */
if (true == is_explicit_mapping) {
fprintf(fp, ".%s_height_%d__pin_%d_(",
convert_side_index_to_string(border_side), iheight, ipin);
}
fprintf(fp, " %s", gen_verilog_grid_one_pin_name(x, y, iheight, side, ipin, top_level));
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Update counter */
num_dumped_port++;
side_pin_index++;
@ -2260,9 +2309,11 @@ char* verilog_get_grid_phy_block_subckt_name(int x, int y, int z,
/* Print the pins of grid subblocks */
void dump_verilog_grid_block_subckt_pins(FILE* fp,
int z,
t_type_ptr type_descriptor) {
t_type_ptr type_descriptor,
bool is_explicit_mapping) {
int iport, ipin, side, dump_pin_cnt;
int grid_pin_index, pin_height, side_pin_index;
t_port* cur_port;
t_pb_graph_node* top_pb_graph_node = NULL;
/* Check the file handler*/
@ -2294,8 +2345,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->input_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_ ",
convert_side_index_to_string(side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
dump_pin_cnt++;
side_pin_index++;
}
@ -2319,8 +2377,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->output_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_ ",
convert_side_index_to_string(side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
dump_pin_cnt++;
side_pin_index++;
}
@ -2344,8 +2409,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->clock_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_ ",
convert_side_index_to_string(side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
dump_pin_cnt++;
side_pin_index++;
}
@ -2362,7 +2434,8 @@ void dump_verilog_io_grid_block_subckt_pins(FILE* fp,
int x,
int y,
int z,
t_type_ptr type_descriptor) {
t_type_ptr type_descriptor,
bool is_explicit_mapping) {
int iport, ipin, side, dump_pin_cnt;
int grid_pin_index, pin_height, side_pin_index;
t_pb_graph_node* top_pb_graph_node = NULL;
@ -2464,7 +2537,8 @@ void dump_verilog_io_grid_block_subckt_pins(FILE* fp,
void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_dir,
int ix, int iy,
t_arch* arch) {
t_arch* arch,
bool is_explicit_mapping) {
int subckt_name_str_len = 0;
char* subckt_name = NULL;
int iz;
@ -2517,7 +2591,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
/* Comments: Grid [x][y]*/
fprintf(fp, "//----- Grid[%d][%d] type_descriptor: %s[%d] -----\n", ix, iy, grid[ix][iy].type->name, iz);
/* Print a NULL logic block...*/
dump_verilog_physical_block(cur_sram_orgz_info, fp, subckt_name, ix, iy, iz, grid[ix][iy].type);
dump_verilog_physical_block(cur_sram_orgz_info, fp, subckt_name, ix, iy, iz,
grid[ix][iy].type, is_explicit_mapping);
fprintf(fp, "//----- END -----\n\n");
}
@ -2531,23 +2606,23 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "module %s ( \n", gen_verilog_one_grid_module_name(ix, iy));
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
/* Pins */
/* Special Care for I/O grid */
if (IO_TYPE == grid[ix][iy].type) {
dump_verilog_io_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE);
dump_verilog_io_grid_pins(fp, ix, iy, FALSE, 0, TRUE, FALSE,is_explicit_mapping);
} else {
dump_verilog_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE);
dump_verilog_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE, is_explicit_mapping);
}
/* IO PAD */
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
iopad_verilog_model->grid_index_low[ix][iy],
iopad_verilog_model->grid_index_high[ix][iy] - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, is_explicit_mapping);
/* Print configuration ports */
/* Reserved configuration ports */
@ -2575,7 +2650,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_num_mem_bit,
get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info) - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT,
false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2603,15 +2679,15 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, " %s (", gen_verilog_one_block_instance_name(ix, iy, iz));
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
/* Print all the pins */
/* Special Care for I/O grid */
if (IO_TYPE == grid[ix][iy].type) {
dump_verilog_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type);
dump_verilog_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type, is_explicit_mapping);
} else {
dump_verilog_grid_block_subckt_pins(fp, iz, grid[ix][iy].type);
dump_verilog_grid_block_subckt_pins(fp, iz, grid[ix][iy].type, is_explicit_mapping);
}
/* Print configuration ports */
temp_reserved_conf_bits_msb = grid[ix][iy].type->pb_type->physical_mode_num_reserved_conf_bits;
@ -2623,7 +2699,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
temp_iopad_lsb,
temp_iopad_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
assert(!(0 > temp_conf_bits_msb - temp_conf_bits_lsb));
/* Reserved configuration ports */
if (0 < temp_reserved_conf_bits_msb) {
@ -2638,7 +2714,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "//---- SRAM ----\n");
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
temp_conf_bits_lsb, temp_conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
if (0 < (temp_conf_bits_msb - 1 - temp_conf_bits_lsb)) {
@ -2648,7 +2724,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
temp_conf_bits_lsb,
temp_conf_bits_msb - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT,
is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2687,7 +2764,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
*/
void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_dir,
t_arch* arch) {
t_arch* arch,
bool is_explicit_mapping) {
int ix, iy;
/* Check the grid*/
@ -2709,7 +2787,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
assert(IO_TYPE != grid[ix][iy].type);
/* Ensure a valid usage */
assert((0 == grid[ix][iy].usage)||(0 < grid[ix][iy].usage));
dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch);
dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy,
arch, is_explicit_mapping);
}
}
@ -2720,7 +2799,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
for (ix = 1; ix < (nx + 1); ix++) {
/* Ensure this is a io */
assert(IO_TYPE == grid[ix][iy].type);
dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch);
dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy,
arch, is_explicit_mapping);
}
/* Right side : x = nx + 1, y = 1 .. ny*/
@ -2728,7 +2808,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
for (iy = 1; iy < (ny + 1); iy++) {
/* Ensure this is a io */
assert(IO_TYPE == grid[ix][iy].type);
dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch);
dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy,
arch, is_explicit_mapping);
}
/* Bottom side : x = 1 .. nx + 1, y = 0 */
@ -2736,14 +2817,16 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
for (ix = 1; ix < (nx + 1); ix++) {
/* Ensure this is a io */
assert(IO_TYPE == grid[ix][iy].type);
dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch);
dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy,
arch, is_explicit_mapping);
}
/* Left side: x = 0, y = 1 .. ny*/
ix = 0;
for (iy = 1; iy < (ny + 1); iy++) {
/* Ensure this is a io */
assert(IO_TYPE == grid[ix][iy].type);
dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch);
dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy,
arch, is_explicit_mapping);
}
/* Output a header file for all the logic blocks */

33
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h
View File

@ -32,7 +32,8 @@ void dump_verilog_pb_type_ports(FILE* fp,
t_pb_type* cur_pb_type,
boolean dump_port_type,
boolean dump_last_comma,
boolean require_explicit_port_map);
boolean require_explicit_port_map,
bool is_full_name);
void dump_verilog_dangling_des_pb_graph_pin_interc(FILE* fp,
t_pb_graph_pin* des_pb_graph_pin,
@ -58,13 +59,15 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
char* parent_pin_prefix,
enum e_spice_pin2pin_interc_type pin2pin_interc_type,
t_pb_graph_pin* des_pb_graph_pin,
t_mode* cur_mode);
t_mode* cur_mode,
bool is_explicit_mapping);
void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* pin_prefix,
t_pb_graph_node* cur_pb_graph_node,
int select_mode_index);
int select_mode_index,
bool is_explicit_mapping);
void dump_verilog_pb_graph_primitive_node(FILE* fp,
char* subckt_prefix,
@ -78,13 +81,14 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf
t_pb_graph_node* prim_pb_graph_node,
int pb_index,
t_spice_model* verilog_model,
int is_idle);
bool is_explicit_mapping);
void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* subckt_prefix,
t_pb_graph_node* cur_pb_graph_node,
int pb_type_index);
int pb_type_index,
bool is_explicit_mapping);
void dump_verilog_block(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
@ -101,19 +105,23 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info,
int x,
int y,
int z,
t_type_ptr type_descriptor);
t_type_ptr type_descriptor,
bool is_explicit_mapping);
void dump_verilog_grid_pins(FILE* fp,
int x, int y,
boolean top_level,
boolean dump_port_type,
boolean dump_last_comma);
boolean dump_last_comma,
bool is_explicit_mapping);
void dump_verilog_io_grid_pins(FILE* fp,
int x, int y,
boolean top_level,
int border_side,
boolean dump_port_type,
boolean dump_last_comma);
boolean dump_last_comma,
bool is_explicit_mapping);
char* get_grid_block_subckt_name(int x,
int y,
@ -123,7 +131,8 @@ char* get_grid_block_subckt_name(int x,
void dump_verilog_grid_block_subckt_pins(FILE* fp,
int z,
t_type_ptr type_descriptor);
t_type_ptr type_descriptor,
bool is_explicit_mapping);
void dump_verilog_io_grid_block_subckt_pins(FILE* fp,
int x,
@ -138,7 +147,8 @@ void dump_verilog_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int ix, int iy,
t_arch* arch);
t_arch* arch,
bool is_explicit_mapping);
void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
@ -147,7 +157,8 @@ void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info,
t_type_ptr type_descriptor);
void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_dir, t_arch* arch);
char* subckt_dir, t_arch* arch,
bool is_explicit_mapping);
void rec_copy_name_mux_in_node(t_pb_graph_node* master_node,
t_pb_graph_node* target_node);

104
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -43,7 +43,8 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* verilog_model) {
t_spice_model* verilog_model,
bool is_explicit_mapping) {
int num_pad_port = 0; /* INOUT port */
t_spice_model_port** pad_ports = NULL;
int num_input_port = 0;
@ -122,7 +123,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "\n");
/* Only dump the global ports belonging to a spice_model
*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
@ -133,8 +134,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl);
/* print ports --> input ports */
dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE);
dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE, false);
/* IOPADs requires a specical port to output */
if (SPICE_MODEL_IOPAD == verilog_model->type) {
fprintf(fp, ",\n");
@ -172,7 +172,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_num_sram,
cur_num_sram + num_conf_bits - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -228,29 +228,28 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
/* Only dump the global ports belonging to a spice_model
* Disable recursive here !
*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, TRUE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
/* assert */
num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1);
/* print ports --> input ports */
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, verilog_model->dump_explicit_port_map);
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping));
/* IOPADs requires a specical port to output */
if (SPICE_MODEL_IOPAD == verilog_model->type) {
fprintf(fp, ",\n");
assert(1 == num_pad_port);
assert(NULL != pad_ports[0]);
/* Add explicit port mapping if required */
if (TRUE == verilog_model->dump_explicit_port_map) {
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
pad_ports[0]->lib_name);
}
/* Print inout port */
fprintf(fp, "%s%s[%d]", gio_inout_prefix,
verilog_model->prefix, verilog_model->cnt);
if (TRUE == verilog_model->dump_explicit_port_map) {
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
@ -264,7 +263,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
case SPICE_SRAM_SCAN_CHAIN:
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -274,7 +273,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
0, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
fprintf(fp, ")");
}
@ -285,7 +284,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ", ");
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -295,14 +294,14 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
1, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
fprintf(fp, ")");
}
break;
case SPICE_SRAM_MEMORY_BANK:
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -312,7 +311,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
0, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
fprintf(fp, ")");
}
/* Check if we have an inverterd prefix */
@ -322,7 +321,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ", ");
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -332,7 +331,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
1, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map)) {
&& (true == is_explicit_mapping)) {
fprintf(fp, ")");
}
break;
@ -370,7 +369,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, -1,
mem_model, cur_num_sram, cur_num_sram + num_sram - 1);
mem_model, cur_num_sram, cur_num_sram + num_sram - 1, my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_sram);
@ -404,7 +403,8 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* verilog_model) {
t_spice_model* verilog_model,
bool is_explicit_mapping) {
int i;
int lut_size = 0;
int num_input_port = 0;
@ -525,11 +525,11 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
formatted_subckt_prefix, cur_pb_type->name);
fprintf(fp, "\n");
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
/* Print inputs, outputs, inouts, clocks, NO SRAMs*/
dump_verilog_pb_type_ports(fp, port_prefix, 0, cur_pb_type, TRUE, TRUE, FALSE);
dump_verilog_pb_type_ports(fp, port_prefix, 0, cur_pb_type, TRUE, TRUE, FALSE, false);
/* Print SRAM ports */
cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl);
@ -558,7 +558,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_num_sram,
cur_num_sram + num_conf_bits - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -602,13 +602,13 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
* Only dump the global ports belonging to a spice_model
* DISABLE recursive here !
*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
/* Connect inputs*/
/* Connect outputs*/
fprintf(fp, "//----- Input and output ports -----\n");
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, verilog_model->dump_explicit_port_map);
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, "\n//----- SRAM ports -----\n");
/* check */
@ -620,41 +620,89 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
case SPICE_SRAM_STANDALONE:
break;
case SPICE_SRAM_SCAN_CHAIN:
if (true == is_explicit_mapping) {
fprintf(fp, ".sram_out( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".sram_outb( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
if (0 < num_mode_sram) {
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".mode_out( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".mode_outb( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
}
break;
case SPICE_SRAM_MEMORY_BANK:
if (true == is_explicit_mapping) {
fprintf(fp, ".sram_out( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".sram_outb( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
if (0 < num_mode_sram) {
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".mode_out( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
0, VERILOG_PORT_CONKT);
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
fprintf(fp, ".mode_outb( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
1, VERILOG_PORT_CONKT);
1, VERILOG_PORT_CONKT);
}
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
break;
default:
@ -680,7 +728,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, -1,
mem_model, cur_num_sram, cur_num_sram + num_sram - 1);
mem_model, cur_num_sram, cur_num_sram + num_sram - 1, is_explicit_mapping);
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_sram);

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.h
View File

@ -5,11 +5,13 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* spice_model);
t_spice_model* spice_model,
bool is_explicit_mapping);
void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* spice_model);
t_spice_model* spice_model,
bool is_explicit_mapping);

69
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c
View File

@ -284,7 +284,7 @@ void verilog_generate_one_report_timing_within_sb(FILE* fp,
fprintf(fp, "%s/",
rr_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_routing_pin(fp, rr_sb, src_rr_node);
dump_verilog_one_sb_routing_pin(fp, rr_sb, src_rr_node, false);
fprintf(fp, " -to ");
@ -326,7 +326,7 @@ void verilog_generate_one_report_timing_within_sb(FILE* fp,
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(cur_sb_info));
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node);
dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node, false);
fprintf(fp, " -to ");
@ -906,7 +906,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, "%s/",
src_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_routing_pin(fp, src_sb, drive_rr_node);
dump_verilog_one_sb_routing_pin(fp, src_sb, drive_rr_node, false);
/* Switch depends on the type of des_rr_node */
switch(des_rr_node->type) {
@ -1048,23 +1048,24 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
break;
case CHANX:
case CHANY: {
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
/* Get the coordinate of ending SB */
next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node);
const RRGSB& next_sb = device_rr_gsb.get_gsb(next_sb_coordinator);
fprintf(fp, " -to ");
/* output instance name */
fprintf(fp, "%s/",
next_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_chan_pin(fp, next_sb, src_rr_node, IN_PORT);
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
fprintf(fp, " -to ");
/* output instance name */
fprintf(fp, "%s/",
next_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_chan_pin(fp, next_sb, src_rr_node, IN_PORT);
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
}
/* Verification is done before the loops.*/
default:
break;
@ -1114,6 +1115,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
break;
}
/* Verification is done before the loops.*/
default:
break;
@ -1163,6 +1165,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
break;
}
/* Verification is done before the loops.*/
default:
break;
@ -1212,6 +1215,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
break;
}
/* Verification is done before the loops.*/
default:
break;
@ -1283,7 +1287,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(src_sb_info));
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_routing_pin(fp, src_sb_info, drive_rr_node);
dump_verilog_one_sb_routing_pin(fp, src_sb_info, drive_rr_node, false);
/* Switch depends on the type of des_rr_node */
switch(des_rr_node->type) {
@ -1427,6 +1431,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
/* Verification is done before the loops.*/
default:
break;
@ -1465,6 +1472,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
/* Verification is done before the loops.*/
default:
break;
@ -1503,6 +1513,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
/* Verification is done before the loops.*/
default:
break;
@ -1541,6 +1554,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
fprintf(fp, " -point_to_point");
fprintf(fp, " -unconstrained");
break;
/* Verification is done before the loops.*/
default:
break;
@ -1549,7 +1565,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,
}
}
if (NULL != rpt_name) {
if (NULL != rpt_name) {
fprintf(fp, " > %s\n", rpt_name);
} else {
fprintf(fp, "\n");
@ -2063,7 +2079,7 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
fprintf(fp, "%s/", rr_sb.gen_sb_verilog_instance_name());
/* output pin name */
dump_verilog_one_sb_routing_pin(fp, rr_sb,
wire_rr_node->drive_rr_nodes[iedge]);
wire_rr_node->drive_rr_nodes[iedge], false);
fprintf(fp, " -to ");
/* output instance name */
fprintf(fp, "%s/",
@ -2121,14 +2137,14 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
rr_sb.gen_sb_verilog_instance_name());
/* output pin name */
dump_verilog_one_sb_routing_pin(fp, rr_sb,
wire_rr_node->drive_rr_nodes[iedge]);
wire_rr_node->drive_rr_nodes[iedge], false);
fprintf(fp, " -to ");
/* output instance name */
fprintf(fp, "%s/",
next_sb.gen_sb_verilog_instance_name());
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_routing_pin(fp, next_sb,
wire_rr_node);
wire_rr_node, false);
/* Print through pins */
if (TRUE == sdc_opts.print_thru_pins) {
fprintf(fp, " -through_pins ");
@ -2229,7 +2245,8 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
gen_verilog_one_sb_instance_name(cur_sb_info));
/* output pin name */
dump_verilog_one_sb_routing_pin(fp, cur_sb_info,
wire_rr_node->drive_rr_nodes[iedge]);
wire_rr_node->drive_rr_nodes[iedge],
false);
fprintf(fp, " -to ");
/* output instance name */
fprintf(fp, "%s/",
@ -2273,14 +2290,14 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp,
gen_verilog_one_sb_instance_name(cur_sb_info));
/* output pin name */
dump_verilog_one_sb_routing_pin(fp, cur_sb_info,
wire_rr_node->drive_rr_nodes[iedge]);
wire_rr_node->drive_rr_nodes[iedge], false);
fprintf(fp, " -to ");
/* output instance name */
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(next_sb));
/* Find which side the ending pin locates, and determine the coordinate */
dump_verilog_one_sb_routing_pin(fp, next_sb,
wire_rr_node);
wire_rr_node, false);
/* Print through pins */
if (TRUE == sdc_opts.print_thru_pins) {
fprintf(fp, " -through_pins ");

351
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -44,7 +44,8 @@ static
void dump_verilog_routing_chan_subckt(char* verilog_dir,
char* subckt_dir,
size_t rr_chan_subckt_id,
const RRChan& rr_chan) {
const RRChan& rr_chan,
bool is_explicit_mapping) {
FILE* fp = NULL;
char* fname = NULL;
@ -78,7 +79,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir,
gen_verilog_one_routing_channel_module_name(rr_chan.get_type(), rr_chan_subckt_id, -1));
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
/* Inputs and outputs,
@ -170,7 +171,8 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
int num_segment) {
int num_segment,
bool is_explicit_mapping) {
int itrack, iseg, cost_index;
int chan_width = 0;
t_rr_node** chan_rr_nodes = NULL;
@ -215,7 +217,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir,
gen_verilog_one_routing_channel_module_name(chan_type, x, y));
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
/* Inputs and outputs,
@ -311,7 +313,8 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir,
void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type,
int pin_index, int side,
int x, int y,
boolean dump_port_type) {
boolean dump_port_type,
bool is_explicit_mapping) {
int height;
t_type_ptr type = NULL;
char* verilog_port_type = NULL;
@ -354,8 +357,15 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type,
/* fprintf(fp, "grid_%d__%d__pin_%d__%d__%d_ ", x, y, height, side, pin_index); */
if (TRUE == dump_port_type) {
fprintf(fp, "%s ", verilog_port_type);
is_explicit_mapping = false; /* Both cannot be true at the same time */
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE));
}
fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE));
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
if (TRUE == dump_port_type) {
fprintf(fp, ",\n");
}
@ -511,7 +521,8 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp,
enum e_side chan_side,
t_rr_node* cur_rr_node,
int actual_fan_in,
t_rr_node* drive_rr_node) {
t_rr_node* drive_rr_node,
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -554,7 +565,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp,
drive_rr_node->ptc_num,
rr_sb.get_opin_node_grid_side(drive_rr_node),
grid_x, grid_y,
FALSE); /* Do not dump the direction of the port! */
FALSE, false); /* Do not dump the direction of the port! */
break;
case CHANX:
case CHANY:
@ -600,7 +611,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp,
int chan_side,
t_rr_node* cur_rr_node,
int actual_fan_in,
t_rr_node* drive_rr_node) {
t_rr_node* drive_rr_node,
bool is_explicit_mapping) {
int side, index;
int grid_x, grid_y;
char* chan_name = NULL;
@ -655,7 +667,7 @@ void dump_verilog_switch_box_short_interc(FILE* fp,
drive_rr_node->ptc_num,
cur_sb_info->opin_rr_node_grid_side[side][index],
grid_x, grid_y,
FALSE); /* Do not dump the direction of the port! */
FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */
break;
case CHANX:
case CHANY:
@ -694,7 +706,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* cur_rr_node,
int mux_size,
t_rr_node** drive_rr_nodes,
int switch_index) {
int switch_index,
bool is_explicit_mapping) {
int inode, side, index, input_cnt = 0;
int grid_x, grid_y;
t_spice_model* verilog_model = NULL;
@ -759,7 +772,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt);
dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num,
cur_sb_info->opin_rr_node_grid_side[side][index],
grid_x, grid_y, FALSE);
grid_x, grid_y, FALSE, is_explicit_mapping);
fprintf(fp, ";\n");
input_cnt++;
break;
@ -823,21 +836,35 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
fprintf(fp, "%s_size%d_%d_inbus, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".in(");
}
fprintf(fp, "%s_size%d_%d_inbus",
verilog_model->prefix, mux_size, verilog_model->cnt);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, " ,");
/* Output port */
if (true == is_explicit_mapping) {
fprintf(fp, ".out(");
}
dump_verilog_switch_box_chan_port(fp, cur_sb_info, chan_side, cur_rr_node, OUT_PORT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Add a comma because dump_verilog_switch_box_chan_port does not add so */
fprintf(fp, ", ");
/* Different design technology requires different configuration bus! */
dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info,
mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits);
mux_size, cur_num_sram,
num_mux_reserved_conf_bits, num_mux_conf_bits,
is_explicit_mapping);
fprintf(fp, ");\n");
@ -901,7 +928,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1);
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits);
@ -941,7 +969,8 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* cur_rr_node,
int mux_size,
t_rr_node** drive_rr_nodes,
int switch_index) {
int switch_index,
bool is_explicit_mapping) {
int input_cnt = 0;
t_spice_model* verilog_model = NULL;
int mux_level, path_id, cur_num_sram;
@ -999,7 +1028,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt);
dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num,
rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]),
grid_x, grid_y, FALSE);
grid_x, grid_y, FALSE, false);
fprintf(fp, ";\n");
input_cnt++;
break;
@ -1063,21 +1092,35 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".in(");
fprintf(fp, "%s_size%d_%d_inbus), ",
verilog_model->prefix, mux_size, verilog_model->cnt);
}
else {
fprintf(fp, "%s_size%d_%d_inbus, ",
verilog_model->prefix, mux_size, verilog_model->cnt);
}
/* Output port */
dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT);
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".out(");
dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT);
fprintf(fp, ")");
}
else {
dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT);
}
/* Add a comma because dump_verilog_switch_box_chan_port does not add so */
fprintf(fp, ", ");
/* Different design technology requires different configuration bus! */
dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info,
mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits);
mux_size, cur_num_sram, num_mux_reserved_conf_bits,
num_mux_conf_bits, is_explicit_mapping);
fprintf(fp, ");\n");
@ -1140,8 +1183,10 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
mem_subckt_name = generate_verilog_mux_subckt_name(verilog_model, mux_size, verilog_mem_posfix);
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info,
verilog_model, mux_size, mem_model,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
is_explicit_mapping);
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits);
@ -1326,7 +1371,8 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_sb* cur_sb_info,
int chan_side,
t_rr_node* cur_rr_node) {
t_rr_node* cur_rr_node,
bool is_explicit_mapping) {
int sb_x, sb_y;
int num_drive_rr_nodes = 0;
t_rr_node** drive_rr_nodes = NULL;
@ -1360,16 +1406,18 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
if (0 == num_drive_rr_nodes) {
/* Print a special direct connection*/
dump_verilog_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node,
num_drive_rr_nodes, cur_rr_node);
num_drive_rr_nodes, cur_rr_node, is_explicit_mapping);
} else if (1 == num_drive_rr_nodes) {
/* Print a direct connection*/
dump_verilog_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node,
num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]);
num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID],
is_explicit_mapping);
} else if (1 < num_drive_rr_nodes) {
/* Print the multiplexer, fan_in >= 2 */
dump_verilog_switch_box_mux(cur_sram_orgz_info, fp, cur_sb_info, chan_side, cur_rr_node,
num_drive_rr_nodes, drive_rr_nodes,
cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]);
cur_rr_node->drive_switches[DEFAULT_SWITCH_ID],
is_explicit_mapping);
} /*Nothing should be done else*/
/* Free */
@ -1382,7 +1430,8 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
const RRGSB& rr_sb,
enum e_side chan_side,
size_t chan_node_id) {
size_t chan_node_id,
bool is_explicit_mapping) {
int num_drive_rr_nodes = 0;
t_rr_node** drive_rr_nodes = NULL;
@ -1409,16 +1458,19 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
if (0 == num_drive_rr_nodes) {
/* Print a special direct connection*/
dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node,
num_drive_rr_nodes, cur_rr_node);
num_drive_rr_nodes, cur_rr_node,
is_explicit_mapping);
} else if (1 == num_drive_rr_nodes) {
/* Print a direct connection*/
dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node,
num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]);
num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID],
is_explicit_mapping);
} else if (1 < num_drive_rr_nodes) {
/* Print the multiplexer, fan_in >= 2 */
dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node,
num_drive_rr_nodes, drive_rr_nodes,
cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]);
cur_rr_node->drive_switches[DEFAULT_SWITCH_ID],
is_explicit_mapping);
} /*Nothing should be done else*/
/* Free */
@ -1659,7 +1711,8 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp,
const RRGSB& rr_sb,
enum e_side sb_side,
size_t seg_id,
boolean dump_port_type) {
boolean dump_port_type,
bool is_explicit_mapping) {
/* Check file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,
@ -1691,11 +1744,22 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp,
fprintf(fp, " ");
if (TRUE == dump_port_type) {
fprintf(fp, "output ");
is_explicit_mapping = false; /* Both cannot be true together */
}
fprintf(fp, "%s,\n",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
}
fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
break;
case IN_PORT:
/* if this is not the specified side, we only consider input ports */
@ -1706,10 +1770,20 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp,
if (TRUE == dump_port_type) {
fprintf(fp, "input ");
}
fprintf(fp, "%s,\n",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
}
fprintf(fp, "%s",
gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack),
port_coordinator.get_x(), port_coordinator.get_y(), itrack,
rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)));
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,
@ -1727,7 +1801,7 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp,
rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode),
rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow,
rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow,
dump_port_type); /* Dump the direction of the port ! */
dump_port_type, is_explicit_mapping); /* Dump the direction of the port ! */
if (FALSE == dump_port_type) {
fprintf(fp, ",\n");
}
@ -1778,7 +1852,8 @@ static
void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
size_t module_id, size_t seg_id,
const RRGSB& rr_sb, enum e_side side) {
const RRGSB& rr_sb, enum e_side side,
bool is_explicit_mapping) {
FILE* fp = NULL;
char* fname = NULL;
Side side_manager(side);
@ -1819,11 +1894,13 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_side_module_name(side, seg_id));
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side, seg_id, TRUE);
dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side,
seg_id, TRUE,
false);
/* Put down configuration port */
/* output of each configuration bit */
@ -1849,7 +1926,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_num_sram,
esti_sram_cnt - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -1874,7 +1951,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
}
dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb,
side_manager.get_side(),
itrack);
itrack, is_explicit_mapping);
}
}
@ -1924,7 +2001,8 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr
static
void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
const RRGSB& rr_sb) {
const RRGSB& rr_sb,
bool is_explicit_mapping) {
FILE* fp = NULL;
char* fname = NULL;
@ -1951,7 +2029,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name());
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
@ -1991,7 +2069,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode),
rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow,
rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow,
TRUE); /* Dump the direction of the port ! */
TRUE, is_explicit_mapping); /* Dump the direction of the port ! */
}
}
@ -2022,7 +2100,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb(),
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT,
false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2068,11 +2147,11 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
rr_gsb.gen_sb_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]),
rr_gsb.gen_sb_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg]));
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_gsb, side_manager.get_side(), seg_ids[iseg], FALSE);
dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_gsb, side_manager.get_side(), seg_ids[iseg], FALSE, is_explicit_mapping);
/* Put down configuration port */
/* output of each configuration bit */
@ -2088,7 +2167,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
cur_sram_lsb,
cur_sram_msb,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
/* Dump ports only visible during formal verification*/
if (0 < side_num_conf_bits) {
@ -2098,7 +2177,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sram_lsb,
cur_sram_msb,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2166,7 +2245,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
static
void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
const RRGSB& rr_sb) {
const RRGSB& rr_sb,
bool is_explicit_mapping) {
FILE* fp = NULL;
char* fname = NULL;
@ -2194,7 +2274,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name());
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -2233,7 +2313,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode),
rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow,
rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow,
TRUE); /* Dump the direction of the port ! */
TRUE, is_explicit_mapping); /* Dump the direction of the port ! */
}
}
@ -2261,7 +2341,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb(),
VERILOG_PORT_OUTPUT);
VERILOG_PORT_OUTPUT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2284,7 +2364,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb,
side_manager.get_side(),
itrack);
itrack, is_explicit_mapping);
}
}
}
@ -2347,7 +2427,8 @@ static
void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
t_sb* cur_sb_info,
boolean compact_routing_hierarchy) {
boolean compact_routing_hierarchy,
bool is_explicit_mapping) {
int itrack, inode, side, ix, iy, x, y;
int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt;
FILE* fp = NULL;
@ -2398,7 +2479,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", gen_verilog_one_sb_module_name(cur_sb_info));
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -2434,7 +2515,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
cur_sb_info->opin_rr_node_grid_side[side][inode],
cur_sb_info->opin_rr_node[side][inode]->xlow,
cur_sb_info->opin_rr_node[side][inode]->ylow,
TRUE); /* Dump the direction of the port ! */
TRUE, is_explicit_mapping); /* Dump the direction of the port ! */
}
}
@ -2461,7 +2542,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sb_info->conf_bits_lsb,
cur_sb_info->conf_bits_msb - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2480,7 +2561,9 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
||(CHANY == cur_sb_info->chan_rr_node[side][itrack]->type));
/* We care INC_DIRECTION tracks at this side*/
if (OUT_PORT == cur_sb_info->chan_rr_node_direction[side][itrack]) {
dump_verilog_switch_box_interc(cur_sram_orgz_info, fp, cur_sb_info, side, cur_sb_info->chan_rr_node[side][itrack]);
dump_verilog_switch_box_interc(cur_sram_orgz_info, fp, cur_sb_info, side,
cur_sb_info->chan_rr_node[side][itrack],
is_explicit_mapping);
}
}
}
@ -2680,7 +2763,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp,
rr_gsb.get_ipin_node(side, index)->ptc_num,
rr_gsb.get_ipin_node_grid_side(side, index),
xlow, ylow, /* Coordinator of Grid */
FALSE); /* Do not specify the direction of this pin */
FALSE, false); /* Do not specify the direction of this pin */
/* End */
fprintf(fp, ";\n");
@ -2692,7 +2775,8 @@ void dump_verilog_connection_box_short_interc(FILE* fp,
/* SRC rr_node is the IPIN of a grid.*/
void dump_verilog_connection_box_short_interc(FILE* fp,
t_cb* cur_cb_info,
t_rr_node* src_rr_node) {
t_rr_node* src_rr_node,
bool is_explicit_mapping) {
t_rr_node* drive_rr_node = NULL;
int iedge, check_flag;
int xlow, ylow, height, side, index;
@ -2756,7 +2840,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp,
cur_cb_info->ipin_rr_node[side][index]->ptc_num,
cur_cb_info->ipin_rr_node_grid_side[side][index],
xlow, ylow, /* Coordinator of Grid */
FALSE); /* Do not specify the direction of this pin */
FALSE, false); /* Do not specify the direction of this pin */
/* End */
fprintf(fp, ";\n");
@ -2768,7 +2852,8 @@ static
void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_rr_node* src_rr_node) {
t_rr_node* src_rr_node,
bool is_explicit_mapping) {
int mux_size, cur_num_sram, input_cnt = 0;
t_rr_node** drive_rr_nodes = NULL;
int mux_level, path_id, switch_index;
@ -2881,13 +2966,20 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
/* connect to input bus*/
fprintf(fp, "%s_size%d_%d_inbus,",
if (true == is_explicit_mapping) {
fprintf(fp, ".in(");
}
fprintf(fp, "%s_size%d_%d_inbus",
verilog_model->prefix, mux_size, verilog_model->cnt);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* output port*/
xlow = src_rr_node->xlow;
@ -2898,16 +2990,24 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
rr_gsb.get_node_side_and_index(src_rr_node, OUT_PORT, &side, &index);
/* We need to be sure that drive_rr_node is part of the CB */
assert((-1 != index)&&(NUM_SIDES != side));
if (true == is_explicit_mapping) {
fprintf(fp, ".out(");
}
dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an output of a connection box */
rr_gsb.get_ipin_node(side, index)->ptc_num,
rr_gsb.get_ipin_node_grid_side(side, index),
xlow, ylow, /* Coordinator of Grid */
FALSE); /* Do not specify the direction of port */
FALSE, false); /* Do not specify the direction of port */
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* Different design technology requires different configuration bus! */
dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info,
mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits);
mux_size, cur_num_sram,
num_mux_reserved_conf_bits,
num_mux_conf_bits, is_explicit_mapping);
fprintf(fp, ");\n");
@ -2960,7 +3060,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1);
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits);
@ -2995,7 +3096,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb* cur_cb_info,
t_rr_node* src_rr_node) {
t_rr_node* src_rr_node,
bool is_explicit_mapping) {
int mux_size, cur_num_sram, input_cnt = 0;
t_rr_node** drive_rr_nodes = NULL;
int inode, mux_level, path_id, switch_index;
@ -3102,7 +3204,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram,
cur_num_sram + num_mux_conf_bits - 1);
fprintf(fp, "`endif\n");
fprintf(fp, "is_explicit_mappingf\n");
/* Call the MUX SPICE model */
@ -3111,13 +3213,20 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
verilog_model->prefix, mux_size, verilog_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
/* connect to input bus*/
fprintf(fp, "%s_size%d_%d_inbus,",
if (true == is_explicit_mapping) {
fprintf(fp, ".in(");
}
fprintf(fp, "%s_size%d_%d_inbus",
verilog_model->prefix, mux_size, verilog_model->cnt);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* output port*/
xlow = src_rr_node->xlow;
@ -3128,16 +3237,24 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
get_rr_node_side_and_index_in_cb_info(src_rr_node, (*cur_cb_info), OUT_PORT, &side, &index);
/* We need to be sure that drive_rr_node is part of the CB */
assert((-1 != index)&&(-1 != side));
if (true == is_explicit_mapping) {
fprintf(fp, ".out(");
}
dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an output of a connection box */
cur_cb_info->ipin_rr_node[side][index]->ptc_num,
cur_cb_info->ipin_rr_node_grid_side[side][index],
xlow, ylow, /* Coordinator of Grid */
FALSE); /* Do not specify the direction of port */
FALSE, false); /* Do not specify the direction of port */
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* Different design technology requires different configuration bus! */
dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info,
mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits);
mux_size, cur_num_sram,
num_mux_reserved_conf_bits,
num_mux_conf_bits, is_explicit_mapping);
fprintf(fp, ");\n");
@ -3190,7 +3307,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s %s_%d_ ( ",
mem_subckt_name, mem_subckt_name, verilog_model->cnt);
dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1);
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, ");\n");
/* update the number of memory bits */
update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits);
@ -3224,7 +3342,8 @@ static
void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
const RRGSB& rr_gsb, t_rr_type cb_type,
t_rr_node* src_rr_node) {
t_rr_node* src_rr_node,
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -3237,7 +3356,8 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node);
} else if (1 < src_rr_node->fan_in) {
/* Print the multiplexer, fan_in >= 2 */
dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type, src_rr_node);
dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type,
src_rr_node, is_explicit_mapping);
} /*Nothing should be done else*/
return;
@ -3247,7 +3367,8 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb* cur_cb_info,
t_rr_node* src_rr_node) {
t_rr_node* src_rr_node,
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -3261,10 +3382,11 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
if (1 == src_rr_node->fan_in) {
/* Print a direct connection*/
dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node);
dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node, is_explicit_mapping);
} else if (1 < src_rr_node->fan_in) {
/* Print the multiplexer, fan_in >= 2 */
dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, src_rr_node);
dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info,
src_rr_node, is_explicit_mapping);
} /*Nothing should be done else*/
return;
@ -3389,7 +3511,8 @@ int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_o
static
void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
const RRGSB& rr_cb, t_rr_type cb_type) {
const RRGSB& rr_cb, t_rr_type cb_type,
bool is_explicit_mapping) {
FILE* fp = NULL;
char* fname = NULL;
int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt;
@ -3427,7 +3550,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra
fprintf(fp, "%s ", rr_gsb.gen_cb_verilog_module_name(cb_type));
fprintf(fp, "(\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
/* Print the ports of channels*/
@ -3450,7 +3573,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra
rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode),
rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow,
rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow,
TRUE);
TRUE, false);
}
}
@ -3479,7 +3602,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_gsb.get_cb_conf_bits_lsb(cb_type),
rr_gsb.get_cb_conf_bits_msb(cb_type),
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -3499,7 +3622,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra
enum e_side cb_ipin_side = cb_ipin_sides[iside];
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
dump_verilog_connection_box_interc(cur_sram_orgz_info, fp, rr_gsb, cb_type,
rr_gsb.get_ipin_node(cb_ipin_side, inode));
rr_gsb.get_ipin_node(cb_ipin_side, inode),
is_explicit_mapping);
}
}
@ -3552,7 +3676,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra
void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
t_cb* cur_cb_info,
boolean compact_routing_hierarchy) {
boolean compact_routing_hierarchy,
bool is_explicit_mapping) {
int itrack, inode, side, x, y;
int side_cnt = 0;
FILE* fp = NULL;
@ -3627,7 +3752,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
fprintf(fp, "(\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
/* Print the ports of channels*/
@ -3668,7 +3793,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
cur_cb_info->ipin_rr_node_grid_side[side][inode],
cur_cb_info->ipin_rr_node[side][inode]->xlow,
cur_cb_info->ipin_rr_node[side][inode]->ylow,
TRUE);
TRUE, is_explicit_mapping);
}
}
@ -3699,7 +3824,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_cb_info->conf_bits_lsb,
cur_cb_info->conf_bits_msb - 1,
VERILOG_PORT_INPUT);
VERILOG_PORT_INPUT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -3725,7 +3850,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
assert(NULL != cur_cb_info->ipin_rr_node[side]);
for (inode = 0; inode < cur_cb_info->num_ipin_rr_nodes[side]; inode++) {
dump_verilog_connection_box_interc(cur_sram_orgz_info, fp, cur_cb_info,
cur_cb_info->ipin_rr_node[side][inode]);
cur_cb_info->ipin_rr_node[side][inode],
is_explicit_mapping);
}
}
@ -3769,9 +3895,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
boolean compact_routing_hierarchy) {
t_fpga_spice_opts FPGA_SPICE_Opts) {
assert(UNI_DIRECTIONAL == routing_arch->directionality);
boolean compact_routing_hierarchy = FPGA_SPICE_Opts.compact_routing_hierarchy;
boolean explicit_port_mapping = FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog;
/* Two major tasks:
* 1. Generate sub-circuits for Routing Channels
* 2. Generate sub-circuits for Switch Boxes
@ -3796,13 +3924,13 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
/* X - channels [1...nx][0..ny]*/
for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANX); ++ichan) {
dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir,
ichan, device_rr_chan.get_module(CHANX, ichan));
ichan, device_rr_chan.get_module(CHANX, ichan), explicit_port_mapping);
}
/* Y - channels [1...ny][0..nx]*/
vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n");
for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANY); ++ichan) {
dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir,
ichan, device_rr_chan.get_module(CHANY, ichan));
ichan, device_rr_chan.get_module(CHANY, ichan), explicit_port_mapping);
}
} else {
/* Output the full array of routing channels */
@ -3811,7 +3939,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
for (int ix = 1; ix < (nx + 1); ix++) {
dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANX,
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data,
arch.num_segments);
arch.num_segments, explicit_port_mapping);
}
}
/* Y - channels [1...ny][0..nx]*/
@ -3820,7 +3948,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
for (int iy = 1; iy < (ny + 1); iy++) {
dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANY,
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data,
arch.num_segments);
arch.num_segments, explicit_port_mapping);
}
}
}
@ -3837,7 +3965,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_submodule(side_manager.get_side(), iseg); ++isb) {
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_submodule(isb, side_manager.get_side(), iseg);
size_t seg_id = device_rr_gsb.get_segment_id(iseg);
dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side());
dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side(), explicit_port_mapping);
}
}
}
@ -3845,7 +3973,8 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
/* Output unique modules */
for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror);
dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir,
subckt_dir, unique_mirror, explicit_port_mapping);
}
/* Restore sram_orgz_info to the base */
@ -3865,8 +3994,10 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
for (int iy = 0; iy < (ny + 1); iy++) {
/* vpr_printf(TIO_MESSAGE_INFO, "Writing Switch Boxes[%d][%d]...\n", ix, iy); */
update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models);
dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(sb_info[ix][iy]),
compact_routing_hierarchy);
dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir,
subckt_dir, &(sb_info[ix][iy]),
compact_routing_hierarchy,
explicit_port_mapping);
update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models);
}
}
@ -3882,13 +4013,17 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
/* X - channels [1...nx][0..ny]*/
for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX);
dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info,
verilog_dir, subckt_dir, unique_mirror, CHANX,
explicit_port_mapping);
}
/* Y - channels [1...ny][0..nx]*/
for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY);
dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info,
verilog_dir, subckt_dir, unique_mirror, CHANY,
explicit_port_mapping);
}
/* Restore sram_orgz_info to the base */
@ -3914,8 +4049,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
update_spice_models_routing_index_low(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models);
if ((TRUE == is_cb_exist(CHANX, ix, iy))
&&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) {
dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cbx_info[ix][iy]),
compact_routing_hierarchy);
dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info,
verilog_dir, subckt_dir,
&(cbx_info[ix][iy]),
compact_routing_hierarchy,
explicit_port_mapping);
}
update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models);
}
@ -3927,8 +4065,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
update_spice_models_routing_index_low(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models);
if ((TRUE == is_cb_exist(CHANY, ix, iy))
&&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) {
dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cby_info[ix][iy]),
compact_routing_hierarchy);
dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info,
verilog_dir, subckt_dir,
&(cby_info[ix][iy]),
compact_routing_hierarchy,
explicit_port_mapping);
}
update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models);
}

29
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h
View File

@ -14,7 +14,8 @@ void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info,
void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type,
int pin_index, int side,
int x, int y,
boolean dump_port_type);
boolean dump_port_type,
bool is_explicit_mapping);
void dump_verilog_grid_side_pins(FILE* fp,
t_rr_type pin_type, int x, int y, int side,
@ -31,7 +32,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp,
int chan_side,
t_rr_node* cur_rr_node,
int actual_fan_in,
t_rr_node* drive_rr_node);
t_rr_node* drive_rr_node,
bool is_explicit_mapping);
void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
@ -40,7 +42,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* cur_rr_node,
int mux_size,
t_rr_node** drive_rr_nodes,
int switch_index);
int switch_index,
bool is_explicit_mapping);
int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_sb cur_sb_info, int chan_side,
@ -54,7 +57,8 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_sb* cur_sb_info,
int chan_side,
t_rr_node* cur_rr_node);
t_rr_node* cur_rr_node,
bool is_explicit_mapping);
int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_sb cur_sb_info);
@ -68,22 +72,26 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy);
boolean compact_routing_hierarchy,
bool is_explicit_mapping);
void dump_verilog_connection_box_short_interc(FILE* fp,
t_cb* cur_cb_info,
t_rr_node* src_rr_node);
t_rr_node* src_rr_node,
bool is_explicit_mapping);
void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb* cur_cb_info,
t_rr_node* src_rr_node);
t_rr_node* src_rr_node,
bool is_explicit_mapping);
void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb* cur_cb_info,
t_rr_node* src_rr_node);
t_rr_node* src_rr_node,
bool is_explicit_mapping);
int count_verilog_connection_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
@ -121,7 +129,8 @@ int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_o
void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
t_cb* cur_cb_info,
boolean compact_routing_hierarchy);
boolean compact_routing_hierarchy,
bool is_explicit_mapping);
void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
@ -132,6 +141,6 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
boolean compact_routing_hierarchy);
t_fpga_spice_opts FPGA_SPICE_Opts);
#endif

18
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -468,7 +468,7 @@ void verilog_generate_sdc_constrain_one_sb_path(FILE* fp,
fprintf(fp, " -from ");
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(cur_sb_info));
dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node);
dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node, false);
fprintf(fp, " -to ");
@ -513,7 +513,7 @@ void verilog_generate_sdc_constrain_one_sb_path(FILE* fp,
fprintf(fp, " -from ");
fprintf(fp, "%s/",
rr_gsb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_routing_pin(fp, rr_gsb, src_rr_node);
dump_verilog_one_sb_routing_pin(fp, rr_gsb, src_rr_node, false);
fprintf(fp, " -to ");
@ -638,7 +638,7 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp,
des_rr_node_grid_side,
des_rr_node->xlow,
des_rr_node->ylow,
FALSE);
FALSE, false);
/* If src_node == des_node, this is a metal wire */
fprintf(fp, " %.2g", tmax);
@ -721,7 +721,7 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp,
des_rr_node_grid_side,
mirror_ipin_node->xlow,
mirror_ipin_node->ylow,
FALSE);
FALSE, false);
/* If src_node == des_node, this is a metal wire */
fprintf(fp, " %.2g", tmax);
@ -1639,7 +1639,8 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp) {
fprintf(fp, "%s/",
rr_sb.gen_sb_verilog_instance_name());
dump_verilog_one_sb_routing_pin(fp, rr_sb,
rr_sb.get_opin_node(side_manager.get_side(), inode));
rr_sb.get_opin_node(side_manager.get_side(),
inode), false);
fprintf(fp, "\n");
}
}
@ -1708,7 +1709,8 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp,
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(cur_sb_info));
dump_verilog_one_sb_routing_pin(fp, cur_sb_info,
cur_sb_info->opin_rr_node[side][inode]);
cur_sb_info->opin_rr_node[side][inode],
false);
fprintf(fp, "\n");
}
}
@ -1758,7 +1760,7 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp,
rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode),
ipin_node->xlow,
ipin_node->ylow,
FALSE); /* Do not specify direction of port */
FALSE, false); /* Do not specify direction of port */
fprintf(fp, "\n");
}
}
@ -1816,7 +1818,7 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp,
cur_cb_info->ipin_rr_node_grid_side[side][inode],
cur_cb_info->ipin_rr_node[side][inode]->xlow,
cur_cb_info->ipin_rr_node[side][inode]->ylow,
FALSE); /* Do not specify direction of port */
FALSE, false); /* Do not specify direction of port */
fprintf(fp, "\n");
}
}

263
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -1153,7 +1153,8 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
char* mux_basis_subckt_name,
t_spice_model spice_model,
t_spice_mux_arch spice_mux_arch,
int num_sram_port, t_spice_model_port** sram_port) {
int num_sram_port, t_spice_model_port** sram_port,
bool is_explicit_mapping) {
int i, j, level, nextlevel;
int nextj, out_idx;
int mux_basis_cnt = 0;
@ -1225,17 +1226,41 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
/* Each basis mux2to1: <given_name> <input0> <input1> <output> <sram> <sram_inv> svdd sgnd <subckt_name> */
fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".in(");
}
/* For intermediate buffers */
if (TRUE == inter_buf_loc[level]) {
fprintf(fp, "mux2_l%d_in_buf[%d:%d], ", level, j, nextj); /* input0 input1 */
fprintf(fp, "mux2_l%d_in_buf[%d:%d]", level, j, nextj); /* input0 input1 */
} else {
fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */
fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, nextj); /* input0 input1 */
}
if (true == is_explicit_mapping) {
fprintf(fp, "), .out(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */
if (true == is_explicit_mapping) {
fprintf(fp, "), .mem(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */
if (true == is_explicit_mapping) {
fprintf(fp, "), .mem_inv(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "%s_inv[%d]", sram_port[0]->prefix, i); /* sram_inv */
if (true == is_explicit_mapping) {
fprintf(fp, "));\n");
} else {
fprintf(fp, ");\n");
}
fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */
fprintf(fp, "%s[%d], %s_inv[%d]);\n", sram_port[0]->prefix, i, sram_port[0]->prefix, i); /* sram sram_inv */
/* For intermediate buffers */
if (TRUE == inter_buf_loc[nextlevel]) {
/* Find the input port, output port, and sram port*/
@ -1302,7 +1327,8 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp,
char* mux_special_basis_subckt_name,
t_spice_model spice_model,
t_spice_mux_arch spice_mux_arch,
int num_sram_port, t_spice_model_port** sram_port) {
int num_sram_port, t_spice_model_port** sram_port,
bool is_explicit_mapping) {
int i, j, level, nextlevel, sram_idx;
int out_idx;
int mux_basis_cnt = 0;
@ -1348,14 +1374,36 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp,
/* Print the special basis */
fprintf(fp, "%s special_basis(", mux_special_basis_subckt_name);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */
fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */
fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ",
sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1,
if (true == is_explicit_mapping) {
fprintf(fp, ".in(");
}
fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, j + cur_num_input_basis - 1); /* input0 input1 */
if (true == is_explicit_mapping) {
fprintf(fp, "), .out(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */
if (true == is_explicit_mapping) {
fprintf(fp, "), .mem(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "%s[%d:%d]",
sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1);
if (true == is_explicit_mapping) {
fprintf(fp, "), .mem_inv(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "%s_inv[%d:%d]",
sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ");\n");
special_basis_cnt++;
}
@ -1365,16 +1413,38 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp,
fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */
fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */
fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */
if (true == is_explicit_mapping) {
fprintf(fp, ".in(");
}
fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, j + cur_num_input_basis - 1); /* input0 input1 */
if (true == is_explicit_mapping) {
fprintf(fp, "), .out(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */
/* Print number of sram bits for this basis */
fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ",
sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1,
if (true == is_explicit_mapping) {
fprintf(fp, "), .mem(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "%s[%d:%d]",
sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1);
fprintf(fp, ");\n");
if (true == is_explicit_mapping) {
fprintf(fp, "), .mem_inv(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "%s_inv[%d:%d]",
sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ");");
fprintf(fp, "\n");
/* Update the counter */
mux_basis_cnt++;
@ -1393,7 +1463,8 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp,
char* mux_basis_subckt_name,
t_spice_model spice_model,
t_spice_mux_arch spice_mux_arch,
int num_sram_port, t_spice_model_port** sram_port) {
int num_sram_port, t_spice_model_port** sram_port,
bool is_explicit_mapping) {
/* Make sure we have a valid file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__);
@ -1407,23 +1478,61 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp,
fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE,
my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
fprintf(fp, "//----- MUX inputs -----\n");
fprintf(fp, "mux2_l%d_in[0:%d], ", 1, spice_mux_arch.num_input - 1); /* input0 */
fprintf(fp, "mux2_l%d_in[%d], ", 0, 0); /* output */
if (true == is_explicit_mapping) {
fprintf(fp, ".in(");
}
fprintf(fp, "mux2_l%d_in[0:%d]", 1, spice_mux_arch.num_input - 1); /* input0 */
if (true == is_explicit_mapping) {
fprintf(fp, "), .out(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "mux2_l%d_in[%d]", 0, 0); /* output */
if (true == is_explicit_mapping) {
fprintf(fp, "),");
} else {
fprintf(fp, ",");
}
fprintf(fp, "\n");
fprintf(fp, "//----- SRAM ports -----\n");
/* Special basis for 2-input MUX, there is only one configuration bit */
if (2 == spice_mux_arch.num_input) {
fprintf(fp, "%s[0:%d], %s_inv[0:%d] ",
sram_port[0]->prefix, 0,
sram_port[0]->prefix, 0); /* sram sram_inv */
if (true == is_explicit_mapping) {
fprintf(fp, ".mem(");
}
fprintf(fp, "%s[0:%d]",
sram_port[0]->prefix, 0); /* sram */
if (true == is_explicit_mapping) {
fprintf(fp, "), .mem_inv(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "%s_inv[0:%d]",
sram_port[0]->prefix, 0); /* sram_inv */
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
} else {
fprintf(fp, "%s[0:%d], %s_inv[0:%d] ",
sram_port[0]->prefix, spice_mux_arch.num_input - 1,
sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram sram_inv */
if (true == is_explicit_mapping) {
fprintf(fp, ".mem(");
}
fprintf(fp, "%s[0:%d]",
sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram */
if (true == is_explicit_mapping) {
fprintf(fp, "), .mem_inv(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "%s_inv[0:%d]",
sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram_inv */
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
}
fprintf(fp, "\n");
fprintf(fp, ");\n");
@ -1434,7 +1543,8 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp,
void dump_verilog_cmos_mux_submodule(FILE* fp,
int mux_size,
t_spice_model spice_model,
t_spice_mux_arch spice_mux_arch) {
t_spice_mux_arch spice_mux_arch,
bool is_explicit_mapping) {
int i, num_conf_bits, iport, ipin, num_mode_bits;
int num_input_port = 0;
int num_output_port = 0;
@ -1541,7 +1651,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
} else {
fprintf(fp, "//----- CMOS MUX info: spice_model_name=%s, size=%d, structure: %s -----\n",
spice_model.name, mux_size, gen_str_spice_model_structure(spice_model.design_tech_info.mux_info->structure));
fprintf(fp, "module %s (",
fprintf(fp, "module %s (\n",
gen_verilog_one_mux_module_name(&spice_model, mux_size));
/* Print input ports*/
fprintf(fp, "input wire [0:%d] %s,\n", mux_size - 1, input_port[0]->prefix);
@ -1568,15 +1678,17 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
switch (cur_mux_structure) {
case SPICE_MODEL_STRUCTURE_TREE:
dump_verilog_cmos_mux_tree_structure(fp, mux_basis_subckt_name,
spice_model, spice_mux_arch, num_sram_port, sram_port);
spice_model, spice_mux_arch, num_sram_port, sram_port, is_explicit_mapping);
break;
case SPICE_MODEL_STRUCTURE_ONELEVEL:
dump_verilog_cmos_mux_onelevel_structure(fp, mux_basis_subckt_name,
spice_model, spice_mux_arch, num_sram_port, sram_port);
spice_model, spice_mux_arch,
num_sram_port, sram_port, is_explicit_mapping);
break;
case SPICE_MODEL_STRUCTURE_MULTILEVEL:
dump_verilog_cmos_mux_multilevel_structure(fp, mux_basis_subckt_name, mux_special_basis_subckt_name,
spice_model, spice_mux_arch, num_sram_port, sram_port);
spice_model, spice_mux_arch, num_sram_port, sram_port,
is_explicit_mapping);
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n",
@ -1941,7 +2053,8 @@ void dump_verilog_rram_mux_onelevel_structure(FILE* fp,
void dump_verilog_rram_mux_submodule(FILE* fp,
int mux_size,
t_spice_model spice_model,
t_spice_mux_arch spice_mux_arch) {
t_spice_mux_arch spice_mux_arch,
bool is_explicit_mapping) {
int i, num_conf_bits;
int num_input_port = 0;
int num_output_port = 0;
@ -2173,7 +2286,8 @@ void dump_verilog_rram_mux_submodule(FILE* fp,
void dump_verilog_cmos_mux_mem_submodule(FILE* fp,
int mux_size,
t_spice_model spice_model,
t_spice_mux_arch spice_mux_arch) {
t_spice_mux_arch spice_mux_arch,
bool is_explicit_mapping) {
int i, num_conf_bits;
int num_sram_port = 0;
@ -2231,7 +2345,7 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp,
* 3. output ports
* 4. bl/wl ports
*/
dump_verilog_mem_module_port_map(fp, mem_model, TRUE, 0, num_conf_bits, FALSE);
dump_verilog_mem_module_port_map(fp, mem_model, TRUE, 0, num_conf_bits, my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, ");\n");
/* Dump all the submodules */
@ -2257,7 +2371,8 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp,
* whatever structure it is: one-level, two-level or multi-level
*/
void dump_verilog_mux_mem_module(FILE* fp,
t_spice_mux_model* spice_mux_model) {
t_spice_mux_model* spice_mux_model,
bool is_explicit_mapping) {
/* Make sure we have a valid file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__);
@ -2287,7 +2402,8 @@ void dump_verilog_mux_mem_module(FILE* fp,
case SPICE_MODEL_DESIGN_CMOS:
dump_verilog_cmos_mux_mem_submodule(fp, spice_mux_model->size,
*(spice_mux_model->spice_model),
*(spice_mux_model->spice_mux_arch));
*(spice_mux_model->spice_mux_arch),
is_explicit_mapping);
break;
case SPICE_MODEL_DESIGN_RRAM:
/* We do not need a memory submodule for RRAM MUX,
@ -2308,7 +2424,8 @@ void dump_verilog_mux_mem_module(FILE* fp,
* whatever structure it is: one-level, two-level or multi-level
*/
void dump_verilog_mux_module(FILE* fp,
t_spice_mux_model* spice_mux_model) {
t_spice_mux_model* spice_mux_model,
bool is_explicit_mapping) {
/* Make sure we have a valid file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__);
@ -2347,12 +2464,14 @@ void dump_verilog_mux_module(FILE* fp,
case SPICE_MODEL_DESIGN_CMOS:
dump_verilog_cmos_mux_submodule(fp, spice_mux_model->size,
*(spice_mux_model->spice_model),
*(spice_mux_model->spice_mux_arch));
*(spice_mux_model->spice_mux_arch),
is_explicit_mapping);
break;
case SPICE_MODEL_DESIGN_RRAM:
dump_verilog_rram_mux_submodule(fp, spice_mux_model->size,
*(spice_mux_model->spice_model),
*(spice_mux_model->spice_mux_arch));
*(spice_mux_model->spice_mux_arch),
is_explicit_mapping);
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n",
@ -2373,7 +2492,8 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info,
int num_switch,
t_switch_inf* switches,
t_spice* spice,
t_det_routing_arch* routing_arch) {
t_det_routing_arch* routing_arch,
bool is_explicit_mapping) {
/* Statisitcs for input sizes and structures of MUXes
* used in FPGA architecture
@ -2444,7 +2564,7 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info,
/* Let's have a N:1 MUX as basis*/
dump_verilog_mux_basis_module(fp, cur_spice_mux_model);
/* Print the mux subckt */
dump_verilog_mux_module(fp, cur_spice_mux_model);
dump_verilog_mux_module(fp, cur_spice_mux_model, is_explicit_mapping);
/* Update the statistics*/
mux_cnt++;
if ((-1 == max_mux_size)||(max_mux_size < cur_spice_mux_model->size)) {
@ -2563,7 +2683,8 @@ void dump_verilog_wire_module(FILE* fp,
/* Dump one module of a LUT */
void dump_verilog_submodule_one_lut(FILE* fp,
t_spice_model* verilog_model) {
t_spice_model* verilog_model,
bool is_explicit_mapping) {
int num_input_port = 0;
int num_output_port = 0;
int num_sram_port = 0;
@ -2935,19 +3056,47 @@ void dump_verilog_submodule_one_lut(FILE* fp,
verilog_model->name, verilog_model->name);
/* Connect MUX inputs to LUT configuration port */
assert(FALSE == sram_port[sram_port_index]->mode_select);
fprintf(fp, " %s_out,",
if (true == is_explicit_mapping) {
fprintf(fp, ".in(");
}
fprintf(fp, "%s_out",
sram_port[sram_port_index]->prefix);
if (true == is_explicit_mapping) {
fprintf(fp, "), ");
} else {
fprintf(fp, ", ");
}
/* Connect MUX output to LUT output */
for (iport = 0; iport < num_output_port; iport++) {
fprintf(fp, " %s,",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
output_port[iport]->prefix);
}
fprintf(fp, "%s",
output_port[iport]->prefix);
if (true == is_explicit_mapping) {
fprintf(fp, "), ");
} else {
fprintf(fp, ", ");
}
}
/* Connect MUX configuration port to LUT inputs */
fprintf(fp, " %s_buf,",
if (true == is_explicit_mapping) {
fprintf(fp, ".sram(");
}
fprintf(fp, "%s_buf",
input_port[0]->prefix);
/* Connect MUX inverted configuration port to inverted LUT inputs */
fprintf(fp, " %s_b",
if (true == is_explicit_mapping) {
fprintf(fp, "), .sram_inv(");
} else {
fprintf(fp, ", ");
}
fprintf(fp, "%s_b",
input_port[0]->prefix);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* End of call LUT MUX */
fprintf(fp, ");\n");
@ -3048,7 +3197,8 @@ void dump_verilog_submodule_luts(char* verilog_dir,
int num_spice_model,
t_spice_model* spice_models,
boolean include_timing,
boolean include_signal_init) {
boolean include_signal_init,
bool is_explicit_mapping) {
FILE* fp = NULL;
char* verilog_name = my_strcat(submodule_dir, luts_verilog_file_name);
int imodel;
@ -3070,7 +3220,7 @@ void dump_verilog_submodule_luts(char* verilog_dir,
continue;
}
if (SPICE_MODEL_LUT == spice_models[imodel].type) {
dump_verilog_submodule_one_lut(fp, &(spice_models[imodel]));
dump_verilog_submodule_one_lut(fp, &(spice_models[imodel]), is_explicit_mapping);
}
}
@ -3234,7 +3384,8 @@ void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info,
int num_switch,
t_switch_inf* switches,
t_spice* spice,
t_det_routing_arch* routing_arch) {
t_det_routing_arch* routing_arch,
bool is_explicit_mapping) {
/* Statisitcs for input sizes and structures of MUXes
* used in FPGA architecture
@ -3308,7 +3459,8 @@ void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info,
cur_spice_mux_model->spice_mux_arch = (t_spice_mux_arch*)my_malloc(sizeof(t_spice_mux_arch));
init_spice_mux_arch(cur_spice_mux_model->spice_model, cur_spice_mux_model->spice_mux_arch, cur_spice_mux_model->size);
/* Print the mux mem subckt */
dump_verilog_mux_mem_module(fp, cur_spice_mux_model);
dump_verilog_mux_mem_module(fp, cur_spice_mux_model,
is_explicit_mapping);
/* Update the statistics*/
/* Move on to the next*/
temp = temp->next;
@ -3485,14 +3637,15 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info,
/* 1. MUXes */
vpr_printf(TIO_MESSAGE_INFO, "Generating modules of multiplexers...\n");
dump_verilog_submodule_muxes(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch,
switch_inf, Arch.spice, routing_arch);
switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog);
/* 2. LUTes */
vpr_printf(TIO_MESSAGE_INFO, "Generating modules of LUTs...\n");
dump_verilog_submodule_luts(verilog_dir, submodule_dir,
Arch.spice->num_spice_model, Arch.spice->spice_models,
fpga_verilog_opts.include_timing,
fpga_verilog_opts.include_signal_init);
fpga_verilog_opts.include_signal_init,
fpga_verilog_opts.dump_explicit_verilog);
/* 3. Hardwires */
vpr_printf(TIO_MESSAGE_INFO, "Generating modules of hardwires...\n");
@ -3502,7 +3655,7 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info,
/* 4. Memories */
vpr_printf(TIO_MESSAGE_INFO, "Generating modules of memories...\n");
dump_verilog_submodule_memories(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch,
switch_inf, Arch.spice, routing_arch);
switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog);
/* 5. Dump decoder modules only when memory bank is required */
dump_verilog_config_peripherals(cur_sram_orgz_info, verilog_dir, submodule_dir);

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c
View File

@ -145,7 +145,8 @@ void dump_verilog_one_sb_chan_pin(FILE* fp,
/* Output the pin name of a routing wire in a SB */
void dump_verilog_one_sb_routing_pin(FILE* fp,
const RRGSB& rr_sb,
t_rr_node* cur_rr_node) {
t_rr_node* cur_rr_node,
bool is_explicit_mapping) {
int side;
/* Check the file handler */
@ -186,7 +187,7 @@ void dump_verilog_one_sb_routing_pin(FILE* fp,
side,
mirror_node->xlow,
mirror_node->ylow,
FALSE); /* Do not specify direction of port */
FALSE,is_explicit_mapping); /* Do not specify direction of port */
break;
}
case CHANX:
@ -206,7 +207,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp,
/* Output the pin name of a routing wire in a SB */
void dump_verilog_one_sb_routing_pin(FILE* fp,
t_sb* cur_sb_info,
t_rr_node* cur_rr_node) {
t_rr_node* cur_rr_node,
bool is_explicit_mapping) {
int side;
/* Check the file handler */
@ -229,7 +231,7 @@ void dump_verilog_one_sb_routing_pin(FILE* fp,
side,
cur_rr_node->xlow,
cur_rr_node->ylow,
FALSE); /* Do not specify direction of port */
FALSE, is_explicit_mapping); /* Do not specify direction of port */
break;
case CHANX:
case CHANY:

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h
View File

@ -20,11 +20,13 @@ void dump_verilog_one_sb_chan_pin(FILE* fp,
void dump_verilog_one_sb_routing_pin(FILE* fp,
const RRGSB& rr_sb,
t_rr_node* cur_rr_node);
t_rr_node* cur_rr_node,
bool is_explicit_mapping);
void dump_verilog_one_sb_routing_pin(FILE* fp,
t_sb* cur_sb_info,
t_rr_node* cur_rr_node);
t_rr_node* cur_rr_node,
bool is_explicit_mapping);
DeviceCoordinator get_chan_node_ending_cb(t_rr_node* src_rr_node,
t_rr_node* end_rr_node);

97
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c
View File

@ -131,7 +131,7 @@ void dump_verilog_top_netlist_memory_bank_internal_wires(t_sram_orgz_info* cur_s
fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
0, get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info) - 1,
VERILOG_PORT_WIRE);
VERILOG_PORT_WIRE, false);
fprintf(fp, ";\n");
fprintf(fp, "`endif\n");
break;
@ -217,7 +217,7 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr
fprintf(fp, " ");
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
0, num_scffs - 1,
VERILOG_PORT_WIRE);
VERILOG_PORT_WIRE, false);
fprintf(fp, ";\n");
fprintf(fp, "`endif\n");
@ -249,7 +249,8 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr
/* Dump ports for the top-level module in Verilog netlist */
void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
enum e_dump_verilog_port_type dump_port_type) {
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping) {
char* port_name = NULL;
char split_sign;
enum e_dump_verilog_port_type actual_dump_port_type;
@ -265,7 +266,7 @@ void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info,
}
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, dump_global_port_type)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, dump_global_port_type, is_explicit_mapping)) {
fprintf(fp, "%c\n", split_sign);
}
/* Inputs and outputs of I/O pads */
@ -317,7 +318,8 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int num_clocks,
char* circuit_name,
t_spice verilog) {
t_spice verilog,
bool is_explicit_mapping) {
/*
int num_array_bl, num_array_wl;
int bl_decoder_size, wl_decoder_size;
@ -334,7 +336,8 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "module %s_top (\n", circuit_name);
fprintf(fp, "\n");
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_INPUT);
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_INPUT,
false);
fprintf(fp, ");\n");
@ -367,7 +370,8 @@ void dump_verilog_top_netlist_internal_wires(t_sram_orgz_info* cur_sram_orgz_inf
static
void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int ix, int iy) {
int ix, int iy,
bool is_explicit_mapping) {
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__);
exit(1);
@ -387,21 +391,21 @@ void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
if (IO_TYPE == grid[ix][iy].type) {
dump_verilog_io_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE);
dump_verilog_io_grid_pins(fp, ix, iy, TRUE, 0, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping));
} else {
dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE);
dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE, is_explicit_mapping);
}
/* IO PAD */
dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix,
iopad_verilog_model->grid_index_low[ix][iy],
iopad_verilog_model->grid_index_high[ix][iy] - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
/* Print configuration ports */
/* Reserved configuration ports */
@ -435,7 +439,8 @@ static
void dump_verilog_defined_one_channel(FILE* fp,
t_rr_type chan_type, int x, int y,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices) {
t_ivec*** LL_rr_node_indices,
bool is_explicit_mapping) {
int itrack;
int chan_width = 0;
t_rr_node** chan_rr_nodes = NULL;
@ -477,7 +482,7 @@ void dump_verilog_defined_one_channel(FILE* fp,
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -572,7 +577,8 @@ void dump_verilog_defined_one_channel(FILE* fp,
/* Call the sub-circuits for channels : Channel X and Channel Y*/
void dump_verilog_defined_channels(FILE* fp,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices) {
t_ivec*** LL_rr_node_indices,
bool is_explicit_mapping) {
int ix, iy;
if (NULL == fp) {
@ -584,7 +590,7 @@ void dump_verilog_defined_channels(FILE* fp,
for (iy = 0; iy < (ny + 1); iy++) {
for (ix = 1; ix < (nx + 1); ix++) {
dump_verilog_defined_one_channel(fp, CHANX, ix, iy,
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices);
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping);
}
}
@ -592,7 +598,7 @@ void dump_verilog_defined_channels(FILE* fp,
for (ix = 0; ix < (nx + 1); ix++) {
for (iy = 1; iy < (ny + 1); iy++) {
dump_verilog_defined_one_channel(fp, CHANY, ix, iy,
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices);
LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping);
}
}
@ -607,7 +613,8 @@ void dump_verilog_defined_channels(FILE* fp,
static
void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb cur_cb_info) {
t_cb cur_cb_info,
bool is_explicit_mapping) {
int itrack, inode, side, x, y;
int side_cnt = 0;
@ -637,7 +644,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf
fprintf(fp, "(");
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -679,7 +686,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf
cur_cb_info.ipin_rr_node_grid_side[side][inode],
cur_cb_info.ipin_rr_node[side][inode]->xlow,
cur_cb_info.ipin_rr_node[side][inode]->ylow,
FALSE); /* Do not specify direction of port */
FALSE, is_explicit_mapping); /* Do not specify direction of port */
fprintf(fp, ", \n");
}
}
@ -698,7 +705,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf
if (0 < (cur_cb_info.conf_bits_msb - cur_cb_info.conf_bits_lsb)) {
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
cur_cb_info.conf_bits_lsb, cur_cb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
if (0 < (cur_cb_info.conf_bits_msb - 1 - cur_cb_info.conf_bits_lsb)) {
@ -708,7 +715,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_cb_info.conf_bits_lsb,
cur_cb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -735,7 +742,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf
/* Call the sub-circuits for connection boxes */
void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
FILE* fp, bool is_explicit_mapping) {
int ix, iy;
/* Check the file handler*/
@ -750,7 +757,8 @@ void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,
for (ix = 1; ix < (nx + 1); ix++) {
if ((TRUE == is_cb_exist(CHANX, ix, iy))
&&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) {
dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cbx_info[ix][iy]);
dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cbx_info[ix][iy],
is_explicit_mapping);
}
}
}
@ -759,7 +767,8 @@ void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,
for (iy = 1; iy < (ny + 1); iy++) {
if ((TRUE == is_cb_exist(CHANY, ix, iy))
&&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) {
dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cby_info[ix][iy]);
dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cby_info[ix][iy],
is_explicit_mapping);
}
}
}
@ -774,7 +783,8 @@ void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,
static
void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_sb cur_sb_info) {
t_sb cur_sb_info,
bool is_explicit_mapping) {
int ix, iy, side, itrack, x, y, inode;
/* Check the file handler*/
@ -801,7 +811,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "\n");
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) {
fprintf(fp, ",\n");
}
@ -823,7 +833,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
cur_sb_info.opin_rr_node_grid_side[side][inode],
cur_sb_info.opin_rr_node[side][inode]->xlow,
cur_sb_info.opin_rr_node[side][inode]->ylow,
FALSE); /* Do not specify the direction of port */
FALSE, is_explicit_mapping); /* Do not specify the direction of port */
fprintf(fp, ",\n");
}
fprintf(fp, "\n");
@ -843,7 +853,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
cur_sb_info.conf_bits_lsb,
cur_sb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
}
/* Dump ports only visible during formal verification*/
@ -854,7 +864,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sb_info.conf_bits_lsb,
cur_sb_info.conf_bits_msb - 1,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -869,7 +879,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info,
}
void dump_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
FILE* fp, bool is_explicit_mapping) {
int ix, iy;
/* Check the file handler*/
@ -881,7 +891,8 @@ void dump_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info,
for (ix = 0; ix < (nx + 1); ix++) {
for (iy = 0; iy < (ny + 1); iy++) {
dump_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, sb_info[ix][iy]);
dump_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, sb_info[ix][iy],
is_explicit_mapping);
}
}
@ -1422,7 +1433,8 @@ char* compact_verilog_get_grid_phy_block_subckt_name(t_type_ptr grid_type_descri
void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,
t_type_ptr grid_type_descriptor,
int border_side,
int z) {
int z,
bool is_explicit_mapping) {
int iport, ipin, dump_pin_cnt;
int grid_pin_index, pin_height, side_pin_index;
t_pb_graph_node* top_pb_graph_node = NULL;
@ -1462,8 +1474,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->input_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_",
convert_side_index_to_string(border_side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
side_pin_index++;
dump_pin_cnt++;
}
@ -1485,8 +1504,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->output_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_",
convert_side_index_to_string(border_side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
side_pin_index++;
dump_pin_cnt++;
}
@ -1508,8 +1534,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,
if (0 < dump_pin_cnt) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->clock_pins[iport]->port, ipin));
}
fprintf(fp, "%s_height_%d__pin_%d_",
convert_side_index_to_string(border_side), pin_height, grid_pin_index);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
side_pin_index++;
dump_pin_cnt++;
}

16
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h
View File

@ -3,20 +3,22 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int num_clocks,
char* circuit_name,
t_spice verilog);
t_spice verilog,
bool is_explicit_mapping);
void dump_verilog_top_netlist_internal_wires(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp);
void dump_verilog_defined_channels(FILE* fp,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices);
t_ivec*** LL_rr_node_indices,
bool is_explicit_mapping);
void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp);
FILE* fp, bool is_explicit_mapping);
void dump_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp);
FILE* fp, bool is_explicit_mapping);
void dump_verilog_clb2clb_directs(FILE* fp,
int num_directs, t_clb_to_clb_directs* direct);
@ -26,7 +28,8 @@ void dump_verilog_configuration_circuits(t_sram_orgz_info* cur_sram_orgz_info,
void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
enum e_dump_verilog_port_type dump_port_type);
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void verilog_compact_generate_fake_xy_for_io_border_side(int border_side,
int* ix, int* iy) ;
@ -49,6 +52,7 @@ char* compact_verilog_get_grid_phy_block_subckt_name(t_type_ptr grid_type_descri
void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,
t_type_ptr grid_type_descriptor,
int border_side,
int z) ;
int z,
bool is_explicit_mapping) ;

7
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c
View File

@ -312,7 +312,8 @@ void dump_verilog_top_testbench_ports(t_sram_orgz_info* cur_sram_orgz_info,
void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* circuit_name) {
char* circuit_name,
bool is_explicit_mapping) {
/*
int iblock, iopad_idx;
*/
@ -322,7 +323,7 @@ void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_
fprintf(fp, "//------Call defined Top-level Verilog Module -----\n");
fprintf(fp, "%s_top U0 (\n", circuit_name);
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT);
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT, is_explicit_mapping);
fprintf(fp, ");\n");
return;
@ -1354,7 +1355,7 @@ void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_top_testbench_ports(cur_sram_orgz_info, fp, circuit_name);
/* Call defined top-level module */
dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name);
dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name, false);
/* Add stimuli for reset, set, clock and iopad signals */
dump_verilog_top_testbench_stimuli(cur_sram_orgz_info, fp, verilog);

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h
View File

@ -6,7 +6,8 @@ void dump_verilog_top_testbench_global_ports_stimuli(FILE* fp, t_llist* head);
void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* circuit_name);
char* circuit_name,
bool is_explicit_mapping);
void dump_verilog_top_testbench_stimuli(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,

244
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -806,16 +806,14 @@ int rec_dump_verilog_spice_model_lib_global_ports(FILE* fp,
cur_spice_model_port->lib_name);
} else {
/* Add explicit port mapping if required */
if ((TRUE == require_explicit_port_map)
&& (TRUE == cur_spice_model->dump_explicit_port_map)) {
if (TRUE == require_explicit_port_map) {
fprintf(fp, ".%s(",
cur_spice_model_port->lib_name);
}
fprintf(fp, "%s[0:%d]",
cur_spice_model_port->lib_name,
cur_spice_model_port->size - 1);
if ((TRUE == require_explicit_port_map)
&& (TRUE == cur_spice_model->dump_explicit_port_map)) {
if (TRUE == require_explicit_port_map) {
fprintf(fp, ")");
}
}
@ -902,16 +900,15 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
cur_spice_model_port->prefix);
} else {
/* Add explicit port mapping if required */
if ((TRUE == require_explicit_port_map)
&& (TRUE == cur_spice_model->dump_explicit_port_map)) {
if (TRUE == require_explicit_port_map ) {
fprintf(fp, ".%s(",
cur_spice_model_port->lib_name);
/* cur_spice_model_port->lib_name); /* Old version*/
cur_spice_model_port->prefix);
}
fprintf(fp, "%s[0:%d]",
cur_spice_model_port->prefix,
cur_spice_model_port->size - 1);
if ((TRUE == require_explicit_port_map)
&& (TRUE == cur_spice_model->dump_explicit_port_map)) {
if (TRUE == require_explicit_port_map) {
fprintf(fp, ")");
}
}
@ -944,7 +941,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
/* Dump all the global ports that are stored in the linked list */
int dump_verilog_global_ports(FILE* fp, t_llist* head,
boolean dump_port_type) {
boolean dump_port_type,
bool is_explicit_mapping) {
t_llist* temp = head;
t_spice_model_port* cur_global_port = NULL;
int dumped_port_cnt = 0;
@ -958,6 +956,10 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head,
/* fprintf(fp, "//----- BEGIN Global ports -----\n"); */
while(NULL != temp) {
cur_global_port = (t_spice_model_port*)(temp->dptr);
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
cur_global_port->prefix);
}
if (TRUE == dump_port_type) {
fprintf(fp, "%s [0:%d] %s",
verilog_convert_port_type_to_string(cur_global_port->type),
@ -968,6 +970,53 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head,
cur_global_port->prefix,
cur_global_port->size - 1);
}
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* if this is the tail, we do not dump a comma */
if (NULL != temp->next) {
fprintf(fp, ", //---- global port \n");
}
/* Update counter */
dumped_port_cnt++;
/* Go to the next */
temp = temp->next;
}
/* fprintf(fp, "//----- END Global ports -----\n"); */
return dumped_port_cnt;
}
/* Dump all the global ports that are stored in the linked list */
int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head,
boolean dump_port_type) {
t_llist* temp = head;
t_spice_model_port* cur_global_port = NULL;
int dumped_port_cnt = 0;
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
__FILE__, __LINE__);
}
/* fprintf(fp, "//----- BEGIN Global ports -----\n"); */
while(NULL != temp) {
cur_global_port = (t_spice_model_port*)(temp->dptr);
fprintf(fp, ".%s(",
cur_global_port->prefix);
if (TRUE == dump_port_type) {
fprintf(fp, "%s [0:%d] %s",
verilog_convert_port_type_to_string(cur_global_port->type),
cur_global_port->size - 1,
cur_global_port->prefix);
} else {
fprintf(fp, "%s[0:%d]",
cur_global_port->prefix,
cur_global_port->size - 1);
}
fprintf(fp, ")");
/* if this is the tail, we do not dump a comma */
if (NULL != temp->next) {
fprintf(fp, ", //---- global port \n");
@ -1311,7 +1360,8 @@ void dump_verilog_sram_outports(FILE* fp,
void dump_verilog_formal_verification_sram_ports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type) {
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping) {
t_spice_model* mem_model = NULL;
char* port_name = NULL;
char* port_full_name = NULL;
@ -1348,8 +1398,14 @@ void dump_verilog_formal_verification_sram_ports(FILE* fp,
/*Malloc and generate the full name of port */
port_full_name = (char*)my_malloc(sizeof(char)*(strlen(mem_model->prefix) + strlen(port_name) + 1 + 1));
sprintf(port_full_name, "%s_%s", mem_model->prefix, port_name);
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
port_full_name);
}
dump_verilog_generic_port(fp, dump_port_type, port_full_name, sram_lsb, sram_msb);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Free */
/* Local variables such as port1_name and port2 name are automatically freed */
@ -1462,7 +1518,7 @@ void dump_verilog_formal_verification_sram_ports_wiring(FILE* fp,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
sram_lsb, sram_msb,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, false);
fprintf(fp, ";\n");
return;
@ -1484,7 +1540,7 @@ void dump_verilog_formal_verification_mux_sram_ports_wiring(FILE* fp,
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
sram_lsb, sram_msb,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, false);
fprintf(fp, ";\n");
return;
@ -1494,7 +1550,8 @@ void dump_verilog_formal_verification_mux_sram_ports_wiring(FILE* fp,
void dump_verilog_sram_local_ports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type) {
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping) {
/* Need to dump inverted BL/WL if needed */
int num_blb_ports, num_wlb_ports;
t_spice_model_port** blb_port = NULL;
@ -1532,14 +1589,26 @@ void dump_verilog_sram_local_ports(FILE* fp,
break;
case SPICE_SRAM_SCAN_CHAIN:
/* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_head(");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
sram_lsb, sram_lsb,
-1, dump_port_type);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
/* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_tail(");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
sram_msb, sram_msb,
0, dump_port_type);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization !\n",
@ -2504,7 +2573,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
t_sram_orgz_info* cur_sram_orgz_info,
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits) {
int num_mux_conf_bits,
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -2524,30 +2594,58 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
/* FOR Scan-chain, we need regular output of a scan-chain FF
* We do not need a prefix implying MUX name, size and index
*/
if (true == is_explicit_mapping) {
fprintf(fp, ".sram(");
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
mux_spice_model, mux_size,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
cur_num_sram,
cur_num_sram + num_mux_conf_bits - 1,
0, VERILOG_PORT_CONKT);
fprintf(fp, ",\n");
if (TRUE == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".sram_inv(");
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
mux_spice_model, mux_size,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
cur_num_sram,
cur_num_sram + num_mux_conf_bits - 1,
1, VERILOG_PORT_CONKT);
if (TRUE == is_explicit_mapping) {
fprintf(fp, ")");
}
break;
case SPICE_SRAM_MEMORY_BANK:
/* configuration wire bus */
/* First bus is for sram_out in CMOS MUX
* We need a prefix implying MUX name, size and index
*/
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".sram(");
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
mux_spice_model, mux_size,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
cur_num_sram,
cur_num_sram + num_mux_conf_bits - 1,
0, VERILOG_PORT_CONKT);
if (TRUE == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".sram_inv(");
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
mux_spice_model, mux_size,
cur_num_sram, cur_num_sram + num_mux_conf_bits - 1,
cur_num_sram,
cur_num_sram + num_mux_conf_bits - 1,
1, VERILOG_PORT_CONKT);
if (TRUE == is_explicit_mapping) {
fprintf(fp, ")");
}
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid SRAM organization!\n",
@ -2563,7 +2661,8 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
t_sram_orgz_info* cur_sram_orgz_info,
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits) {
int num_mux_conf_bits,
bool is_explicit_mapping) {
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -2583,9 +2682,11 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
case SPICE_MODEL_DESIGN_CMOS:
dump_verilog_cmos_mux_config_bus_ports(fp, mux_spice_model, cur_sram_orgz_info,
mux_size, cur_num_sram,
num_mux_reserved_conf_bits, num_mux_conf_bits);
num_mux_reserved_conf_bits,
num_mux_conf_bits, is_explicit_mapping);
break;
case SPICE_MODEL_DESIGN_RRAM:
/*TODO: Do explicit mapping for the RRAM*/
/* configuration wire bus */
fprintf(fp, "%s_size%d_%d_configbus0, ",
mux_spice_model->prefix, mux_size, mux_spice_model->cnt);
@ -2612,7 +2713,8 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
*/
void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,
char* general_port_prefix, int lsb, int msb,
enum e_dump_verilog_port_type dump_port_type) {
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping) {
char* port_full_name = NULL;
/* Check the file handler*/
@ -2630,9 +2732,15 @@ void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,
/*Malloc and generate the full name of port */
port_full_name = (char*)my_malloc(sizeof(char)*(strlen(general_port_prefix) + strlen(cur_verilog_model->prefix) + 1));
sprintf(port_full_name, "%s%s", general_port_prefix, cur_verilog_model->prefix);
fprintf(fp, ",\n");
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
port_full_name);
}
dump_verilog_generic_port(fp, dump_port_type, port_full_name, msb, lsb);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Free */
/* Local variables such as port1_name and port2 name are automatically freed */
@ -2981,7 +3089,8 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* cur_verilog_model, int mux_size,
t_spice_model* cur_sram_verilog_model,
int lsb, int msb) {
int lsb, int msb,
bool is_explicit_mapping) {
int cur_bl, cur_wl;
int num_bl_ports, num_wl_ports;
t_spice_model_port** bl_port = NULL;
@ -2992,6 +3101,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
int num_bl_per_sram = 0;
int num_wl_per_sram = 0;
int iport = 0;
/* Check the file handler*/
if (NULL == fp) {
@ -3029,7 +3139,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
}
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
@ -3077,10 +3187,10 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
case SPICE_SRAM_STANDALONE:
/* SRAM subckts*/
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
fprintf(fp, "%s_out[%d:%d], ",
fprintf(fp, "%s_in[%d:%d], ",
cur_sram_verilog_model->prefix, lsb, msb); /* Input*/
fprintf(fp, "%s_out[%d:%d], %s_outb[%d:%d] ",
cur_sram_verilog_model->prefix, lsb, msb,
@ -3088,41 +3198,107 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
break;
case SPICE_SRAM_SCAN_CHAIN:
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
if (SPICE_MODEL_MUX == cur_verilog_model->type) {
/* Input of Scan-chain DFF, should be connected to the output of its precedent */
if (true == is_explicit_mapping) {
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
cur_verilog_model, mux_size,
lsb, msb,
-1, VERILOG_PORT_CONKT);
fprintf(fp, ", \n"); //
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
fprintf(fp, ", \n");
/* Output of Scan-chain DFF, should be connected to the output of its successor */
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
cur_verilog_model, mux_size,
lsb, msb,
0, VERILOG_PORT_CONKT);
fprintf(fp, ", \n"); //
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
fprintf(fp, ", \n");
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
cur_verilog_model, mux_size,
lsb, msb,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
break;
}
/* Input of Scan-chain DFF, should be connected to the output of its precedent */
if (true == is_explicit_mapping) {
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
lsb, msb,
-1, VERILOG_PORT_CONKT);
fprintf(fp, ", \n"); //
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
fprintf(fp, ", \n");
/* Output of Scan-chain DFF, should be connected to the output of its successor */
if (true == is_explicit_mapping) {
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
lsb, msb,
0, VERILOG_PORT_CONKT);
fprintf(fp, ", \n"); //
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
fprintf(fp, ", \n");
if (true == is_explicit_mapping) {
while(TRUE == cur_sram_verilog_model->ports[iport].is_global) {
iport++;
}
fprintf(fp, ".%s(",
cur_sram_verilog_model->ports[iport].prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
lsb, msb,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
iport++;
fprintf(fp, ")");
}
break;
default:
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n",

27
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
View File

@ -76,7 +76,11 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
boolean require_explicit_port_map);
int dump_verilog_global_ports(FILE* fp, t_llist* head,
boolean dump_port_type);
boolean dump_port_type,
bool is_explicit_mapping);
int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head,
boolean dump_port_type);
void dump_verilog_mux_sram_one_outport(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
@ -96,7 +100,8 @@ void dump_verilog_mux_sram_one_local_outport(FILE* fp,
t_spice_model* cur_mux_spice_model, int mux_size,
int sram_lsb, int sram_msb,
int port_type_index,
enum e_dump_verilog_port_type dump_port_type);
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_one_local_outport(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
@ -112,7 +117,8 @@ void dump_verilog_sram_outports(FILE* fp,
void dump_verilog_formal_verification_sram_ports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type);
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_one_port(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
@ -123,7 +129,8 @@ void dump_verilog_sram_one_port(FILE* fp,
void dump_verilog_sram_local_ports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type);
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
@ -184,17 +191,20 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
t_sram_orgz_info* cur_sram_orgz_info,
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits);
int num_mux_conf_bits,
bool is_explicit_mapping);
void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
t_sram_orgz_info* cur_sram_orgz_info,
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits);
int num_mux_conf_bits,
bool is_explicit_mapping);
void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,
char* general_port_prefix, int lsb, int msb,
enum e_dump_verilog_port_type dump_port_type);
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
int lsb, int msb);
@ -234,7 +244,8 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* cur_verilog_model, int mux_size,
t_spice_model* cur_sram_verilog_model,
int lsb, int msb);
int lsb, int msb,
bool is_explicit_mapping);
char* gen_verilog_grid_one_pin_name(int x, int y,
int height, int side, int pin_index,

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c
View File

@ -187,7 +187,7 @@ void dump_verilog_formal_verfication_top_netlist_call_top_module(t_sram_orgz_inf
circuit_name,
formal_verification_top_module_uut_name);
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT);
dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT, false);
fprintf(fp, ");\n");
return;
@ -338,14 +338,14 @@ void dump_verilog_formal_verification_top_netlist_config_bitstream(t_sram_orgz_i
case SPICE_SRAM_SCAN_CHAIN:
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_conf_bit->index, cur_conf_bit->index,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, false);
fprintf(fp, " = 1'b%d",
cur_conf_bit->sram_bit->val);
break;
case SPICE_SRAM_MEMORY_BANK:
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_conf_bit->bl->addr, cur_conf_bit->bl->addr,
VERILOG_PORT_CONKT);
VERILOG_PORT_CONKT, false);
fprintf(fp, " = 1'b%d",
cur_conf_bit->bl->val);
break;

10
vpr7_x2p/vpr/VerilogNetlists/io.v
View File

@ -3,14 +3,14 @@
//------ Author: Xifan TANG -----//
module iopad(
//input zin, // Set output to be Z
input dout, // Data output
output din, // Data input
input outpad, // Data output
output inpad, // Data input
inout pad, // bi-directional pad
input direction // enable signal to control direction of iopad
input en // enable signal to control direction of iopad
//input direction_inv // enable signal to control direction of iopad
);
//----- when direction enabled, the signal is propagated from pad to din
assign din = direction ? pad : 1'bz;
assign inpad = en ? pad : 1'bz;
//----- when direction is disabled, the signal is propagated from dout to pad
assign pad = direction ? 1'bz : dout;
assign pad = en ? 1'bz : outpad;
endmodule

2
vpr7_x2p/vpr/regression_verilog.sh Normal file → Executable file
View File

@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
cd -
# Run VPR
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping
cd $fpga_flow_scripts
perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path