From 87ddca9f57428934c9c8b67b53f26a55e1500a00 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Wed, 26 Jun 2019 14:22:02 -0600 Subject: [PATCH 01/24] commiting current work. Stable but function not implemented yet --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 - .../fpga_x2p/verilog/verilog_report_timing.c | 531 +----------------- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 4 + 3 files changed, 23 insertions(+), 514 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index f4888c25f..0ea4fc420 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -288,8 +288,6 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); } - /* dump_verilog_sdc_file(); */ - /* dump verilog testbench only for input blif */ if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_input_blif_testbench) { blif_testbench_file_name = my_strcat(chomped_circuit_name, blif_testbench_verilog_file_postfix); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c index 495184f34..c8f5088ec 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c @@ -1016,6 +1016,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -unconstrained"); break; + /* All the types are verified before */ default: break; } @@ -1062,6 +1063,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + break; + /* All the types are verified before */ + default: break; } } @@ -1107,6 +1111,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + break; + /* All the types are verified before */ + default: break; } } @@ -1152,6 +1159,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + break; + /* All the types are verified before */ + default: break; } } @@ -1185,7 +1195,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, int path_cnt) { int L_wire; int ix, iy; - int cur_sb_x, cur_sb_y; int end_sb_x, end_sb_y; t_cb* next_cb = NULL; t_sb* next_sb = NULL; @@ -1368,6 +1377,8 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } @@ -1403,6 +1414,8 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } @@ -1438,6 +1451,8 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } @@ -1473,12 +1488,14 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } } - if (NULL != rpt_name) { + if (NULL != rpt_name) { fprintf(fp, " > %s\n", rpt_name); } else { fprintf(fp, "\n"); @@ -1490,516 +1507,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, return; } -///* Print the pins of SBs that a routing wire will go through -// * from the src_rr_node to the des_rr_node -// */ -//static -//void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, -// t_syn_verilog_opts fpga_verilog_opts, -// const RRGSB& src_sb, -// t_rr_node* drive_rr_node, -// t_rr_node* src_rr_node, -// t_rr_node* des_rr_node, -// int path_cnt) { -// int L_wire; -// int cur_sb_x, cur_sb_y; -// int end_sb_x, end_sb_y; -// t_cb* next_cb = NULL; -// char* rpt_name = NULL; -// DeviceCoordinator next_sb_coordinator; -// RRGSB next_sb; -// -// /* Check the file handler */ -// if (NULL == fp) { -// vpr_printf(TIO_MESSAGE_ERROR, -// "(FILE:%s,LINE[%d])Invalid file handler for SDC generation", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Check */ -// assert ((INC_DIRECTION == src_rr_node->direction) -// ||(DEC_DIRECTION == src_rr_node->direction)); -// assert ((CHANX == src_rr_node->type) -// ||(CHANY == src_rr_node->type)); -// -// L_wire = get_rr_node_wire_length(src_rr_node); -// -// /* Get report name */ -// rpt_name = gen_verilog_one_routing_report_timing_rpt_name(fpga_verilog_opts.report_timing_path, -// L_wire, path_cnt); -// -// /* Start printing report timing info */ -// fprintf(fp, "# L%d wire, Path ID: %d\n", -// L_wire, -// path_cnt); -// /* Report timing for the SB MUX delay, from the drive_rr_node to the wire_rr_node */ -// verilog_generate_one_report_timing_within_sb(fp, src_sb, -// drive_rr_node, -// src_rr_node); -// if (NULL != rpt_name) { -// fprintf(fp, " > %s\n", rpt_name); -// } else { -// fprintf(fp, "\n"); -// } -// -// /* Switch depends on the type of des_rr_node */ -// switch(des_rr_node->type) { -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y] | -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_cb|<---| src_sb |--->|thru_cb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x][y] | -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case IPIN: -// /* Get the coordinate of ending CB */ -// next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node); -// assert(next_cb->type == src_rr_node->type); -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x - 1; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y - 1; -// } -// break; -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y+1]| -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_sb|<---| src_sb |--->|thru_sb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x+1][y]| -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case CHANX: -// case CHANY: -// /* Get the coordinate of ending CB */ -// next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node); -// next_sb = device_rr_gsb.get_gsb(next_sb_coordinator); -// end_sb_x = next_sb.get_sb_x(); -// end_sb_y = next_sb.get_sb_y(); -// break; -// default: -// vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Get the base coordinate of src_sb */ -// cur_sb_x = src_sb.get_sb_x(); -// cur_sb_y = src_sb.get_sb_y(); -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (int ix = src_sb.get_sb_x(); ix < end_sb_x; ix++) { -// DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(ix + 1, cur_sb_y); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (int iy = src_sb.get_sb_y(); iy < end_sb_y; iy++) { -// DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(cur_sb_x, iy + 1); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (int ix = src_sb.get_sb_x() - 1; ix > end_sb_x; ix--) { -// DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(ix - 1, cur_sb_y); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (int iy = src_sb.get_sb_y() - 1; iy > end_sb_y; iy--) { -// DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(cur_sb_x, iy - 1); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } -// -// /* Free */ -// my_free(rpt_name); -// -// return; -//} -// -// -///* Print the pins of SBs that a routing wire will go through -// * from the src_rr_node to the des_rr_node -// */ -//static -//void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, -// t_syn_verilog_opts fpga_verilog_opts, -// t_sb* src_sb_info, -// t_rr_node* drive_rr_node, -// t_rr_node* src_rr_node, -// t_rr_node* des_rr_node, -// int path_cnt) { -// int L_wire; -// int ix, iy; -// int cur_sb_x, cur_sb_y; -// int end_sb_x, end_sb_y; -// t_cb* next_cb = NULL; -// t_sb* next_sb = NULL; -// char* rpt_name = NULL; -// -// /* Check the file handler */ -// if (NULL == fp) { -// vpr_printf(TIO_MESSAGE_ERROR, -// "(FILE:%s,LINE[%d])Invalid file handler for SDC generation", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Check */ -// assert ((INC_DIRECTION == src_rr_node->direction) -// ||(DEC_DIRECTION == src_rr_node->direction)); -// assert ((CHANX == src_rr_node->type) -// ||(CHANY == src_rr_node->type)); -// -// L_wire = get_rr_node_wire_length(src_rr_node); -// -// /* Get report name */ -// rpt_name = gen_verilog_one_routing_report_timing_rpt_name(fpga_verilog_opts.report_timing_path, -// L_wire, path_cnt); -// -// /* Start printing report timing info */ -// fprintf(fp, "# L%d wire, Path ID: %d\n", -// L_wire, -// path_cnt); -// /* Report timing for the SB MUX delay, from the drive_rr_node to the wire_rr_node */ -// verilog_generate_one_report_timing_within_sb(fp, src_sb_info, -// drive_rr_node, -// src_rr_node); -// if (NULL != rpt_name) { -// fprintf(fp, " > %s\n", rpt_name); -// } else { -// fprintf(fp, "\n"); -// } -// -// /* Switch depends on the type of des_rr_node */ -// switch(des_rr_node->type) { -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y] | -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_cb|<---| src_sb |--->|thru_cb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x][y] | -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case IPIN: -// /* Get the coordinate of ending CB */ -// next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node); -// assert(next_cb->type == src_rr_node->type); -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x - 1; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y - 1; -// } -// break; -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y+1]| -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_sb|<---| src_sb |--->|thru_sb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x+1][y]| -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case CHANX: -// case CHANY: -// /* Get the coordinate of ending CB */ -// next_sb = get_chan_rr_node_ending_sb(src_rr_node, des_rr_node); -// end_sb_x = next_sb->x; -// end_sb_y = next_sb->y; -// break; -// default: -// vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Get the base coordinate of src_sb */ -// cur_sb_x = src_sb_info->x; -// cur_sb_y = src_sb_info->y; -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (ix = src_sb_info->x; ix < end_sb_x; ix++) { -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// des_rr_node, -// rpt_name); -// -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// &(sb_info[ix + 1][cur_sb_y]), src_rr_node, -// rpt_name); -// } -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (iy = src_sb_info->y; iy < end_sb_y; iy++) { -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// &(sb_info[cur_sb_x][iy + 1]), src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (ix = src_sb_info->x - 1; ix > end_sb_x; ix--) { -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// &(sb_info[ix - 1][cur_sb_y]), src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (iy = src_sb_info->y - 1; iy > end_sb_y; iy--) { -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// &(sb_info[cur_sb_x][iy - 1]), src_rr_node, -// rpt_name); -// } -// } -// -// /* Free */ -// my_free(rpt_name); -// -// return; -//} - /* Print the pins of SBs that a routing wire will go through * from the src_rr_node to the des_rr_node */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index abdfbba53..6e21f776e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -958,6 +958,8 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, /* fprintf(fp, "//----- BEGIN Global ports -----\n"); */ while(NULL != temp) { cur_global_port = (t_spice_model_port*)(temp->dptr); + fprintf(fp, ".%s(", + cur_global_port->prefix); if (TRUE == dump_port_type) { fprintf(fp, "%s [0:%d] %s", verilog_convert_port_type_to_string(cur_global_port->type), @@ -968,6 +970,8 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, cur_global_port->prefix, cur_global_port->size - 1); } + fprintf(fp, ")"); + /* if this is the tail, we do not dump a comma */ if (NULL != temp->next) { fprintf(fp, ", //---- global port \n"); From 0ce9846e47e06222cb893d8e204da172649b350e Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Wed, 26 Jun 2019 16:54:41 -0600 Subject: [PATCH 02/24] Stable, unfinished --- vpr7_x2p/vpr/SRC/base/OptionTokens.c | 1 + vpr7_x2p/vpr/SRC/base/OptionTokens.h | 1 + vpr7_x2p/vpr/SRC/base/ReadOptions.c | 2 + vpr7_x2p/vpr/SRC/base/SetupVPR.c | 5 +++ vpr7_x2p/vpr/SRC/base/vpr_api.c | 1 + vpr7_x2p/vpr/SRC/base/vpr_types.h | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 +- .../fpga_x2p/verilog/verilog_report_timing.c | 1 + .../SRC/fpga_x2p/verilog/verilog_routing.c | 27 +++++++----- .../SRC/fpga_x2p/verilog/verilog_routing.h | 2 +- .../verilog/verilog_top_netlist_utils.c | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 43 ++++++++++++++++++- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 3 ++ 13 files changed, 77 insertions(+), 14 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.c b/vpr7_x2p/vpr/SRC/base/OptionTokens.c index cb71d400c..f3984d4c7 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.c +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.c @@ -84,6 +84,7 @@ struct s_TokenPair OptionBaseTokenList[] = { /* Xifan TANG: Synthsizable Verilog */ { "fpga_verilog", OT_FPGA_VERILOG_SYN }, { "fpga_verilog_dir", OT_FPGA_VERILOG_SYN_DIR }, + { "fpga_verilog_explicit_mapping", OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING }, { "fpga_verilog_print_top_testbench", OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH }, { "fpga_verilog_print_autocheck_top_testbench", OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH }, { "fpga_verilog_print_input_blif_testbench", OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH }, diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.h b/vpr7_x2p/vpr/SRC/base/OptionTokens.h index 6f426b26f..f31630281 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.h +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.h @@ -101,6 +101,7 @@ enum e_OptionBaseToken { /* Xifan TANG: Verilog Generation */ OT_FPGA_VERILOG_SYN, /* Xifan TANG: Synthesizable Verilog Dump */ OT_FPGA_VERILOG_SYN_DIR, /* Xifan TANG: Synthesizable Verilog Dump */ + OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING, /* Baudouin Chauviere: explicit pin mapping during verilog generation */ OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist */ OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist */ OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for the orignial input blif */ diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c index 14ba29921..29096fae3 100644 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c +++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.c @@ -527,6 +527,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) { return Args; case OT_FPGA_VERILOG_SYN_DIR: return ReadString(Args, &Options->fpga_syn_verilog_dir); + case OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING: + return Args; case OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH: return Args; case OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH: diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 09441daa1..c63bbeb17 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -1088,6 +1088,7 @@ static void SetupSynVerilogOpts(t_options Options, /* Initialize */ syn_verilog_opts->dump_syn_verilog = FALSE; syn_verilog_opts->syn_verilog_dump_dir = NULL; + syn_verilog_opts->dump_explicit_verilog = FALSE; syn_verilog_opts->print_top_testbench = FALSE; syn_verilog_opts->print_autocheck_top_testbench = FALSE; syn_verilog_opts->reference_verilog_benchmark_file = NULL; @@ -1114,6 +1115,10 @@ static void SetupSynVerilogOpts(t_options Options, syn_verilog_opts->syn_verilog_dump_dir = my_strdup(Options.fpga_syn_verilog_dir); } + if (Options.Count[OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING]) { + syn_verilog_opts->dump_explicit_verilog = TRUE; + } + if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH]) { syn_verilog_opts->print_top_testbench = TRUE; } diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index 6827e010f..96353023b 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -194,6 +194,7 @@ void vpr_print_usage(void) { vpr_printf(TIO_MESSAGE_INFO, "Synthesizable Verilog Generator Options:\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_dir \n"); + vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_explicit_mapping\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_top_testbench\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_autocheck_top_testbench \n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_input_blif_testbench\n"); diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index 02a0d3657..2a3089271 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -1253,6 +1253,7 @@ struct s_spice_opts { typedef struct s_syn_verilog_opts t_syn_verilog_opts; struct s_syn_verilog_opts { boolean dump_syn_verilog; + boolean dump_explicit_verilog; char* syn_verilog_dump_dir; boolean print_top_testbench; boolean print_input_blif_testbench; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 0ea4fc420..b98d07224 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -255,7 +255,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, /* Dump routing resources: switch blocks, connection blocks and channel tracks */ dump_verilog_routing_resources(sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, &vpr_setup.RoutingArch, num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data, - vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); + vpr_setup.FPGA_SPICE_Opts); /* Dump logic blocks * Branches to go: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c index c8f5088ec..3961e2619 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c @@ -1195,6 +1195,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, int path_cnt) { int L_wire; int ix, iy; + int cur_sb_x, cur_sb_y; int end_sb_x, end_sb_y; t_cb* next_cb = NULL; t_sb* next_sb = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 47a1efec5..9616461b2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -941,7 +941,8 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, t_rr_node* cur_rr_node, int mux_size, t_rr_node** drive_rr_nodes, - int switch_index) { + int switch_index, + boolean is_explicit_mapping) { int input_cnt = 0; t_spice_model* verilog_model = NULL; int mux_level, path_id, cur_num_sram; @@ -1063,7 +1064,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -1382,7 +1383,8 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_sb, enum e_side chan_side, - size_t chan_node_id) { + size_t chan_node_id, + boolean is_explicit_mapping) { int num_drive_rr_nodes = 0; t_rr_node** drive_rr_nodes = NULL; @@ -1418,7 +1420,8 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, /* Print the multiplexer, fan_in >= 2 */ dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node, num_drive_rr_nodes, drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); + cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], + is_explicit_mapping); } /*Nothing should be done else*/ /* Free */ @@ -1778,7 +1781,8 @@ static void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, size_t module_id, size_t seg_id, - const RRGSB& rr_sb, enum e_side side) { + const RRGSB& rr_sb, enum e_side side, + boolean is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; Side side_manager(side); @@ -1874,7 +1878,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr } dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb, side_manager.get_side(), - itrack); + itrack, is_explicit_mapping); } } @@ -2166,7 +2170,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or static void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - const RRGSB& rr_sb) { + const RRGSB& rr_sb, + boolean is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; @@ -2284,7 +2289,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb, side_manager.get_side(), - itrack); + itrack, is_explicit_mapping); } } } @@ -3764,9 +3769,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - boolean compact_routing_hierarchy) { + t_fpga_spice_opts FPGA_SPICE_Opts) { assert(UNI_DIRECTIONAL == routing_arch->directionality); + boolean compact_routing_hierarchy = FPGA_SPICE_Opts.compact_routing_hierarchy; + boolean explicit_port_mapping = FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog; /* Two major tasks: * 1. Generate sub-circuits for Routing Channels * 2. Generate sub-circuits for Switch Boxes @@ -3832,7 +3839,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_submodule(side_manager.get_side(), iseg); ++isb) { const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_submodule(isb, side_manager.get_side(), iseg); size_t seg_id = device_rr_gsb.get_segment_id(iseg); - dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side()); + dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side(), explicit_port_mapping); } } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index d5a2433ea..1cfd449b4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -132,6 +132,6 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - boolean compact_routing_hierarchy); + t_fpga_spice_opts FPGA_SPICE_Opts); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index b8c0933c4..90fdf268d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -477,7 +477,7 @@ void dump_verilog_defined_one_channel(FILE* fp, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports_explicit(fp, global_ports_head, FALSE)) { fprintf(fp, ",\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 6e21f776e..58f30aa43 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -958,8 +958,49 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, /* fprintf(fp, "//----- BEGIN Global ports -----\n"); */ while(NULL != temp) { cur_global_port = (t_spice_model_port*)(temp->dptr); - fprintf(fp, ".%s(", + if (TRUE == dump_port_type) { + fprintf(fp, "%s [0:%d] %s", + verilog_convert_port_type_to_string(cur_global_port->type), + cur_global_port->size - 1, cur_global_port->prefix); + } else { + fprintf(fp, "%s[0:%d]", + cur_global_port->prefix, + cur_global_port->size - 1); + } + + /* if this is the tail, we do not dump a comma */ + if (NULL != temp->next) { + fprintf(fp, ", //---- global port \n"); + } + /* Update counter */ + dumped_port_cnt++; + /* Go to the next */ + temp = temp->next; + } + /* fprintf(fp, "//----- END Global ports -----\n"); */ + + return dumped_port_cnt; +} + +/* Dump all the global ports that are stored in the linked list */ +int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head, + boolean dump_port_type) { + t_llist* temp = head; + t_spice_model_port* cur_global_port = NULL; + int dumped_port_cnt = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + } + + /* fprintf(fp, "//----- BEGIN Global ports -----\n"); */ + while(NULL != temp) { + cur_global_port = (t_spice_model_port*)(temp->dptr); + fprintf(fp, ".%s(", + cur_global_port->prefix); if (TRUE == dump_port_type) { fprintf(fp, "%s [0:%d] %s", verilog_convert_port_type_to_string(cur_global_port->type), diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 5fdd6821a..282f4cfaa 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -78,6 +78,9 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, int dump_verilog_global_ports(FILE* fp, t_llist* head, boolean dump_port_type); +int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head, + boolean dump_port_type); + void dump_verilog_mux_sram_one_outport(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, t_spice_model* cur_mux_spice_model, int mux_size, From 7c742f1cbbc4c648a630e4cd875e62a8569df632 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 27 Jun 2019 10:29:57 -0600 Subject: [PATCH 03/24] Stable, is_explicit propagated through the code. Not implemented though except for muxes --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 4 +- .../verilog/verilog_compact_netlist.c | 18 ++- .../verilog/verilog_compact_netlist.h | 6 +- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 67 +++++++---- .../SRC/fpga_x2p/verilog/verilog_pbtypes.h | 18 ++- .../SRC/fpga_x2p/verilog/verilog_routing.c | 106 +++++++++++++----- .../SRC/fpga_x2p/verilog/verilog_routing.h | 18 ++- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 46 ++++++-- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 6 +- 9 files changed, 206 insertions(+), 83 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index b98d07224..20ea51ecd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -262,7 +262,9 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, * 1. a compact output * 2. a full-size output */ - dump_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path, lb_dir_path, &Arch); + dump_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path, + lb_dir_path, &Arch, + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* Dump internal structures of submodules */ dump_verilog_submodules(sram_verilog_orgz_info, src_dir_path, submodule_dir_path, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 064cb2623..5d20c5f2a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -281,7 +281,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf char* verilog_dir_path, char* subckt_dir_path, t_type_ptr phy_block_type, - int border_side) { + int border_side, + boolean is_explicit_mapping) { int iz; int temp_reserved_conf_bits_msb; int temp_iopad_lsb, temp_iopad_msb; @@ -343,7 +344,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "//----- Submodule of type_descriptor: %s -----\n", phy_block_type->name); /* Print a NULL logic block...*/ dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name_prefix, - phy_block_type->pb_graph_head, iz); + phy_block_type->pb_graph_head, iz, + is_explicit_mapping); fprintf(fp, "//----- END -----\n\n"); /* Switch Flag on dumping verilog module */ verilog_module_dumped = TRUE; @@ -512,7 +514,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - t_arch* arch) { + t_arch* arch, + boolean is_explicit_mapping) { int itype, iside, num_sides; int* stamped_spice_model_cnt = NULL; t_sram_orgz_info* stamped_sram_orgz_info = NULL; @@ -534,20 +537,23 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (iside = 0; iside < num_sides; iside++) { dump_compact_verilog_one_physical_block(cur_sram_orgz_info, verilog_dir, subckt_dir, - &type_descriptors[itype], iside); + &type_descriptors[itype], iside, + is_explicit_mapping); } continue; } else if (FILL_TYPE == &type_descriptors[itype]) { /* For CLB */ dump_compact_verilog_one_physical_block(cur_sram_orgz_info, verilog_dir, subckt_dir, - &type_descriptors[itype], -1); + &type_descriptors[itype], -1, + is_explicit_mapping); continue; } else { /* For heterogenenous blocks */ dump_compact_verilog_one_physical_block(cur_sram_orgz_info, verilog_dir, subckt_dir, - &type_descriptors[itype], -1); + &type_descriptors[itype], -1, + is_explicit_mapping); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h index 87eb33f78..852415d67 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h @@ -5,12 +5,14 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf char* verilog_dir_path, char* subckt_dir_path, t_type_ptr phy_block_type, - int border_side); + int border_side, + boolean is_explicit_mapping); void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - t_arch* arch); + t_arch* arch, + boolean is_explicit_mapping); void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index ea01fc03e..51a85edc8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1037,7 +1037,8 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, char* parent_pin_prefix, enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode) { + t_mode* cur_mode, + boolean is_explicit_mapping) { int iedge, ipin; int fan_in = 0; t_interconnect* cur_interc = NULL; @@ -1261,7 +1262,8 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, cur_interc->spice_model, cur_sram_orgz_info, - fan_in, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + fan_in, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits, + is_explicit_mapping); fprintf(fp, ");\n"); @@ -1318,7 +1320,8 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, char* formatted_pin_prefix, t_pb_graph_node* cur_pb_graph_node, enum e_spice_pb_port_type pb_port_type, - t_mode* cur_mode) { + t_mode* cur_mode, + boolean is_explicit_mapping) { int iport, ipin; /* Check the file handler*/ @@ -1339,7 +1342,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, formatted_pin_prefix, /* parent_pin_prefix */ INPUT2INPUT_INTERC, &(cur_pb_graph_node->input_pins[iport][ipin]), - cur_mode); + cur_mode, is_explicit_mapping); } } break; @@ -1351,7 +1354,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, formatted_pin_prefix, /* parent_pin_prefix */ OUTPUT2OUTPUT_INTERC, &(cur_pb_graph_node->output_pins[iport][ipin]), - cur_mode); + cur_mode, is_explicit_mapping); } } break; @@ -1363,7 +1366,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, formatted_pin_prefix, /* parent_pin_prefix */ INPUT2INPUT_INTERC, &(cur_pb_graph_node->clock_pins[iport][ipin]), - cur_mode); + cur_mode, is_explicit_mapping); } } break; @@ -1382,7 +1385,8 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* pin_prefix, t_pb_graph_node* cur_pb_graph_node, - int select_mode_index) { + int select_mode_index, + boolean is_explicit_mapping) { int ipb, jpb; t_mode* cur_mode = NULL; t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; @@ -1416,7 +1420,7 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix, cur_pb_graph_node, SPICE_PB_PORT_OUTPUT, - cur_mode); + cur_mode, is_explicit_mapping); /* We check input_pins of child_pb_graph_node and its the input_edges * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node @@ -1432,12 +1436,12 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix, child_pb_graph_node, SPICE_PB_PORT_INPUT, - cur_mode); + cur_mode, is_explicit_mapping); /* TODO: for clock pins, we should do the same work */ dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix, child_pb_graph_node, SPICE_PB_PORT_CLOCK, - cur_mode); + cur_mode, is_explicit_mapping); } } @@ -1582,7 +1586,8 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* subckt_prefix, t_pb_graph_node* cur_pb_graph_node, - int pb_type_index) { + int pb_type_index, + boolean is_explicit_mapping) { int mode_index, ipb, jpb, child_mode_index; t_pb_type* cur_pb_type = NULL; char* subckt_name = NULL; @@ -1645,8 +1650,10 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, /* Recursive*/ /* Refer to pack/output_clustering.c [LINE 392] */ /* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */ - dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, pass_on_prefix, - &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), jpb); + dump_verilog_phy_pb_graph_node_rec( + cur_sram_orgz_info, fp, pass_on_prefix, + &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), + jpb, is_explicit_mapping); /* Free */ my_free(pass_on_prefix); /* Make the current module has been dumped */ @@ -1872,7 +1879,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, } } /* Print interconnections, set is_idle as TRUE*/ - dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, cur_pb_graph_node, mode_index); + dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, + cur_pb_graph_node, mode_index, + is_explicit_mapping); /* Check each pins of pb_graph_node */ /* Check and update stamped_sram_cnt */ /* Now we only dump one Verilog for each pb_type, and instance them when num_pb > 1 @@ -1951,7 +1960,8 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, int x, int y, int z, - t_type_ptr type_descriptor) { + t_type_ptr type_descriptor, + boolean is_explicit_mapping) { t_pb_graph_node* top_pb_graph_node = NULL; t_block* mapped_block = NULL; t_pb* top_pb = NULL; @@ -1978,7 +1988,8 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, } /* Recursively find all idle mode and print netlist*/ - dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name, top_pb_graph_node, z); + dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name, + top_pb_graph_node, z, is_explicit_mapping); return; } @@ -2464,7 +2475,8 @@ void dump_verilog_io_grid_block_subckt_pins(FILE* fp, void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, int ix, int iy, - t_arch* arch) { + t_arch* arch, + boolean is_explicit_mapping) { int subckt_name_str_len = 0; char* subckt_name = NULL; int iz; @@ -2517,7 +2529,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, /* Comments: Grid [x][y]*/ fprintf(fp, "//----- Grid[%d][%d] type_descriptor: %s[%d] -----\n", ix, iy, grid[ix][iy].type->name, iz); /* Print a NULL logic block...*/ - dump_verilog_physical_block(cur_sram_orgz_info, fp, subckt_name, ix, iy, iz, grid[ix][iy].type); + dump_verilog_physical_block(cur_sram_orgz_info, fp, subckt_name, ix, iy, iz, + grid[ix][iy].type, is_explicit_mapping); fprintf(fp, "//----- END -----\n\n"); } @@ -2687,7 +2700,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, */ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, - t_arch* arch) { + t_arch* arch, + boolean is_explicit_mapping) { int ix, iy; /* Check the grid*/ @@ -2709,7 +2723,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, assert(IO_TYPE != grid[ix][iy].type); /* Ensure a valid usage */ assert((0 == grid[ix][iy].usage)||(0 < grid[ix][iy].usage)); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } } @@ -2720,7 +2735,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (ix = 1; ix < (nx + 1); ix++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Right side : x = nx + 1, y = 1 .. ny*/ @@ -2728,7 +2744,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (iy = 1; iy < (ny + 1); iy++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Bottom side : x = 1 .. nx + 1, y = 0 */ @@ -2736,14 +2753,16 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (ix = 1; ix < (nx + 1); ix++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Left side: x = 0, y = 1 .. ny*/ ix = 0; for (iy = 1; iy < (ny + 1); iy++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Output a header file for all the logic blocks */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h index 42db03fb0..f5e45c2a7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h @@ -58,13 +58,15 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, char* parent_pin_prefix, enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode); + t_mode* cur_mode, + boolean is_explicit_mapping); void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* pin_prefix, t_pb_graph_node* cur_pb_graph_node, - int select_mode_index); + int select_mode_index, + boolean is_explicit_mapping); void dump_verilog_pb_graph_primitive_node(FILE* fp, char* subckt_prefix, @@ -84,7 +86,8 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* subckt_prefix, t_pb_graph_node* cur_pb_graph_node, - int pb_type_index); + int pb_type_index, + boolean is_explicit_mapping); void dump_verilog_block(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -101,7 +104,8 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, int x, int y, int z, - t_type_ptr type_descriptor); + t_type_ptr type_descriptor, + boolean is_explicit_mapping); void dump_verilog_grid_pins(FILE* fp, int x, int y, @@ -138,7 +142,8 @@ void dump_verilog_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, int ix, int iy, - t_arch* arch); + t_arch* arch, + boolean is_explicit_mapping); void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -147,7 +152,8 @@ void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info, t_type_ptr type_descriptor); void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, - char* subckt_dir, t_arch* arch); + char* subckt_dir, t_arch* arch, + boolean is_explicit_mapping); void rec_copy_name_mux_in_node(t_pb_graph_node* master_node, t_pb_graph_node* target_node); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 9616461b2..03a749747 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -694,7 +694,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, t_rr_node* cur_rr_node, int mux_size, t_rr_node** drive_rr_nodes, - int switch_index) { + int switch_index, + boolean is_explicit_mapping) { int inode, side, index, input_cnt = 0; int grid_x, grid_y; t_spice_model* verilog_model = NULL; @@ -837,7 +838,9 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, + num_mux_reserved_conf_bits, num_mux_conf_bits, + is_explicit_mapping); fprintf(fp, ");\n"); @@ -1068,17 +1071,31 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ",\n"); } + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".in("); + fprintf(fp, "%s_size%d_%d_inbus), ", + verilog_model->prefix, mux_size, verilog_model->cnt); + } + else { fprintf(fp, "%s_size%d_%d_inbus, ", verilog_model->prefix, mux_size, verilog_model->cnt); - + } /* Output port */ - dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".out("); + dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT); + fprintf(fp, ")"); + } + else { + dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT); + } /* Add a comma because dump_verilog_switch_box_chan_port does not add so */ fprintf(fp, ", "); /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); fprintf(fp, ");\n"); @@ -1327,7 +1344,8 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_sb* cur_sb_info, int chan_side, - t_rr_node* cur_rr_node) { + t_rr_node* cur_rr_node, + boolean is_explicit_mapping) { int sb_x, sb_y; int num_drive_rr_nodes = 0; t_rr_node** drive_rr_nodes = NULL; @@ -1370,7 +1388,8 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, /* Print the multiplexer, fan_in >= 2 */ dump_verilog_switch_box_mux(cur_sram_orgz_info, fp, cur_sb_info, chan_side, cur_rr_node, num_drive_rr_nodes, drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); + cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], + is_explicit_mapping); } /*Nothing should be done else*/ /* Free */ @@ -2352,7 +2371,8 @@ static void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_sb* cur_sb_info, - boolean compact_routing_hierarchy) { + boolean compact_routing_hierarchy, + boolean is_explicit_mapping) { int itrack, inode, side, ix, iy, x, y; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; FILE* fp = NULL; @@ -2485,7 +2505,9 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info ||(CHANY == cur_sb_info->chan_rr_node[side][itrack]->type)); /* We care INC_DIRECTION tracks at this side*/ if (OUT_PORT == cur_sb_info->chan_rr_node_direction[side][itrack]) { - dump_verilog_switch_box_interc(cur_sram_orgz_info, fp, cur_sb_info, side, cur_sb_info->chan_rr_node[side][itrack]); + dump_verilog_switch_box_interc(cur_sram_orgz_info, fp, cur_sb_info, side, + cur_sb_info->chan_rr_node[side][itrack], + is_explicit_mapping); } } } @@ -2768,7 +2790,8 @@ static void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { int mux_size, cur_num_sram, input_cnt = 0; t_rr_node** drive_rr_nodes = NULL; int mux_level, path_id, switch_index; @@ -2907,7 +2930,9 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, + num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); fprintf(fp, ");\n"); @@ -2995,7 +3020,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { int mux_size, cur_num_sram, input_cnt = 0; t_rr_node** drive_rr_nodes = NULL; int inode, mux_level, path_id, switch_index; @@ -3137,7 +3163,9 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, + num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); fprintf(fp, ");\n"); @@ -3224,7 +3252,8 @@ static void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3237,7 +3266,8 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ - dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type, src_rr_node); + dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type, + src_rr_node, is_explicit_mapping); } /*Nothing should be done else*/ return; @@ -3247,7 +3277,8 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3264,7 +3295,8 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ - dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, src_rr_node); + dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, + src_rr_node, is_explicit_mapping); } /*Nothing should be done else*/ return; @@ -3389,7 +3421,8 @@ int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_o static void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - const RRGSB& rr_cb, t_rr_type cb_type) { + const RRGSB& rr_cb, t_rr_type cb_type, + boolean is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; @@ -3499,7 +3532,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra enum e_side cb_ipin_side = cb_ipin_sides[iside]; for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { dump_verilog_connection_box_interc(cur_sram_orgz_info, fp, rr_gsb, cb_type, - rr_gsb.get_ipin_node(cb_ipin_side, inode)); + rr_gsb.get_ipin_node(cb_ipin_side, inode), + is_explicit_mapping); } } @@ -3552,7 +3586,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_cb* cur_cb_info, - boolean compact_routing_hierarchy) { + boolean compact_routing_hierarchy, + boolean is_explicit_mapping) { int itrack, inode, side, x, y; int side_cnt = 0; FILE* fp = NULL; @@ -3725,7 +3760,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ assert(NULL != cur_cb_info->ipin_rr_node[side]); for (inode = 0; inode < cur_cb_info->num_ipin_rr_nodes[side]; inode++) { dump_verilog_connection_box_interc(cur_sram_orgz_info, fp, cur_cb_info, - cur_cb_info->ipin_rr_node[side][inode]); + cur_cb_info->ipin_rr_node[side][inode], + is_explicit_mapping); } } @@ -3867,8 +3903,10 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (int iy = 0; iy < (ny + 1); iy++) { /* vpr_printf(TIO_MESSAGE_INFO, "Writing Switch Boxes[%d][%d]...\n", ix, iy); */ update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); - dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(sb_info[ix][iy]), - compact_routing_hierarchy); + dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, + subckt_dir, &(sb_info[ix][iy]), + compact_routing_hierarchy, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); } } @@ -3886,7 +3924,9 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* X - channels [1...nx][0..ny]*/ for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb); - dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX); + dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, + verilog_dir, subckt_dir, unique_mirror, CHANX, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } /* TODO: when we follow a tile organization, * updating the conf bits should follow a tile organization: CLB, SB and CBX, CBY */ @@ -3900,7 +3940,9 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* Y - channels [1...ny][0..nx]*/ for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb); - dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY); + dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, + verilog_dir, subckt_dir, unique_mirror, CHANY, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { @@ -3919,8 +3961,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, update_spice_models_routing_index_low(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); if ((TRUE == is_cb_exist(CHANX, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { - dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cbx_info[ix][iy]), - compact_routing_hierarchy); + dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, + verilog_dir, subckt_dir, + &(cbx_info[ix][iy]), + compact_routing_hierarchy, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); } @@ -3932,8 +3977,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, update_spice_models_routing_index_low(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); if ((TRUE == is_cb_exist(CHANY, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { - dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cby_info[ix][iy]), - compact_routing_hierarchy); + dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, + verilog_dir, subckt_dir, + &(cby_info[ix][iy]), + compact_routing_hierarchy, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index 1cfd449b4..52ac54cc7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -40,7 +40,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, t_rr_node* cur_rr_node, int mux_size, t_rr_node** drive_rr_nodes, - int switch_index); + int switch_index, + boolean is_explicit_mapping); int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, t_sb cur_sb_info, int chan_side, @@ -54,7 +55,8 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_sb* cur_sb_info, int chan_side, - t_rr_node* cur_rr_node); + t_rr_node* cur_rr_node, + boolean is_explicit_mapping); int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, t_sb cur_sb_info); @@ -68,7 +70,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_syn_verilog_opts fpga_verilog_opts, - boolean compact_routing_hierarchy); + boolean compact_routing_hierarchy, + boolean is_explicit_mapping); void dump_verilog_connection_box_short_interc(FILE* fp, @@ -78,12 +81,14 @@ void dump_verilog_connection_box_short_interc(FILE* fp, void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node); + t_rr_node* src_rr_node, + boolean is_explicit_mapping); void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node); + t_rr_node* src_rr_node, + boolean is_explicit_mapping); int count_verilog_connection_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, @@ -121,7 +126,8 @@ int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_o void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_cb* cur_cb_info, - boolean compact_routing_hierarchy); + boolean compact_routing_hierarchy, + boolean is_explicit_mapping); void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 58f30aa43..fefad5466 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2549,7 +2549,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits) { + int num_mux_conf_bits, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -2569,30 +2570,58 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m /* FOR Scan-chain, we need regular output of a scan-chain FF * We do not need a prefix implying MUX name, size and index */ + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 0, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram_inv("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 1, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } break; case SPICE_SRAM_MEMORY_BANK: /* configuration wire bus */ /* First bus is for sram_out in CMOS MUX * We need a prefix implying MUX name, size and index */ + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 0, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram_inv("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 1, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } break; default: vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid SRAM organization!\n", @@ -2608,7 +2637,8 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits) { + int num_mux_conf_bits, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -2628,9 +2658,11 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, case SPICE_MODEL_DESIGN_CMOS: dump_verilog_cmos_mux_config_bus_ports(fp, mux_spice_model, cur_sram_orgz_info, mux_size, cur_num_sram, - num_mux_reserved_conf_bits, num_mux_conf_bits); + num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); break; case SPICE_MODEL_DESIGN_RRAM: + /*TODO: Do explicit mapping for the RRAM*/ /* configuration wire bus */ fprintf(fp, "%s_size%d_%d_configbus0, ", mux_spice_model->prefix, mux_size, mux_spice_model->cnt); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 282f4cfaa..5485ad97f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -187,13 +187,15 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits); + int num_mux_conf_bits, + boolean is_explicit_mapping); void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits); + int num_mux_conf_bits, + boolean is_explicit_mapping); void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, char* general_port_prefix, int lsb, int msb, From 0e04b88c8ffb8be8eedfd9b847838af323f47a3c Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 1 Jul 2019 11:27:48 -0600 Subject: [PATCH 04/24] Include new files in the parameter spreading --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 10 +++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 1 + .../verilog/verilog_compact_netlist.c | 4 +- .../verilog/verilog_compact_netlist.h | 4 +- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 40 +++++++----- .../SRC/fpga_x2p/verilog/verilog_pbtypes.h | 14 ++-- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 18 ++--- .../SRC/fpga_x2p/verilog/verilog_primitives.h | 6 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 65 ++++++++++++------- .../SRC/fpga_x2p/verilog/verilog_routing.h | 12 ++-- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 11 ++-- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 7 +- 12 files changed, 117 insertions(+), 75 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index ac0072342..28e3563cd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -3476,3 +3476,13 @@ int my_strlen_int(int input_int) { return length_input; } + +boolean my_bool_to_boolean(bool my_bool) { + + if(true == my_bool) + return TRUE; + if(false == my_bool) + return FALSE; + vpr_printf(TIO_MESSAGE_ERROR,"Failure to convert bool to boolean. Parameter is neither true nor false.\n"); + exit(1); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index adc1cb8f9..2f28cbf2a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -406,4 +406,5 @@ void get_fpga_x2p_global_all_clock_ports(t_llist* head, int my_strlen_int(int input_int); +boolean my_bool_to_boolean(bool my_bool); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 5d20c5f2a..4187a0904 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -282,7 +282,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf char* subckt_dir_path, t_type_ptr phy_block_type, int border_side, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int iz; int temp_reserved_conf_bits_msb; int temp_iopad_lsb, temp_iopad_msb; @@ -515,7 +515,7 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_arch* arch, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int itype, iside, num_sides; int* stamped_spice_model_cnt = NULL; t_sram_orgz_info* stamped_sram_orgz_info = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h index 852415d67..cf3898dc8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h @@ -6,13 +6,13 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf char* subckt_dir_path, t_type_ptr phy_block_type, int border_side, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_arch* arch, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 51a85edc8..1551aa028 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1038,7 +1038,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, t_mode* cur_mode, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int iedge, ipin; int fan_in = 0; t_interconnect* cur_interc = NULL; @@ -1276,7 +1276,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, cur_interc->spice_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, cur_interc->spice_model, fan_in, - mem_model, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + mem_model, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, is_explicit_mapping); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); @@ -1321,7 +1321,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, t_pb_graph_node* cur_pb_graph_node, enum e_spice_pb_port_type pb_port_type, t_mode* cur_mode, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int iport, ipin; /* Check the file handler*/ @@ -1386,7 +1386,7 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, char* pin_prefix, t_pb_graph_node* cur_pb_graph_node, int select_mode_index, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int ipb, jpb; t_mode* cur_mode = NULL; t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; @@ -1527,7 +1527,8 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf char* subckt_prefix, t_pb_graph_node* prim_pb_graph_node, int pb_index, - t_spice_model* verilog_model) { + t_spice_model* verilog_model, + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -1551,23 +1552,27 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf case SPICE_MODEL_LUT: /* If this is a idle block we should set sram_bits to zero*/ dump_verilog_pb_primitive_lut(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node, - pb_index, verilog_model); + pb_index, verilog_model, + my_bool_to_boolean(is_explicit_mapping)); break; case SPICE_MODEL_FF: assert(NULL != verilog_model->model_netlist); /* TODO : We should learn trigger type and initial value!!! and how to apply them!!! */ dump_verilog_pb_generic_primitive(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node, - pb_index, verilog_model); + pb_index, verilog_model, + my_bool_to_boolean(is_explicit_mapping)); break; case SPICE_MODEL_IOPAD: assert(NULL != verilog_model->model_netlist); dump_verilog_pb_generic_primitive (cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node, - pb_index, verilog_model); + pb_index, verilog_model, + my_bool_to_boolean(is_explicit_mapping)); break; case SPICE_MODEL_HARDLOGIC: assert(NULL != verilog_model->model_netlist); dump_verilog_pb_generic_primitive(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node, - pb_index, verilog_model); + pb_index, verilog_model, + my_bool_to_boolean(is_explicit_mapping)); break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of verilog_model(%s), should be [LUT|FF|HARD_LOGIC|IO]!\n", @@ -1587,7 +1592,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_prefix, t_pb_graph_node* cur_pb_graph_node, int pb_type_index, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int mode_index, ipb, jpb, child_mode_index; t_pb_type* cur_pb_type = NULL; char* subckt_name = NULL; @@ -1668,21 +1673,24 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, case LUT_CLASS: dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, cur_pb_graph_node, pb_type_index, - cur_pb_type->spice_model); /* last param means idle */ + cur_pb_type->spice_model, + my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */ break; case LATCH_CLASS: assert(0 == cur_pb_type->num_modes); /* Consider the num_pb, create all the subckts*/ dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, cur_pb_graph_node, pb_type_index, - cur_pb_type->spice_model); /* last param means idle */ + cur_pb_type->spice_model, + my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */ break; case UNKNOWN_CLASS: case MEMORY_CLASS: /* Consider the num_pb, create all the subckts*/ dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, cur_pb_graph_node , pb_type_index, - cur_pb_type->spice_model); /* last param means idle */ + cur_pb_type->spice_model, + my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */ break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n", @@ -1961,7 +1969,7 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, int y, int z, t_type_ptr type_descriptor, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { t_pb_graph_node* top_pb_graph_node = NULL; t_block* mapped_block = NULL; t_pb* top_pb = NULL; @@ -2476,7 +2484,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, int ix, int iy, t_arch* arch, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int subckt_name_str_len = 0; char* subckt_name = NULL; int iz; @@ -2701,7 +2709,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, t_arch* arch, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int ix, iy; /* Check the grid*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h index f5e45c2a7..3ad43e94c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h @@ -59,14 +59,14 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, t_mode* cur_mode, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* pin_prefix, t_pb_graph_node* cur_pb_graph_node, int select_mode_index, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_pb_graph_primitive_node(FILE* fp, char* subckt_prefix, @@ -80,14 +80,14 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf t_pb_graph_node* prim_pb_graph_node, int pb_index, t_spice_model* verilog_model, - int is_idle); + bool is_explicit_mapping); void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* subckt_prefix, t_pb_graph_node* cur_pb_graph_node, int pb_type_index, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_block(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -105,7 +105,7 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, int y, int z, t_type_ptr type_descriptor, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_grid_pins(FILE* fp, int x, int y, @@ -143,7 +143,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, int ix, int iy, t_arch* arch, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -153,7 +153,7 @@ void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, t_arch* arch, - boolean is_explicit_mapping); + bool is_explicit_mapping); void rec_copy_name_mux_in_node(t_pb_graph_node* master_node, t_pb_graph_node* target_node); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index e306d5d9b..cad259077 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -43,7 +43,8 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_prefix, t_pb_graph_node* prim_pb_graph_node, int index, - t_spice_model* verilog_model) { + t_spice_model* verilog_model, + bool is_explicit_mapping) { int num_pad_port = 0; /* INOUT port */ t_spice_model_port** pad_ports = NULL; int num_input_port = 0; @@ -122,7 +123,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } @@ -228,7 +229,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, /* Only dump the global ports belonging to a spice_model * Disable recursive here ! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } @@ -370,7 +371,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, -1, - mem_model, cur_num_sram, cur_num_sram + num_sram - 1); + mem_model, cur_num_sram, cur_num_sram + num_sram - 1, my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_sram); @@ -404,7 +405,8 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_prefix, t_pb_graph_node* prim_pb_graph_node, int index, - t_spice_model* verilog_model) { + t_spice_model* verilog_model, + bool is_explicit_mapping) { int i; int lut_size = 0; int num_input_port = 0; @@ -525,7 +527,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, formatted_subckt_prefix, cur_pb_type->name); fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } /* Print inputs, outputs, inouts, clocks, NO SRAMs*/ @@ -602,7 +604,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, * Only dump the global ports belonging to a spice_model * DISABLE recursive here ! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } /* Connect inputs*/ @@ -680,7 +682,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, -1, - mem_model, cur_num_sram, cur_num_sram + num_sram - 1); + mem_model, cur_num_sram, cur_num_sram + num_sram - 1, is_explicit_mapping); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_sram); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.h index 81788ad20..b7dec3a48 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.h @@ -5,11 +5,13 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_prefix, t_pb_graph_node* prim_pb_graph_node, int index, - t_spice_model* spice_model); + t_spice_model* spice_model, + bool is_explicit_mapping); void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* subckt_prefix, t_pb_graph_node* prim_pb_graph_node, int index, - t_spice_model* spice_model); + t_spice_model* spice_model, + bool is_explicit_mapping); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 68aa13f64..1e69c6998 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -695,7 +695,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, int mux_size, t_rr_node** drive_rr_nodes, int switch_index, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int inode, side, index, input_cnt = 0; int grid_x, grid_y; t_spice_model* verilog_model = NULL; @@ -824,15 +824,27 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } - - fprintf(fp, "%s_size%d_%d_inbus, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "%s_size%d_%d_inbus", verilog_model->prefix, mux_size, verilog_model->cnt); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, " ,"); /* Output port */ + if (true == is_explicit_mapping) { + fprintf(fp, ".out("); + } dump_verilog_switch_box_chan_port(fp, cur_sb_info, chan_side, cur_rr_node, OUT_PORT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* Add a comma because dump_verilog_switch_box_chan_port does not add so */ fprintf(fp, ", "); @@ -904,7 +916,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); @@ -945,7 +958,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, int mux_size, t_rr_node** drive_rr_nodes, int switch_index, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int input_cnt = 0; t_spice_model* verilog_model = NULL; int mux_level, path_id, cur_num_sram; @@ -1067,7 +1080,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, is_explicit_mapping)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } @@ -1158,8 +1171,10 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, mem_subckt_name = generate_verilog_mux_subckt_name(verilog_model, mux_size, verilog_mem_posfix); fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); - dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, + verilog_model, mux_size, mem_model, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + is_explicit_mapping); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); @@ -1345,7 +1360,7 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, t_sb* cur_sb_info, int chan_side, t_rr_node* cur_rr_node, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int sb_x, sb_y; int num_drive_rr_nodes = 0; t_rr_node** drive_rr_nodes = NULL; @@ -1403,7 +1418,7 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, const RRGSB& rr_sb, enum e_side chan_side, size_t chan_node_id, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int num_drive_rr_nodes = 0; t_rr_node** drive_rr_nodes = NULL; @@ -1801,7 +1816,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr char* verilog_dir, char* subckt_dir, size_t module_id, size_t seg_id, const RRGSB& rr_sb, enum e_side side, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; Side side_manager(side); @@ -2190,7 +2205,7 @@ static void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, const RRGSB& rr_sb, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; @@ -2372,7 +2387,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info char* verilog_dir, char* subckt_dir, t_sb* cur_sb_info, boolean compact_routing_hierarchy, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int itrack, inode, side, ix, iy, x, y; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; FILE* fp = NULL; @@ -2791,7 +2806,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, t_rr_node* src_rr_node, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int mux_size, cur_num_sram, input_cnt = 0; t_rr_node** drive_rr_nodes = NULL; int mux_level, path_id, switch_index; @@ -2904,7 +2919,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } @@ -2985,7 +3000,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); @@ -3021,7 +3037,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, t_rr_node* src_rr_node, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int mux_size, cur_num_sram, input_cnt = 0; t_rr_node** drive_rr_nodes = NULL; int inode, mux_level, path_id, switch_index; @@ -3137,7 +3153,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } @@ -3218,7 +3234,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); @@ -3253,7 +3270,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, t_rr_node* src_rr_node, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3278,7 +3295,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, t_rr_node* src_rr_node, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3422,7 +3439,7 @@ static void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, const RRGSB& rr_cb, t_rr_type cb_type, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; @@ -3587,7 +3604,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ char* verilog_dir, char* subckt_dir, t_cb* cur_cb_info, boolean compact_routing_hierarchy, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int itrack, inode, side, x, y; int side_cnt = 0; FILE* fp = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index 52ac54cc7..e3038477b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -41,7 +41,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, int mux_size, t_rr_node** drive_rr_nodes, int switch_index, - boolean is_explicit_mapping); + bool is_explicit_mapping); int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, t_sb cur_sb_info, int chan_side, @@ -56,7 +56,7 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, t_sb* cur_sb_info, int chan_side, t_rr_node* cur_rr_node, - boolean is_explicit_mapping); + bool is_explicit_mapping); int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, t_sb cur_sb_info); @@ -71,7 +71,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info t_ivec*** LL_rr_node_indices, t_syn_verilog_opts fpga_verilog_opts, boolean compact_routing_hierarchy, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_connection_box_short_interc(FILE* fp, @@ -82,13 +82,13 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, t_rr_node* src_rr_node, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, t_rr_node* src_rr_node, - boolean is_explicit_mapping); + bool is_explicit_mapping); int count_verilog_connection_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, @@ -127,7 +127,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ char* verilog_dir, char* subckt_dir, t_cb* cur_cb_info, boolean compact_routing_hierarchy, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index fefad5466..f120ddd7c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2550,7 +2550,7 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, int num_mux_conf_bits, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -2570,7 +2570,7 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m /* FOR Scan-chain, we need regular output of a scan-chain FF * We do not need a prefix implying MUX name, size and index */ - if (TRUE == is_explicit_mapping) { + if (true == is_explicit_mapping) { fprintf(fp, ".sram("); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, @@ -2638,7 +2638,7 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, int num_mux_conf_bits, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3058,7 +3058,8 @@ void dump_verilog_mem_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, t_spice_model* cur_verilog_model, int mux_size, t_spice_model* cur_sram_verilog_model, - int lsb, int msb) { + int lsb, int msb, + bool is_explicit_mapping) { int cur_bl, cur_wl; int num_bl_ports, num_wl_ports; t_spice_model_port** bl_port = NULL; @@ -3106,7 +3107,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, } /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 5485ad97f..cf8427720 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -188,14 +188,14 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, int num_mux_conf_bits, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, int num_mux_conf_bits, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, char* general_port_prefix, int lsb, int msb, @@ -239,7 +239,8 @@ void dump_verilog_mem_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, t_spice_model* cur_verilog_model, int mux_size, t_spice_model* cur_sram_verilog_model, - int lsb, int msb); + int lsb, int msb, + bool is_explicit_mapping); char* gen_verilog_grid_one_pin_name(int x, int y, int height, int side, int pin_index, From 863e8677c0f75e3d69c1906395b92385b10d628a Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 1 Jul 2019 12:12:36 -0600 Subject: [PATCH 05/24] Further add new functions to tree --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 39 ++++++++++++------- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 2 +- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 08f53ea0f..5bcc70cb8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1434,7 +1434,8 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, void dump_verilog_cmos_mux_submodule(FILE* fp, int mux_size, t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch) { + t_spice_mux_arch spice_mux_arch, + bool is_explicit_mapping) { int i, num_conf_bits, iport, ipin, num_mode_bits; int num_input_port = 0; int num_output_port = 0; @@ -1941,7 +1942,8 @@ void dump_verilog_rram_mux_onelevel_structure(FILE* fp, void dump_verilog_rram_mux_submodule(FILE* fp, int mux_size, t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch) { + t_spice_mux_arch spice_mux_arch, + bool is_explicit_mapping) { int i, num_conf_bits; int num_input_port = 0; int num_output_port = 0; @@ -2173,7 +2175,8 @@ void dump_verilog_rram_mux_submodule(FILE* fp, void dump_verilog_cmos_mux_mem_submodule(FILE* fp, int mux_size, t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch) { + t_spice_mux_arch spice_mux_arch, + bool is_explicit_mapping) { int i, num_conf_bits; int num_sram_port = 0; @@ -2257,7 +2260,8 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp, * whatever structure it is: one-level, two-level or multi-level */ void dump_verilog_mux_mem_module(FILE* fp, - t_spice_mux_model* spice_mux_model) { + t_spice_mux_model* spice_mux_model, + bool is_explicit_mapping) { /* Make sure we have a valid file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); @@ -2287,7 +2291,8 @@ void dump_verilog_mux_mem_module(FILE* fp, case SPICE_MODEL_DESIGN_CMOS: dump_verilog_cmos_mux_mem_submodule(fp, spice_mux_model->size, *(spice_mux_model->spice_model), - *(spice_mux_model->spice_mux_arch)); + *(spice_mux_model->spice_mux_arch), + is_explicit_mapping); break; case SPICE_MODEL_DESIGN_RRAM: /* We do not need a memory submodule for RRAM MUX, @@ -2308,7 +2313,8 @@ void dump_verilog_mux_mem_module(FILE* fp, * whatever structure it is: one-level, two-level or multi-level */ void dump_verilog_mux_module(FILE* fp, - t_spice_mux_model* spice_mux_model) { + t_spice_mux_model* spice_mux_model, + bool is_explicit_mapping) { /* Make sure we have a valid file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); @@ -2347,12 +2353,14 @@ void dump_verilog_mux_module(FILE* fp, case SPICE_MODEL_DESIGN_CMOS: dump_verilog_cmos_mux_submodule(fp, spice_mux_model->size, *(spice_mux_model->spice_model), - *(spice_mux_model->spice_mux_arch)); + *(spice_mux_model->spice_mux_arch), + is_explicit_mapping); break; case SPICE_MODEL_DESIGN_RRAM: dump_verilog_rram_mux_submodule(fp, spice_mux_model->size, *(spice_mux_model->spice_model), - *(spice_mux_model->spice_mux_arch)); + *(spice_mux_model->spice_mux_arch), + is_explicit_mapping); break; default: vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", @@ -2373,7 +2381,8 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, int num_switch, t_switch_inf* switches, t_spice* spice, - t_det_routing_arch* routing_arch) { + t_det_routing_arch* routing_arch, + bool is_explicit_mapping) { /* Statisitcs for input sizes and structures of MUXes * used in FPGA architecture @@ -2444,7 +2453,7 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, /* Let's have a N:1 MUX as basis*/ dump_verilog_mux_basis_module(fp, cur_spice_mux_model); /* Print the mux subckt */ - dump_verilog_mux_module(fp, cur_spice_mux_model); + dump_verilog_mux_module(fp, cur_spice_mux_model, is_explicit_mapping); /* Update the statistics*/ mux_cnt++; if ((-1 == max_mux_size)||(max_mux_size < cur_spice_mux_model->size)) { @@ -3234,7 +3243,8 @@ void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info, int num_switch, t_switch_inf* switches, t_spice* spice, - t_det_routing_arch* routing_arch) { + t_det_routing_arch* routing_arch, + bool is_explicit_mapping) { /* Statisitcs for input sizes and structures of MUXes * used in FPGA architecture @@ -3308,7 +3318,8 @@ void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info, cur_spice_mux_model->spice_mux_arch = (t_spice_mux_arch*)my_malloc(sizeof(t_spice_mux_arch)); init_spice_mux_arch(cur_spice_mux_model->spice_model, cur_spice_mux_model->spice_mux_arch, cur_spice_mux_model->size); /* Print the mux mem subckt */ - dump_verilog_mux_mem_module(fp, cur_spice_mux_model); + dump_verilog_mux_mem_module(fp, cur_spice_mux_model, + is_explicit_mapping); /* Update the statistics*/ /* Move on to the next*/ temp = temp->next; @@ -3485,7 +3496,7 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, /* 1. MUXes */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of multiplexers...\n"); dump_verilog_submodule_muxes(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, - switch_inf, Arch.spice, routing_arch); + switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); /* 2. LUTes */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of LUTs...\n"); @@ -3502,7 +3513,7 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, /* 4. Memories */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of memories...\n"); dump_verilog_submodule_memories(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, - switch_inf, Arch.spice, routing_arch); + switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); /* 5. Dump decoder modules only when memory bank is required */ dump_verilog_config_peripherals(cur_sram_orgz_info, verilog_dir, submodule_dir); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index f120ddd7c..3a5e134f5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -3166,7 +3166,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, break; case SPICE_SRAM_SCAN_CHAIN: /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } if (SPICE_MODEL_MUX == cur_verilog_model->type) { From 370ce23646e00197b79b572600e6fc9e5940c453 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 1 Jul 2019 13:58:24 -0600 Subject: [PATCH 06/24] Mux explicit verilog done --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 175 ++++++++++++++---- 1 file changed, 143 insertions(+), 32 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 5bcc70cb8..6b985dc70 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1153,7 +1153,8 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name, t_spice_model spice_model, t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { + int num_sram_port, t_spice_model_port** sram_port, + bool is_explicit_mapping) { int i, j, level, nextlevel; int nextj, out_idx; int mux_basis_cnt = 0; @@ -1225,17 +1226,41 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, /* Each basis mux2to1: svdd sgnd */ fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } /* For intermediate buffers */ if (TRUE == inter_buf_loc[level]) { - fprintf(fp, "mux2_l%d_in_buf[%d:%d], ", level, j, nextj); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in_buf[%d:%d]", level, j, nextj); /* input0 input1 */ } else { - fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, nextj); /* input0 input1 */ + } + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[%d]", sram_port[0]->prefix, i); /* sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, "));\n"); + } else { + fprintf(fp, ");\n"); } - fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ - fprintf(fp, "%s[%d], %s_inv[%d]);\n", sram_port[0]->prefix, i, sram_port[0]->prefix, i); /* sram sram_inv */ /* For intermediate buffers */ if (TRUE == inter_buf_loc[nextlevel]) { /* Find the input port, output port, and sram port*/ @@ -1302,7 +1327,8 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, char* mux_special_basis_subckt_name, t_spice_model spice_model, t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { + int num_sram_port, t_spice_model_port** sram_port, + bool is_explicit_mapping) { int i, j, level, nextlevel, sram_idx; int out_idx; int mux_basis_cnt = 0; @@ -1348,14 +1374,36 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, /* Print the special basis */ fprintf(fp, "%s special_basis(", mux_special_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } - fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ - fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ - fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ", - sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1, + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d:%d]", sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ");\n"); special_basis_cnt++; } @@ -1365,16 +1413,38 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } - fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ - fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ /* Print number of sram bits for this basis */ - fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ", - sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1, + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d:%d]", sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); - fprintf(fp, ");\n"); + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ");"); fprintf(fp, "\n"); /* Update the counter */ mux_basis_cnt++; @@ -1393,7 +1463,8 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, char* mux_basis_subckt_name, t_spice_model spice_model, t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { + int num_sram_port, t_spice_model_port** sram_port, + bool is_explicit_mapping) { /* Make sure we have a valid file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); @@ -1407,23 +1478,61 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, + my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } fprintf(fp, "//----- MUX inputs -----\n"); - fprintf(fp, "mux2_l%d_in[0:%d], ", 1, spice_mux_arch.num_input - 1); /* input0 */ - fprintf(fp, "mux2_l%d_in[%d], ", 0, 0); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "mux2_l%d_in[0:%d]", 1, spice_mux_arch.num_input - 1); /* input0 */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", 0, 0); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "),"); + } else { + fprintf(fp, ","); + } fprintf(fp, "\n"); fprintf(fp, "//----- SRAM ports -----\n"); /* Special basis for 2-input MUX, there is only one configuration bit */ if (2 == spice_mux_arch.num_input) { - fprintf(fp, "%s[0:%d], %s_inv[0:%d] ", - sram_port[0]->prefix, 0, - sram_port[0]->prefix, 0); /* sram sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ".mem("); + } + fprintf(fp, "%s[0:%d]", + sram_port[0]->prefix, 0); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[0:%d]", + sram_port[0]->prefix, 0); /* sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } } else { - fprintf(fp, "%s[0:%d], %s_inv[0:%d] ", - sram_port[0]->prefix, spice_mux_arch.num_input - 1, - sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ".mem("); + } + fprintf(fp, "%s[0:%d]", + sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[0:%d]", + sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } } fprintf(fp, "\n"); fprintf(fp, ");\n"); @@ -1542,7 +1651,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, } else { fprintf(fp, "//----- CMOS MUX info: spice_model_name=%s, size=%d, structure: %s -----\n", spice_model.name, mux_size, gen_str_spice_model_structure(spice_model.design_tech_info.mux_info->structure)); - fprintf(fp, "module %s (", + fprintf(fp, "module %s (\n", gen_verilog_one_mux_module_name(&spice_model, mux_size)); /* Print input ports*/ fprintf(fp, "input wire [0:%d] %s,\n", mux_size - 1, input_port[0]->prefix); @@ -1569,15 +1678,17 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, switch (cur_mux_structure) { case SPICE_MODEL_STRUCTURE_TREE: dump_verilog_cmos_mux_tree_structure(fp, mux_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); + spice_model, spice_mux_arch, num_sram_port, sram_port, is_explicit_mapping); break; case SPICE_MODEL_STRUCTURE_ONELEVEL: dump_verilog_cmos_mux_onelevel_structure(fp, mux_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); + spice_model, spice_mux_arch, + num_sram_port, sram_port, is_explicit_mapping); break; case SPICE_MODEL_STRUCTURE_MULTILEVEL: dump_verilog_cmos_mux_multilevel_structure(fp, mux_basis_subckt_name, mux_special_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); + spice_model, spice_mux_arch, num_sram_port, sram_port, + is_explicit_mapping); break; default: vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", From f189ef1d8fc9253502ef6324be2b5f4d4d8eb83f Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 1 Jul 2019 14:24:09 -0600 Subject: [PATCH 07/24] Done with the submodules --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 47 +++++++++++++++---- 1 file changed, 39 insertions(+), 8 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 6b985dc70..269516054 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2683,7 +2683,8 @@ void dump_verilog_wire_module(FILE* fp, /* Dump one module of a LUT */ void dump_verilog_submodule_one_lut(FILE* fp, - t_spice_model* verilog_model) { + t_spice_model* verilog_model, + bool is_explicit_mapping) { int num_input_port = 0; int num_output_port = 0; int num_sram_port = 0; @@ -3055,19 +3056,47 @@ void dump_verilog_submodule_one_lut(FILE* fp, verilog_model->name, verilog_model->name); /* Connect MUX inputs to LUT configuration port */ assert(FALSE == sram_port[sram_port_index]->mode_select); - fprintf(fp, " %s_out,", + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "%s_out", sram_port[sram_port_index]->prefix); + if (true == is_explicit_mapping) { + fprintf(fp, "), "); + } else { + fprintf(fp, ", "); + } /* Connect MUX output to LUT output */ for (iport = 0; iport < num_output_port; iport++) { - fprintf(fp, " %s,", + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + output_port[iport]->prefix); + } + fprintf(fp, "%s", output_port[iport]->prefix); + if (true == is_explicit_mapping) { + fprintf(fp, "), "); + } else { + fprintf(fp, ", "); + } } /* Connect MUX configuration port to LUT inputs */ - fprintf(fp, " %s_buf,", + if (true == is_explicit_mapping) { + fprintf(fp, ".sram("); + } + fprintf(fp, "%s_buf", input_port[0]->prefix); /* Connect MUX inverted configuration port to inverted LUT inputs */ - fprintf(fp, " %s_b", + if (true == is_explicit_mapping) { + fprintf(fp, "), sram_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_b", input_port[0]->prefix); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* End of call LUT MUX */ fprintf(fp, ");\n"); @@ -3168,7 +3197,8 @@ void dump_verilog_submodule_luts(char* verilog_dir, int num_spice_model, t_spice_model* spice_models, boolean include_timing, - boolean include_signal_init) { + boolean include_signal_init, + bool is_explicit_mapping) { FILE* fp = NULL; char* verilog_name = my_strcat(submodule_dir, luts_verilog_file_name); int imodel; @@ -3190,7 +3220,7 @@ void dump_verilog_submodule_luts(char* verilog_dir, continue; } if (SPICE_MODEL_LUT == spice_models[imodel].type) { - dump_verilog_submodule_one_lut(fp, &(spice_models[imodel])); + dump_verilog_submodule_one_lut(fp, &(spice_models[imodel]), is_explicit_mapping); } } @@ -3614,7 +3644,8 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_submodule_luts(verilog_dir, submodule_dir, Arch.spice->num_spice_model, Arch.spice->spice_models, fpga_verilog_opts.include_timing, - fpga_verilog_opts.include_signal_init); + fpga_verilog_opts.include_signal_init, + fpga_verilog_opts.dump_explicit_verilog); /* 3. Hardwires */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of hardwires...\n"); From 8f5ad2eb67ac39e5e6ee1db83a98c058d9109a0e Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Tue, 2 Jul 2019 10:10:48 -0600 Subject: [PATCH 08/24] Snapshot of progress --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 +- .../verilog/verilog_compact_netlist.c | 32 +++--- .../verilog/verilog_compact_netlist.h | 3 +- .../fpga_x2p/verilog/verilog_report_timing.c | 21 ++-- .../SRC/fpga_x2p/verilog/verilog_routing.c | 98 ++++++++++++------- .../SRC/fpga_x2p/verilog/verilog_routing.h | 9 +- .../vpr/SRC/fpga_x2p/verilog/verilog_sdc.c | 18 ++-- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 2 +- .../SRC/fpga_x2p/verilog/verilog_tcl_utils.c | 10 +- .../SRC/fpga_x2p/verilog/verilog_tcl_utils.h | 6 +- .../verilog/verilog_top_netlist_utils.c | 23 +++-- .../verilog/verilog_top_netlist_utils.h | 4 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 28 +++++- 13 files changed, 162 insertions(+), 94 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 20ea51ecd..41b2c634c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -277,7 +277,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, num_rr_nodes, rr_node, rr_node_indices, num_clocks, vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy, - *(Arch.spice)); + *(Arch.spice), vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* Dump SDC constraints */ /* Output SDC to contrain the P&R flow diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 4187a0904..5e83ecca7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -750,7 +750,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, static void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - const RRGSB& rr_sb) { + const RRGSB& rr_sb, + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -797,7 +798,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, - FALSE); /* Do not specify the direction of port */ + FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } fprintf(fp, "\n"); @@ -850,7 +851,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz static void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp) { + FILE* fp, bool is_explicit_mapping) { DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range(); /* Check the file handler*/ @@ -863,7 +864,7 @@ void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_i for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy); - dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, rr_sb); + dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, rr_sb, is_explicit_mapping); } } @@ -878,7 +879,8 @@ void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_i static void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - const RRGSB& rr_gsb, t_rr_type cb_type) { + const RRGSB& rr_gsb, t_rr_type cb_type, + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -928,7 +930,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), cur_ipin_node->xlow, cur_ipin_node->ylow, - FALSE); /* Do not specify direction of port */ + FALSE, is_explicit_mapping); /* Do not specify direction of port */ fprintf(fp, ", \n"); } } @@ -974,7 +976,8 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ /* Call the sub-circuits for connection boxes */ static void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp) { + FILE* fp, + bool is_explicit_mapping) { DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range(); /* Check the file handler*/ @@ -994,7 +997,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or /* X - channels [1...nx][0..ny]*/ if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_x())) &&(true == rr_gsb.is_cb_exist(CHANX))) { - dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX); + dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX, is_explicit_mapping); } /* Get X-channel CB coordinator */ @@ -1002,7 +1005,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or /* Y - channels [1...ny][0..nx]*/ if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_x())) &&(true == rr_gsb.is_cb_exist(CHANY))) { - dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY); + dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY, is_explicit_mapping); } } } @@ -1183,7 +1186,8 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, t_ivec*** LL_rr_node_indices, int num_clock, boolean compact_routing_hierarchy, - t_spice verilog) { + t_spice verilog, + bool is_explicit_mapping) { FILE* fp = NULL; char* formatted_dir_path = NULL; char* temp_include_file_path = NULL; @@ -1243,16 +1247,16 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, /* Quote Routing structures: Switch Boxes */ if (TRUE == compact_routing_hierarchy ) { - dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp); + dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); } else { - dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp); + dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); /* BC: Explicit mapping not done because we will erase this in the future*/ } /* Quote Routing structures: Connection Boxes */ if (TRUE == compact_routing_hierarchy ) { - dump_compact_verilog_defined_connection_boxes(cur_sram_orgz_info, fp); + dump_compact_verilog_defined_connection_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); } else { - dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp); + dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); } /* Quote defined Logic blocks subckts (Grids) */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h index cf3898dc8..5086722d2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h @@ -26,5 +26,6 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, t_ivec*** LL_rr_node_indices, int num_clock, boolean compact_routing_hierarchy, - t_spice verilog); + t_spice verilog, + bool is_explicit_verilog); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c index f1f6ca6a7..87487220c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c @@ -284,7 +284,7 @@ void verilog_generate_one_report_timing_within_sb(FILE* fp, fprintf(fp, "%s/", rr_sb.gen_sb_verilog_instance_name()); /* Find which side the ending pin locates, and determine the coordinate */ - dump_verilog_one_sb_routing_pin(fp, rr_sb, src_rr_node); + dump_verilog_one_sb_routing_pin(fp, rr_sb, src_rr_node, false); fprintf(fp, " -to "); @@ -326,7 +326,7 @@ void verilog_generate_one_report_timing_within_sb(FILE* fp, fprintf(fp, "%s/", gen_verilog_one_sb_instance_name(cur_sb_info)); /* Find which side the ending pin locates, and determine the coordinate */ - dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node); + dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node, false); fprintf(fp, " -to "); @@ -906,7 +906,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, "%s/", src_sb.gen_sb_verilog_instance_name()); /* Find which side the ending pin locates, and determine the coordinate */ - dump_verilog_one_sb_routing_pin(fp, src_sb, drive_rr_node); + dump_verilog_one_sb_routing_pin(fp, src_sb, drive_rr_node, false); /* Switch depends on the type of des_rr_node */ switch(des_rr_node->type) { @@ -1287,7 +1287,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, "%s/", gen_verilog_one_sb_instance_name(src_sb_info)); /* Find which side the ending pin locates, and determine the coordinate */ - dump_verilog_one_sb_routing_pin(fp, src_sb_info, drive_rr_node); + dump_verilog_one_sb_routing_pin(fp, src_sb_info, drive_rr_node, false); /* Switch depends on the type of des_rr_node */ switch(des_rr_node->type) { @@ -2079,7 +2079,7 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp, fprintf(fp, "%s/", rr_sb.gen_sb_verilog_instance_name()); /* output pin name */ dump_verilog_one_sb_routing_pin(fp, rr_sb, - wire_rr_node->drive_rr_nodes[iedge]); + wire_rr_node->drive_rr_nodes[iedge], false); fprintf(fp, " -to "); /* output instance name */ fprintf(fp, "%s/", @@ -2137,14 +2137,14 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp, rr_sb.gen_sb_verilog_instance_name()); /* output pin name */ dump_verilog_one_sb_routing_pin(fp, rr_sb, - wire_rr_node->drive_rr_nodes[iedge]); + wire_rr_node->drive_rr_nodes[iedge], false); fprintf(fp, " -to "); /* output instance name */ fprintf(fp, "%s/", next_sb.gen_sb_verilog_instance_name()); /* Find which side the ending pin locates, and determine the coordinate */ dump_verilog_one_sb_routing_pin(fp, next_sb, - wire_rr_node); + wire_rr_node, false); /* Print through pins */ if (TRUE == sdc_opts.print_thru_pins) { fprintf(fp, " -through_pins "); @@ -2245,7 +2245,8 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp, gen_verilog_one_sb_instance_name(cur_sb_info)); /* output pin name */ dump_verilog_one_sb_routing_pin(fp, cur_sb_info, - wire_rr_node->drive_rr_nodes[iedge]); + wire_rr_node->drive_rr_nodes[iedge], + false); fprintf(fp, " -to "); /* output instance name */ fprintf(fp, "%s/", @@ -2289,14 +2290,14 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp, gen_verilog_one_sb_instance_name(cur_sb_info)); /* output pin name */ dump_verilog_one_sb_routing_pin(fp, cur_sb_info, - wire_rr_node->drive_rr_nodes[iedge]); + wire_rr_node->drive_rr_nodes[iedge], false); fprintf(fp, " -to "); /* output instance name */ fprintf(fp, "%s/", gen_verilog_one_sb_instance_name(next_sb)); /* Find which side the ending pin locates, and determine the coordinate */ dump_verilog_one_sb_routing_pin(fp, next_sb, - wire_rr_node); + wire_rr_node, false); /* Print through pins */ if (TRUE == sdc_opts.print_thru_pins) { fprintf(fp, " -through_pins "); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 1e69c6998..e052d24b0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -311,7 +311,8 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, - boolean dump_port_type) { + boolean dump_port_type, + bool is_explicit_mapping) { int height; t_type_ptr type = NULL; char* verilog_port_type = NULL; @@ -355,7 +356,13 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, if (TRUE == dump_port_type) { fprintf(fp, "%s ", verilog_port_type); } + if (true == is_explicit_mapping) { + fprintf(fp, ".out("); + } fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } if (TRUE == dump_port_type) { fprintf(fp, ",\n"); } @@ -511,7 +518,8 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, enum e_side chan_side, t_rr_node* cur_rr_node, int actual_fan_in, - t_rr_node* drive_rr_node) { + t_rr_node* drive_rr_node, + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -554,7 +562,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_node), grid_x, grid_y, - FALSE); /* Do not dump the direction of the port! */ + FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ break; case CHANX: case CHANY: @@ -600,7 +608,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp, int chan_side, t_rr_node* cur_rr_node, int actual_fan_in, - t_rr_node* drive_rr_node) { + t_rr_node* drive_rr_node, + bool is_explicit_mapping) { int side, index; int grid_x, grid_y; char* chan_name = NULL; @@ -655,7 +664,7 @@ void dump_verilog_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], grid_x, grid_y, - FALSE); /* Do not dump the direction of the port! */ + FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ break; case CHANX: case CHANY: @@ -760,7 +769,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], - grid_x, grid_y, FALSE); + grid_x, grid_y, FALSE, is_explicit_mapping); fprintf(fp, ";\n"); input_cnt++; break; @@ -1016,7 +1025,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]), - grid_x, grid_y, FALSE); + grid_x, grid_y, FALSE, is_explicit_mapping); fprintf(fp, ";\n"); input_cnt++; break; @@ -1394,11 +1403,12 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (0 == num_drive_rr_nodes) { /* Print a special direct connection*/ dump_verilog_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node, - num_drive_rr_nodes, cur_rr_node); + num_drive_rr_nodes, cur_rr_node, is_explicit_mapping); } else if (1 == num_drive_rr_nodes) { /* Print a direct connection*/ dump_verilog_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]); + num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID], + is_explicit_mapping); } else if (1 < num_drive_rr_nodes) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_switch_box_mux(cur_sram_orgz_info, fp, cur_sb_info, chan_side, cur_rr_node, @@ -1445,11 +1455,13 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (0 == num_drive_rr_nodes) { /* Print a special direct connection*/ dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, cur_rr_node); + num_drive_rr_nodes, cur_rr_node, + is_explicit_mapping); } else if (1 == num_drive_rr_nodes) { /* Print a direct connection*/ dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]); + num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID], + is_explicit_mapping); } else if (1 < num_drive_rr_nodes) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node, @@ -1696,7 +1708,8 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, const RRGSB& rr_sb, enum e_side sb_side, size_t seg_id, - boolean dump_port_type) { + boolean dump_port_type, + bool is_explicit_mapping) { /* Check file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR, @@ -1764,7 +1777,7 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, - dump_port_type); /* Dump the direction of the port ! */ + dump_port_type, is_explicit_mapping); /* Dump the direction of the port ! */ if (FALSE == dump_port_type) { fprintf(fp, ",\n"); } @@ -1861,7 +1874,9 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr fprintf(fp, ",\n"); } - dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side, seg_id, TRUE); + dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side, + seg_id, TRUE, + is_explicit_mapping); /* Put down configuration port */ /* output of each configuration bit */ @@ -1962,7 +1977,8 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr static void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - const RRGSB& rr_sb) { + const RRGSB& rr_sb, + bool is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; @@ -2029,7 +2045,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE); /* Dump the direction of the port ! */ + TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2110,7 +2126,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or fprintf(fp, ",\n"); } - dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_gsb, side_manager.get_side(), seg_ids[iseg], FALSE); + dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_gsb, side_manager.get_side(), seg_ids[iseg], FALSE, is_explicit_mapping); /* Put down configuration port */ /* output of each configuration bit */ @@ -2272,7 +2288,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE); /* Dump the direction of the port ! */ + TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2474,7 +2490,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info cur_sb_info->opin_rr_node_grid_side[side][inode], cur_sb_info->opin_rr_node[side][inode]->xlow, cur_sb_info->opin_rr_node[side][inode]->ylow, - TRUE); /* Dump the direction of the port ! */ + TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2663,7 +2679,8 @@ int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* c static void dump_verilog_connection_box_short_interc(FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + bool is_explicit_mapping) { t_rr_node* drive_rr_node = NULL; int iedge, check_flag; int xlow, ylow, height, index; @@ -2717,7 +2734,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ - FALSE); /* Do not specify the direction of this pin */ + FALSE, is_explicit_mapping); /* Do not specify the direction of this pin */ /* End */ fprintf(fp, ";\n"); @@ -2729,7 +2746,8 @@ void dump_verilog_connection_box_short_interc(FILE* fp, /* SRC rr_node is the IPIN of a grid.*/ void dump_verilog_connection_box_short_interc(FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + bool is_explicit_mapping) { t_rr_node* drive_rr_node = NULL; int iedge, check_flag; int xlow, ylow, height, side, index; @@ -2793,7 +2811,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ - FALSE); /* Do not specify the direction of this pin */ + FALSE, is_explicit_mapping); /* Do not specify the direction of this pin */ /* End */ fprintf(fp, ";\n"); @@ -2940,7 +2958,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ - FALSE); /* Do not specify the direction of port */ + FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ", "); /* Different design technology requires different configuration bus! */ @@ -3158,8 +3176,15 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, } /* connect to input bus*/ - fprintf(fp, "%s_size%d_%d_inbus,", + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "%s_size%d_%d_inbus", verilog_model->prefix, mux_size, verilog_model->cnt); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ", "); /* output port*/ xlow = src_rr_node->xlow; @@ -3174,7 +3199,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ - FALSE); /* Do not specify the direction of port */ + FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ", "); /* Different design technology requires different configuration bus! */ @@ -3280,7 +3305,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (1 == src_rr_node->fan_in) { /* Print a direct connection*/ - dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node); + dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node, is_explicit_mapping); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type, @@ -3309,7 +3334,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (1 == src_rr_node->fan_in) { /* Print a direct connection*/ - dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node); + dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node, is_explicit_mapping); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, @@ -3500,7 +3525,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow, rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow, - TRUE); + TRUE, is_explicit_mapping); } } @@ -3720,7 +3745,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, - TRUE); + TRUE, is_explicit_mapping); } } @@ -3900,7 +3925,8 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* Output unique modules */ for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) { const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); - dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror); + dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, + subckt_dir, unique_mirror, explicit_port_mapping); } /* Restore sram_orgz_info to the base */ @@ -3923,7 +3949,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(sb_info[ix][iy]), compact_routing_hierarchy, - FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + explicit_port_mapping); update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); } } @@ -3941,7 +3967,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb); dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX, - FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + explicit_port_mapping); } /* Y - channels [1...ny][0..nx]*/ @@ -3949,7 +3975,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb); dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY, - FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + explicit_port_mapping); } /* Restore sram_orgz_info to the base */ @@ -3979,7 +4005,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, verilog_dir, subckt_dir, &(cbx_info[ix][iy]), compact_routing_hierarchy, - FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + explicit_port_mapping); } update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); } @@ -3995,7 +4021,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, verilog_dir, subckt_dir, &(cby_info[ix][iy]), compact_routing_hierarchy, - FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + explicit_port_mapping); } update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index e3038477b..b126300e7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -14,7 +14,8 @@ void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, - boolean dump_port_type); + boolean dump_port_type, + bool is_explicit_mapping); void dump_verilog_grid_side_pins(FILE* fp, t_rr_type pin_type, int x, int y, int side, @@ -31,7 +32,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp, int chan_side, t_rr_node* cur_rr_node, int actual_fan_in, - t_rr_node* drive_rr_node); + t_rr_node* drive_rr_node, + bool is_explicit_mapping); void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -76,7 +78,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info void dump_verilog_connection_box_short_interc(FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node); + t_rr_node* src_rr_node, + bool is_explicit_mapping); void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index 20a988a09..a57ff6416 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -468,7 +468,7 @@ void verilog_generate_sdc_constrain_one_sb_path(FILE* fp, fprintf(fp, " -from "); fprintf(fp, "%s/", gen_verilog_one_sb_instance_name(cur_sb_info)); - dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node); + dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node, false); fprintf(fp, " -to "); @@ -513,7 +513,7 @@ void verilog_generate_sdc_constrain_one_sb_path(FILE* fp, fprintf(fp, " -from "); fprintf(fp, "%s/", rr_gsb.gen_sb_verilog_instance_name()); - dump_verilog_one_sb_routing_pin(fp, rr_gsb, src_rr_node); + dump_verilog_one_sb_routing_pin(fp, rr_gsb, src_rr_node, false); fprintf(fp, " -to "); @@ -638,7 +638,7 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, des_rr_node->xlow, des_rr_node->ylow, - FALSE); + FALSE, false); /* If src_node == des_node, this is a metal wire */ fprintf(fp, " %.2g", tmax); @@ -721,7 +721,7 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, mirror_ipin_node->xlow, mirror_ipin_node->ylow, - FALSE); + FALSE, false); /* If src_node == des_node, this is a metal wire */ fprintf(fp, " %.2g", tmax); @@ -1639,7 +1639,8 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp) { fprintf(fp, "%s/", rr_sb.gen_sb_verilog_instance_name()); dump_verilog_one_sb_routing_pin(fp, rr_sb, - rr_sb.get_opin_node(side_manager.get_side(), inode)); + rr_sb.get_opin_node(side_manager.get_side(), + inode), false); fprintf(fp, "\n"); } } @@ -1708,7 +1709,8 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp, fprintf(fp, "%s/", gen_verilog_one_sb_instance_name(cur_sb_info)); dump_verilog_one_sb_routing_pin(fp, cur_sb_info, - cur_sb_info->opin_rr_node[side][inode]); + cur_sb_info->opin_rr_node[side][inode], + false); fprintf(fp, "\n"); } } @@ -1758,7 +1760,7 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), ipin_node->xlow, ipin_node->ylow, - FALSE); /* Do not specify direction of port */ + FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } } @@ -1816,7 +1818,7 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, - FALSE); /* Do not specify direction of port */ + FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 269516054..b91ffc3e6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2345,7 +2345,7 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp, * 3. output ports * 4. bl/wl ports */ - dump_verilog_mem_module_port_map(fp, mem_model, TRUE, 0, num_conf_bits, FALSE); + dump_verilog_mem_module_port_map(fp, mem_model, TRUE, 0, num_conf_bits, my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, ");\n"); /* Dump all the submodules */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c index 845bb7cf5..256f281a9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c @@ -145,7 +145,8 @@ void dump_verilog_one_sb_chan_pin(FILE* fp, /* Output the pin name of a routing wire in a SB */ void dump_verilog_one_sb_routing_pin(FILE* fp, const RRGSB& rr_sb, - t_rr_node* cur_rr_node) { + t_rr_node* cur_rr_node, + bool is_explicit_mapping) { int side; /* Check the file handler */ @@ -186,7 +187,7 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, mirror_node->xlow, mirror_node->ylow, - FALSE); /* Do not specify direction of port */ + FALSE,is_explicit_mapping); /* Do not specify direction of port */ break; } case CHANX: @@ -206,7 +207,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, /* Output the pin name of a routing wire in a SB */ void dump_verilog_one_sb_routing_pin(FILE* fp, t_sb* cur_sb_info, - t_rr_node* cur_rr_node) { + t_rr_node* cur_rr_node, + bool is_explicit_mapping) { int side; /* Check the file handler */ @@ -229,7 +231,7 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, cur_rr_node->xlow, cur_rr_node->ylow, - FALSE); /* Do not specify direction of port */ + FALSE, is_explicit_mapping); /* Do not specify direction of port */ break; case CHANX: case CHANY: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h index e0b9652cf..1db242a40 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h @@ -20,11 +20,13 @@ void dump_verilog_one_sb_chan_pin(FILE* fp, void dump_verilog_one_sb_routing_pin(FILE* fp, const RRGSB& rr_sb, - t_rr_node* cur_rr_node); + t_rr_node* cur_rr_node, + bool is_explicit_mapping); void dump_verilog_one_sb_routing_pin(FILE* fp, t_sb* cur_sb_info, - t_rr_node* cur_rr_node); + t_rr_node* cur_rr_node, + bool is_explicit_mapping); DeviceCoordinator get_chan_node_ending_cb(t_rr_node* src_rr_node, t_rr_node* end_rr_node); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 90fdf268d..267dd2c4a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -607,7 +607,8 @@ void dump_verilog_defined_channels(FILE* fp, static void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - t_cb cur_cb_info) { + t_cb cur_cb_info, + bool is_explicit_mapping) { int itrack, inode, side, x, y; int side_cnt = 0; @@ -679,7 +680,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf cur_cb_info.ipin_rr_node_grid_side[side][inode], cur_cb_info.ipin_rr_node[side][inode]->xlow, cur_cb_info.ipin_rr_node[side][inode]->ylow, - FALSE); /* Do not specify direction of port */ + FALSE, is_explicit_mapping); /* Do not specify direction of port */ fprintf(fp, ", \n"); } } @@ -735,7 +736,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf /* Call the sub-circuits for connection boxes */ void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp) { + FILE* fp, bool is_explicit_mapping) { int ix, iy; /* Check the file handler*/ @@ -750,7 +751,8 @@ void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, for (ix = 1; ix < (nx + 1); ix++) { if ((TRUE == is_cb_exist(CHANX, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { - dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cbx_info[ix][iy]); + dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cbx_info[ix][iy], + is_explicit_mapping); } } } @@ -759,7 +761,8 @@ void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, for (iy = 1; iy < (ny + 1); iy++) { if ((TRUE == is_cb_exist(CHANY, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { - dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cby_info[ix][iy]); + dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cby_info[ix][iy], + is_explicit_mapping); } } } @@ -774,7 +777,8 @@ void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, static void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - t_sb cur_sb_info) { + t_sb cur_sb_info, + bool is_explicit_mapping) { int ix, iy, side, itrack, x, y, inode; /* Check the file handler*/ @@ -823,7 +827,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, cur_sb_info.opin_rr_node_grid_side[side][inode], cur_sb_info.opin_rr_node[side][inode]->xlow, cur_sb_info.opin_rr_node[side][inode]->ylow, - FALSE); /* Do not specify the direction of port */ + FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } fprintf(fp, "\n"); @@ -869,7 +873,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, } void dump_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp) { + FILE* fp, bool is_explicit_mapping) { int ix, iy; /* Check the file handler*/ @@ -881,7 +885,8 @@ void dump_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, for (ix = 0; ix < (nx + 1); ix++) { for (iy = 0; iy < (ny + 1); iy++) { - dump_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, sb_info[ix][iy]); + dump_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, sb_info[ix][iy], + is_explicit_mapping); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h index c25c42756..74549b8d6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h @@ -13,10 +13,10 @@ void dump_verilog_defined_channels(FILE* fp, t_ivec*** LL_rr_node_indices); void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp); + FILE* fp, bool is_explicit_mapping); void dump_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp); + FILE* fp, bool is_explicit_mapping); void dump_verilog_clb2clb_directs(FILE* fp, int num_directs, t_clb_to_clb_directs* direct); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 3a5e134f5..5b7f472c0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -905,7 +905,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, if ((TRUE == require_explicit_port_map) && (TRUE == cur_spice_model->dump_explicit_port_map)) { fprintf(fp, ".%s(", - cur_spice_model_port->lib_name); + /* cur_spice_model_port->lib_name); /* Old version*/ + cur_spice_model_port->prefix); } fprintf(fp, "%s[0:%d]", cur_spice_model_port->prefix, @@ -3155,10 +3156,10 @@ void dump_verilog_mem_sram_submodule(FILE* fp, case SPICE_SRAM_STANDALONE: /* SRAM subckts*/ /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } - fprintf(fp, "%s_out[%d:%d], ", + fprintf(fp, "%s_in[%d:%d], ", cur_sram_verilog_model->prefix, lsb, msb); /* Input*/ fprintf(fp, "%s_out[%d:%d], %s_outb[%d:%d] ", cur_sram_verilog_model->prefix, lsb, msb, @@ -3171,21 +3172,42 @@ void dump_verilog_mem_sram_submodule(FILE* fp, } if (SPICE_MODEL_MUX == cur_verilog_model->type) { /* Input of Scan-chain DFF, should be connected to the output of its precedent */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[0].prefix); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, -1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", \n"); // /* Output of Scan-chain DFF, should be connected to the output of its successor */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[1].prefix); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", \n"); // + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[2].prefix); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, 1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } break; } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ From b08513d9029c679e1984f7e58f265b232a643592 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Tue, 2 Jul 2019 14:12:42 -0600 Subject: [PATCH 09/24] Big chunk added on the routing part of the explicit mapping --- .../verilog/verilog_autocheck_top_testbench.c | 4 +- .../verilog/verilog_compact_netlist.c | 73 ++++++----- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 22 ++-- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 4 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 119 ++++++++++++------ .../verilog/verilog_top_netlist_utils.c | 44 ++++--- .../verilog/verilog_top_netlist_utils.h | 9 +- .../fpga_x2p/verilog/verilog_top_testbench.c | 7 +- .../fpga_x2p/verilog/verilog_top_testbench.h | 3 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 43 +++++-- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 9 +- .../verilog_verification_top_netlist.c | 6 +- 12 files changed, 222 insertions(+), 121 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c index 7fa549e9e..e3c234c08 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c @@ -354,6 +354,7 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, t_spice verilog) { FILE* fp = NULL; char* title = my_strcat("FPGA Verilog Testbench for Top-level netlist of Design: ", circuit_name); + bool is_explicit_mapping = fpga_verilog_opts.dump_explicit_verilog; /* Check if the path exists*/ fp = fopen(top_netlist_name,"w"); @@ -379,7 +380,8 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_top_auto_testbench_ports(fp, cur_sram_orgz_info, circuit_name, fpga_verilog_opts); /* Call defined top-level module */ - dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name); + dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, + circuit_name, is_explicit_mapping); /* Call defined benchmark */ dump_verilog_top_auto_testbench_call_benchmark(fp, circuit_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 5e83ecca7..57be783cf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -361,7 +361,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "module %s ( \n", subckt_name); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -406,7 +406,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, 0, temp_conf_bits_msb - 1, - VERILOG_PORT_INPUT); // Should be modified to be VERILOG_PORT_INPUT + VERILOG_PORT_INPUT, is_explicit_mapping); // Should be modified to be VERILOG_PORT_INPUT fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -430,7 +430,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, " %s (", gen_verilog_one_phy_block_instance_name(phy_block_type, iz)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } /* Print all the pins */ @@ -464,7 +464,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "//---- SRAM ----\n"); dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, temp_conf_bits_lsb, temp_conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ @@ -475,7 +475,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, temp_conf_bits_lsb, temp_conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -592,7 +592,8 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, static void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - int ix, int iy, int border_side) { + int ix, int iy, int border_side, + bool is_explicit_mapping) { char* subckt_name = NULL; if (NULL == fp) { @@ -616,7 +617,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -648,7 +649,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, cur_sram_orgz_info->grid_conf_bits_lsb[ix][iy], cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ @@ -660,7 +661,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sram_orgz_info->grid_conf_bits_lsb[ix][iy], cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -676,7 +677,8 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, */ static void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp) { + FILE* fp, + bool is_explicit_mapping) { int ix, iy; if (NULL == fp) { @@ -692,7 +694,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, continue; } assert(IO_TYPE != grid[ix][iy].type); - dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, -1); + dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, + ix, iy, -1, is_explicit_mapping); } } @@ -705,7 +708,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, continue; } assert(IO_TYPE == grid[ix][iy].type); - dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 0); + dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, + ix, iy, 0, is_explicit_mapping); } /* RIGHT side */ ix = nx + 1; @@ -715,7 +719,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, continue; } assert(IO_TYPE == grid[ix][iy].type); - dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 1); + dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, + ix, iy, 1, is_explicit_mapping); } /* BOTTOM side */ @@ -726,7 +731,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, continue; } assert(IO_TYPE == grid[ix][iy].type); - dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 2); + dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, + ix, iy, 2, is_explicit_mapping); } /* LEFT side */ ix = 0; @@ -736,7 +742,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, continue; } assert(IO_TYPE == grid[ix][iy].type); - dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 3); + dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, + iy, 3, is_explicit_mapping); } @@ -775,7 +782,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -821,7 +828,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, rr_sb.get_sb_conf_bits_lsb(), rr_sb.get_sb_conf_bits_msb(), - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ @@ -833,7 +840,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_sb.get_sb_conf_bits_lsb(), rr_sb.get_sb_conf_bits_msb(), - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -901,7 +908,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -949,7 +956,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, rr_gsb.get_cb_conf_bits_lsb(cb_type), rr_gsb.get_cb_conf_bits_msb(cb_type), - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ if (0 < rr_gsb.get_cb_num_conf_bits(cb_type)) { @@ -959,7 +966,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_cb_conf_bits_lsb(cb_type), rr_gsb.get_cb_conf_bits_msb(cb_type), - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -1019,7 +1026,9 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or static void dump_compact_verilog_defined_one_channel(FILE* fp, int x, int y, - const RRChan& rr_chan, size_t subckt_id) { + const RRChan& rr_chan, + size_t subckt_id, + bool is_explicit_mapping) { if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); exit(1); @@ -1053,7 +1062,7 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -1140,7 +1149,8 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, /* Call the sub-circuits for channels : Channel X and Channel Y*/ static -void dump_compact_verilog_defined_channels(FILE* fp) { +void dump_compact_verilog_defined_channels(FILE* fp, + bool is_explicit_mapping) { int ix, iy; if (NULL == fp) { @@ -1153,7 +1163,8 @@ void dump_compact_verilog_defined_channels(FILE* fp) { for (ix = 1; ix < (nx + 1); ix++) { dump_compact_verilog_defined_one_channel(fp, ix, iy, device_rr_chan.get_module_with_coordinator(CHANX, ix, iy), - device_rr_chan.get_module_id(CHANX, ix, iy)); + device_rr_chan.get_module_id(CHANX, ix, iy), + is_explicit_mapping); } } @@ -1162,7 +1173,8 @@ void dump_compact_verilog_defined_channels(FILE* fp) { for (iy = 1; iy < (ny + 1); iy++) { dump_compact_verilog_defined_one_channel(fp, ix, iy, device_rr_chan.get_module_with_coordinator(CHANY, ix, iy), - device_rr_chan.get_module_id(CHANY, ix, iy)); + device_rr_chan.get_module_id(CHANY, ix, iy), + is_explicit_mapping); } } @@ -1234,15 +1246,16 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, my_free(temp_include_file_path); /* Print all global wires*/ - dump_verilog_top_netlist_ports(cur_sram_orgz_info, fp, num_clock, circuit_name, verilog); + dump_verilog_top_netlist_ports(cur_sram_orgz_info, fp, num_clock, + circuit_name, verilog, is_explicit_mapping); dump_verilog_top_netlist_internal_wires(cur_sram_orgz_info, fp); /* Quote Routing structures: Channels */ if (TRUE == compact_routing_hierarchy ) { - dump_compact_verilog_defined_channels(fp); + dump_compact_verilog_defined_channels(fp, is_explicit_mapping); } else { - dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping); } /* Quote Routing structures: Switch Boxes */ @@ -1260,7 +1273,7 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, } /* Quote defined Logic blocks subckts (Grids) */ - dump_compact_verilog_defined_grids(cur_sram_orgz_info, fp); + dump_compact_verilog_defined_grids(cur_sram_orgz_info, fp, is_explicit_mapping); /* Apply CLB to CLB direct connections */ dump_verilog_clb2clb_directs(fp, num_clb2clb_directs, clb2clb_direct); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 1551aa028..80ed46195 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1733,7 +1733,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, */ fprintf(fp, "\n"); /* dump global ports */ - if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { fprintf(fp, ",\n"); } /* Simplify the port prefix, make SPICE netlist readable */ @@ -1772,7 +1772,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, stamped_sram_cnt, stamped_sram_cnt + num_conf_bits - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -1819,7 +1819,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, /* dump global ports */ /* If the child node is a primitive, we only dump global ports belonging to this primitive */ if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } } else { @@ -1863,7 +1863,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, stamped_sram_cnt, stamped_sram_cnt + child_pb_num_conf_bits - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ if (0 < child_pb_num_conf_bits) { @@ -1873,7 +1873,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, stamped_sram_cnt, stamped_sram_cnt + child_pb_num_conf_bits - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2552,7 +2552,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "module %s ( \n", gen_verilog_one_grid_module_name(ix, iy)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -2596,7 +2596,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_num_mem_bit, get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info) - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, + false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2624,7 +2625,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, " %s (", gen_verilog_one_block_instance_name(ix, iy, iz)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } /* Print all the pins */ @@ -2659,7 +2660,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "//---- SRAM ----\n"); dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, temp_conf_bits_lsb, temp_conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ if (0 < (temp_conf_bits_msb - 1 - temp_conf_bits_lsb)) { @@ -2669,7 +2670,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, temp_conf_bits_lsb, temp_conf_bits_msb - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, + is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index cad259077..a735d36fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -173,7 +173,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_conf_bits - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -560,7 +560,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_conf_bits - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index e052d24b0..4ff427dcf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -44,7 +44,8 @@ static void dump_verilog_routing_chan_subckt(char* verilog_dir, char* subckt_dir, size_t rr_chan_subckt_id, - const RRChan& rr_chan) { + const RRChan& rr_chan, + bool is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; @@ -78,7 +79,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, gen_verilog_one_routing_channel_module_name(rr_chan.get_type(), rr_chan_subckt_id, -1)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } /* Inputs and outputs, @@ -170,7 +171,8 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - int num_segment) { + int num_segment, + bool is_explicit_mapping) { int itrack, iseg, cost_index; int chan_width = 0; t_rr_node** chan_rr_nodes = NULL; @@ -215,7 +217,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, gen_verilog_one_routing_channel_module_name(chan_type, x, y)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } /* Inputs and outputs, @@ -355,9 +357,10 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, /* fprintf(fp, "grid_%d__%d__pin_%d__%d__%d_ ", x, y, height, side, pin_index); */ if (TRUE == dump_port_type) { fprintf(fp, "%s ", verilog_port_type); + is_explicit_mapping = false; /* Both cannot be true at the same time */ } if (true == is_explicit_mapping) { - fprintf(fp, ".out("); + fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); } fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); if (true == is_explicit_mapping) { @@ -562,7 +565,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_node), grid_x, grid_y, - FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ + FALSE, false); /* Do not dump the direction of the port! */ break; case CHANX: case CHANY: @@ -1025,7 +1028,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]), - grid_x, grid_y, FALSE, is_explicit_mapping); + grid_x, grid_y, FALSE, false); fprintf(fp, ";\n"); input_cnt++; break; @@ -1741,11 +1744,22 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, fprintf(fp, " "); if (TRUE == dump_port_type) { fprintf(fp, "output "); + is_explicit_mapping = false; /* Both cannot be true together */ } - fprintf(fp, "%s,\n", + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), port_coordinator.get_x(), port_coordinator.get_y(), itrack, rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + } + fprintf(fp, "%s", + gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), + port_coordinator.get_x(), port_coordinator.get_y(), itrack, + rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; case IN_PORT: /* if this is not the specified side, we only consider input ports */ @@ -1756,10 +1770,20 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, if (TRUE == dump_port_type) { fprintf(fp, "input "); } - fprintf(fp, "%s,\n", + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), port_coordinator.get_x(), port_coordinator.get_y(), itrack, rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + } + fprintf(fp, "%s", + gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), + port_coordinator.get_x(), port_coordinator.get_y(), itrack, + rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; default: vpr_printf(TIO_MESSAGE_ERROR, @@ -1870,7 +1894,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_side_module_name(side, seg_id)); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } @@ -1902,7 +1926,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_num_sram, esti_sram_cnt - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2005,7 +2029,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name()); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } @@ -2076,7 +2100,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_sb_conf_bits_lsb(), rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, + is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2122,7 +2147,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or rr_gsb.gen_sb_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]), rr_gsb.gen_sb_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg])); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -2142,7 +2167,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, cur_sram_lsb, cur_sram_msb, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); /* Dump ports only visible during formal verification*/ if (0 < side_num_conf_bits) { @@ -2152,7 +2177,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sram_lsb, cur_sram_msb, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2249,7 +2274,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name()); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -2316,7 +2341,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_sb_conf_bits_lsb(), rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_OUTPUT); + VERILOG_PORT_OUTPUT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2454,7 +2479,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", gen_verilog_one_sb_module_name(cur_sb_info)); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -2517,7 +2542,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sb_info->conf_bits_lsb, cur_sb_info->conf_bits_msb - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2679,8 +2704,7 @@ int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* c static void dump_verilog_connection_box_short_interc(FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, - t_rr_node* src_rr_node, - bool is_explicit_mapping) { + t_rr_node* src_rr_node) { t_rr_node* drive_rr_node = NULL; int iedge, check_flag; int xlow, ylow, height, index; @@ -2734,7 +2758,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ - FALSE, is_explicit_mapping); /* Do not specify the direction of this pin */ + FALSE, false); /* Do not specify the direction of this pin */ /* End */ fprintf(fp, ";\n"); @@ -2811,7 +2835,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ - FALSE, is_explicit_mapping); /* Do not specify the direction of this pin */ + FALSE, false); /* Do not specify the direction of this pin */ /* End */ fprintf(fp, ";\n"); @@ -2942,8 +2966,15 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, } /* connect to input bus*/ - fprintf(fp, "%s_size%d_%d_inbus,", + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "%s_size%d_%d_inbus", verilog_model->prefix, mux_size, verilog_model->cnt); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ", "); /* output port*/ xlow = src_rr_node->xlow; @@ -2954,11 +2985,17 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, rr_gsb.get_node_side_and_index(src_rr_node, OUT_PORT, &side, &index); /* We need to be sure that drive_rr_node is part of the CB */ assert((-1 != index)&&(NUM_SIDES != side)); + if (true == is_explicit_mapping) { + fprintf(fp, ".out("); + } dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an output of a connection box */ rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ - FALSE, is_explicit_mapping); /* Do not specify the direction of port */ + FALSE, false); /* Do not specify the direction of port */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); /* Different design technology requires different configuration bus! */ @@ -3162,7 +3199,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); - fprintf(fp, "`endif\n"); + fprintf(fp, "is_explicit_mappingf\n"); /* Call the MUX SPICE model */ @@ -3195,11 +3232,17 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, get_rr_node_side_and_index_in_cb_info(src_rr_node, (*cur_cb_info), OUT_PORT, &side, &index); /* We need to be sure that drive_rr_node is part of the CB */ assert((-1 != index)&&(-1 != side)); + if (true == is_explicit_mapping) { + fprintf(fp, ".out("); + } dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an output of a connection box */ cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ - FALSE, is_explicit_mapping); /* Do not specify the direction of port */ + FALSE, false); /* Do not specify the direction of port */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); /* Different design technology requires different configuration bus! */ @@ -3305,7 +3348,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (1 == src_rr_node->fan_in) { /* Print a direct connection*/ - dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node, is_explicit_mapping); + dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type, @@ -3502,7 +3545,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra fprintf(fp, "%s ", rr_gsb.gen_cb_verilog_module_name(cb_type)); fprintf(fp, "(\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } /* Print the ports of channels*/ @@ -3525,7 +3568,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow, rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow, - TRUE, is_explicit_mapping); + TRUE, false); } } @@ -3554,7 +3597,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_cb_conf_bits_lsb(cb_type), rr_gsb.get_cb_conf_bits_msb(cb_type), - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -3704,7 +3747,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ fprintf(fp, "(\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } /* Print the ports of channels*/ @@ -3776,7 +3819,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_cb_info->conf_bits_lsb, cur_cb_info->conf_bits_msb - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -3876,13 +3919,13 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* X - channels [1...nx][0..ny]*/ for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANX); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, - ichan, device_rr_chan.get_module(CHANX, ichan)); + ichan, device_rr_chan.get_module(CHANX, ichan), explicit_port_mapping); } /* Y - channels [1...ny][0..nx]*/ vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANY); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, - ichan, device_rr_chan.get_module(CHANY, ichan)); + ichan, device_rr_chan.get_module(CHANY, ichan), explicit_port_mapping); } } else { /* Output the full array of routing channels */ @@ -3891,7 +3934,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (int ix = 1; ix < (nx + 1); ix++) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANX, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments); + arch.num_segments, explicit_port_mapping); } } /* Y - channels [1...ny][0..nx]*/ @@ -3900,7 +3943,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (int iy = 1; iy < (ny + 1); iy++) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANY, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments); + arch.num_segments, explicit_port_mapping); } } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 267dd2c4a..830cbf02c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -131,7 +131,7 @@ void dump_verilog_top_netlist_memory_bank_internal_wires(t_sram_orgz_info* cur_s fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, 0, get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info) - 1, - VERILOG_PORT_WIRE); + VERILOG_PORT_WIRE, false); fprintf(fp, ";\n"); fprintf(fp, "`endif\n"); break; @@ -217,7 +217,7 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr fprintf(fp, " "); dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, 0, num_scffs - 1, - VERILOG_PORT_WIRE); + VERILOG_PORT_WIRE, false); fprintf(fp, ";\n"); fprintf(fp, "`endif\n"); @@ -249,7 +249,8 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr /* Dump ports for the top-level module in Verilog netlist */ void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - enum e_dump_verilog_port_type dump_port_type) { + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping) { char* port_name = NULL; char split_sign; enum e_dump_verilog_port_type actual_dump_port_type; @@ -265,7 +266,7 @@ void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info, } /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, dump_global_port_type)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, dump_global_port_type, is_explicit_mapping)) { fprintf(fp, "%c\n", split_sign); } /* Inputs and outputs of I/O pads */ @@ -317,7 +318,8 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, int num_clocks, char* circuit_name, - t_spice verilog) { + t_spice verilog, + bool is_explicit_mapping) { /* int num_array_bl, num_array_wl; int bl_decoder_size, wl_decoder_size; @@ -334,7 +336,8 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "module %s_top (\n", circuit_name); fprintf(fp, "\n"); - dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_INPUT); + dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_INPUT, + is_explicit_mapping); fprintf(fp, ");\n"); @@ -367,7 +370,8 @@ void dump_verilog_top_netlist_internal_wires(t_sram_orgz_info* cur_sram_orgz_inf static void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - int ix, int iy) { + int ix, int iy, + bool is_explicit_mapping) { if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); exit(1); @@ -387,7 +391,7 @@ void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -435,7 +439,8 @@ static void dump_verilog_defined_one_channel(FILE* fp, t_rr_type chan_type, int x, int y, int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { + t_ivec*** LL_rr_node_indices, + bool is_explicit_mapping) { int itrack; int chan_width = 0; t_rr_node** chan_rr_nodes = NULL; @@ -477,7 +482,7 @@ void dump_verilog_defined_one_channel(FILE* fp, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports_explicit(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -572,7 +577,8 @@ void dump_verilog_defined_one_channel(FILE* fp, /* Call the sub-circuits for channels : Channel X and Channel Y*/ void dump_verilog_defined_channels(FILE* fp, int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { + t_ivec*** LL_rr_node_indices, + bool is_explicit_mapping) { int ix, iy; if (NULL == fp) { @@ -584,7 +590,7 @@ void dump_verilog_defined_channels(FILE* fp, for (iy = 0; iy < (ny + 1); iy++) { for (ix = 1; ix < (nx + 1); ix++) { dump_verilog_defined_one_channel(fp, CHANX, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping); } } @@ -592,7 +598,7 @@ void dump_verilog_defined_channels(FILE* fp, for (ix = 0; ix < (nx + 1); ix++) { for (iy = 1; iy < (ny + 1); iy++) { dump_verilog_defined_one_channel(fp, CHANY, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping); } } @@ -638,7 +644,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -699,7 +705,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf if (0 < (cur_cb_info.conf_bits_msb - cur_cb_info.conf_bits_lsb)) { dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, cur_cb_info.conf_bits_lsb, cur_cb_info.conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ if (0 < (cur_cb_info.conf_bits_msb - 1 - cur_cb_info.conf_bits_lsb)) { @@ -709,7 +715,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_cb_info.conf_bits_lsb, cur_cb_info.conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -805,7 +811,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -847,7 +853,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, cur_sb_info.conf_bits_lsb, cur_sb_info.conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ @@ -858,7 +864,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sb_info.conf_bits_lsb, cur_sb_info.conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h index 74549b8d6..91b185e08 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h @@ -3,14 +3,16 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, int num_clocks, char* circuit_name, - t_spice verilog); + t_spice verilog, + bool is_explicit_mapping); void dump_verilog_top_netlist_internal_wires(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp); void dump_verilog_defined_channels(FILE* fp, int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices); + t_ivec*** LL_rr_node_indices, + bool is_explicit_mapping); void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, bool is_explicit_mapping); @@ -26,7 +28,8 @@ void dump_verilog_configuration_circuits(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - enum e_dump_verilog_port_type dump_port_type); + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping); void verilog_compact_generate_fake_xy_for_io_border_side(int border_side, int* ix, int* iy) ; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c index ce309d764..6671ec6e4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c @@ -312,7 +312,8 @@ void dump_verilog_top_testbench_ports(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - char* circuit_name) { + char* circuit_name, + bool is_explicit_mapping) { /* int iblock, iopad_idx; */ @@ -322,7 +323,7 @@ void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_ fprintf(fp, "//------Call defined Top-level Verilog Module -----\n"); fprintf(fp, "%s_top U0 (\n", circuit_name); - dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT); + dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, ");\n"); return; @@ -1354,7 +1355,7 @@ void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_top_testbench_ports(cur_sram_orgz_info, fp, circuit_name); /* Call defined top-level module */ - dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name); + dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name, false); /* Add stimuli for reset, set, clock and iopad signals */ dump_verilog_top_testbench_stimuli(cur_sram_orgz_info, fp, verilog); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h index 320786a40..caf107479 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h @@ -6,7 +6,8 @@ void dump_verilog_top_testbench_global_ports_stimuli(FILE* fp, t_llist* head); void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - char* circuit_name); + char* circuit_name, + bool is_explicit_mapping); void dump_verilog_top_testbench_stimuli(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 5b7f472c0..c3287e7a7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -945,7 +945,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, /* Dump all the global ports that are stored in the linked list */ int dump_verilog_global_ports(FILE* fp, t_llist* head, - boolean dump_port_type) { + boolean dump_port_type, + bool is_explicit_mapping) { t_llist* temp = head; t_spice_model_port* cur_global_port = NULL; int dumped_port_cnt = 0; @@ -959,6 +960,10 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, /* fprintf(fp, "//----- BEGIN Global ports -----\n"); */ while(NULL != temp) { cur_global_port = (t_spice_model_port*)(temp->dptr); + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_global_port->prefix); + } if (TRUE == dump_port_type) { fprintf(fp, "%s [0:%d] %s", verilog_convert_port_type_to_string(cur_global_port->type), @@ -969,7 +974,9 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, cur_global_port->prefix, cur_global_port->size - 1); } - + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* if this is the tail, we do not dump a comma */ if (NULL != temp->next) { fprintf(fp, ", //---- global port \n"); @@ -1357,7 +1364,8 @@ void dump_verilog_sram_outports(FILE* fp, void dump_verilog_formal_verification_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int sram_lsb, int sram_msb, - enum e_dump_verilog_port_type dump_port_type) { + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping) { t_spice_model* mem_model = NULL; char* port_name = NULL; char* port_full_name = NULL; @@ -1394,8 +1402,14 @@ void dump_verilog_formal_verification_sram_ports(FILE* fp, /*Malloc and generate the full name of port */ port_full_name = (char*)my_malloc(sizeof(char)*(strlen(mem_model->prefix) + strlen(port_name) + 1 + 1)); sprintf(port_full_name, "%s_%s", mem_model->prefix, port_name); - + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + port_full_name); + } dump_verilog_generic_port(fp, dump_port_type, port_full_name, sram_lsb, sram_msb); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* Free */ /* Local variables such as port1_name and port2 name are automatically freed */ @@ -1508,7 +1522,7 @@ void dump_verilog_formal_verification_sram_ports_wiring(FILE* fp, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, sram_lsb, sram_msb, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, false); fprintf(fp, ";\n"); return; @@ -1530,7 +1544,7 @@ void dump_verilog_formal_verification_mux_sram_ports_wiring(FILE* fp, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, sram_lsb, sram_msb, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, false); fprintf(fp, ";\n"); return; @@ -1540,7 +1554,8 @@ void dump_verilog_formal_verification_mux_sram_ports_wiring(FILE* fp, void dump_verilog_sram_local_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int sram_lsb, int sram_msb, - enum e_dump_verilog_port_type dump_port_type) { + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping) { /* Need to dump inverted BL/WL if needed */ int num_blb_ports, num_wlb_ports; t_spice_model_port** blb_port = NULL; @@ -1578,14 +1593,26 @@ void dump_verilog_sram_local_ports(FILE* fp, break; case SPICE_SRAM_SCAN_CHAIN: /* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */ + if (true == is_explicit_mapping) { + fprintf(fp, ".scff_scff_head("); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, sram_lsb, sram_lsb, -1, dump_port_type); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); /* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */ + if (true == is_explicit_mapping) { + fprintf(fp, ".scff_scff_tail("); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, sram_msb, sram_msb, 0, dump_port_type); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } break; default: vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization !\n", @@ -2582,7 +2609,7 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m if (TRUE == is_explicit_mapping) { fprintf(fp, ")"); } - fprintf(fp, ",\n"); + fprintf(fp, ", "); if (TRUE == is_explicit_mapping) { fprintf(fp, ".sram_inv("); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index cf8427720..8930d8068 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -76,7 +76,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, boolean require_explicit_port_map); int dump_verilog_global_ports(FILE* fp, t_llist* head, - boolean dump_port_type); + boolean dump_port_type, + bool is_explicit_mapping); int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head, boolean dump_port_type); @@ -115,7 +116,8 @@ void dump_verilog_sram_outports(FILE* fp, void dump_verilog_formal_verification_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int sram_lsb, int sram_msb, - enum e_dump_verilog_port_type dump_port_type); + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping); void dump_verilog_sram_one_port(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, @@ -126,7 +128,8 @@ void dump_verilog_sram_one_port(FILE* fp, void dump_verilog_sram_local_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int sram_lsb, int sram_msb, - enum e_dump_verilog_port_type dump_port_type); + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping); void dump_verilog_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int sram_lsb, int sram_msb, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c index 573c821ac..74ac2317d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c @@ -187,7 +187,7 @@ void dump_verilog_formal_verfication_top_netlist_call_top_module(t_sram_orgz_inf circuit_name, formal_verification_top_module_uut_name); - dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT); + dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT, false); fprintf(fp, ");\n"); return; @@ -338,14 +338,14 @@ void dump_verilog_formal_verification_top_netlist_config_bitstream(t_sram_orgz_i case SPICE_SRAM_SCAN_CHAIN: dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_conf_bit->index, cur_conf_bit->index, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, false); fprintf(fp, " = 1'b%d", cur_conf_bit->sram_bit->val); break; case SPICE_SRAM_MEMORY_BANK: dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_conf_bit->bl->addr, cur_conf_bit->bl->addr, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, false); fprintf(fp, " = 1'b%d", cur_conf_bit->bl->val); break; From 64d8e9663a40d8f0c3dbfdabbfc31080c6824aed Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2019 13:13:35 -0600 Subject: [PATCH 10/24] minor fix to satisfy Fc_in and Fc_out --- .../device/rr_graph/tileable_rr_graph_gsb.cpp | 24 +++++++++++++++---- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp index 02e7e4701..f1c497ca2 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp @@ -1062,13 +1062,13 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, assert (0 == actual_track_list.size() % 2); /* Scale Fc */ - int actual_Fc = Fc * actual_track_list.size() / chan_width; + int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */ actual_Fc = std::max(2, actual_Fc); /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in */ - size_t track_step = actual_track_list.size() / actual_Fc; + size_t track_step = std::ceil((float)actual_track_list.size() / (float)actual_Fc); /* Track step mush be a multiple of 2!!!*/ if (0 != track_step % 2) { track_step--; /* minus 1 to increase connectivity */ @@ -1078,7 +1078,9 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, /* Adapt offset to the range of actual_track_list */ size_t actual_offset = offset % actual_track_list.size(); /* rotate the track list by an offset */ - std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); + if (0 < actual_offset) { + std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); + } /* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step */ int track_cnt = 0; @@ -1108,6 +1110,12 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, /* Ensure the number of tracks is similar to Fc */ //printf("Fc_in=%d, track_cnt=%d\n", actual_Fc, track_cnt); assert (actual_Fc <= track_cnt); + /* Give a warning if Fc is < track_cnt */ + if (actual_Fc < track_cnt) { + vpr_printf(TIO_MESSAGE_INFO, + "Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than IPINs!\n", + ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); + } } return; @@ -1163,13 +1171,13 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, } /* Scale Fc */ - int actual_Fc = Fc * actual_track_list.size() / chan_width; + int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); /* Minimum Fc should be 1 : ensure we will drive 1 routing track */ actual_Fc = std::max(1, actual_Fc); /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in */ - size_t track_step = actual_track_list.size() / actual_Fc; + size_t track_step = std::ceil((float)actual_track_list.size() / (float)actual_Fc); /* Track step mush be a multiple of 2!!!*/ /* Make sure step should be at least 1 */ track_step = std::max(1, (int)track_step); @@ -1203,6 +1211,12 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, /* Ensure the number of tracks is similar to Fc */ //printf("Fc_out=%lu, scaled_Fc_out=%d, track_cnt=%d, actual_track_cnt=%lu/%lu\n", Fc, actual_Fc, track_cnt, actual_track_list.size(), chan_width); assert (actual_Fc <= track_cnt); + /* Give a warning if Fc is < track_cnt */ + if (actual_Fc < track_cnt) { + vpr_printf(TIO_MESSAGE_INFO, + "Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than OPINs!\n", + opin_node_id, track_cnt, actual_Fc); + } } return; From c62762ce59e7cb62db5bad573c3a602e52d7fd10 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2019 13:42:22 -0600 Subject: [PATCH 11/24] bug fixing in assign ipins to tracks using Fc_in --- .../device/rr_graph/tileable_rr_graph_gsb.cpp | 21 ++++++++----------- 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp index f1c497ca2..252d929b3 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp @@ -1064,17 +1064,14 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, /* Scale Fc */ int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */ - actual_Fc = std::max(2, actual_Fc); + actual_Fc = std::max(1, actual_Fc); /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in + * For uni-directional arch, all the tracks are in pair, we will divide by 2 to be normalized (Fc counts pairs) */ - size_t track_step = std::ceil((float)actual_track_list.size() / (float)actual_Fc); - /* Track step mush be a multiple of 2!!!*/ - if (0 != track_step % 2) { - track_step--; /* minus 1 to increase connectivity */ - } + size_t track_step = std::ceil((float)(actual_track_list.size() / 2) / (float)actual_Fc); /* Make sure step should be at least 2 */ - track_step = std::max(2, (int)track_step); + track_step = std::max(1, (int)track_step); /* Adapt offset to the range of actual_track_list */ size_t actual_offset = offset % actual_track_list.size(); /* rotate the track list by an offset */ @@ -1109,12 +1106,12 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, /* Ensure the number of tracks is similar to Fc */ //printf("Fc_in=%d, track_cnt=%d\n", actual_Fc, track_cnt); - assert (actual_Fc <= track_cnt); + assert (2 * actual_Fc <= track_cnt); /* Give a warning if Fc is < track_cnt */ - if (actual_Fc < track_cnt) { + if (2 * actual_Fc < track_cnt) { vpr_printf(TIO_MESSAGE_INFO, - "Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than IPINs!\n", - ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); + "IPIN Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than IPINs!\n", + ipin_node - rr_graph->rr_node, track_cnt, 2 * actual_Fc); } } @@ -1214,7 +1211,7 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, /* Give a warning if Fc is < track_cnt */ if (actual_Fc < track_cnt) { vpr_printf(TIO_MESSAGE_INFO, - "Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than OPINs!\n", + "OPIN Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than OPINs!\n", opin_node_id, track_cnt, actual_Fc); } } From 76fefdb8766f627ccbc23f5e566c7841e02c644b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2019 16:23:15 -0600 Subject: [PATCH 12/24] bug fixing in Fc_in and be serious in the performance of rr_graph --- .../device/rr_graph/tileable_rr_graph_gsb.cpp | 43 +++++++++---------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp index 252d929b3..aa6fcc2aa 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp @@ -1067,9 +1067,8 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, actual_Fc = std::max(1, actual_Fc); /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in - * For uni-directional arch, all the tracks are in pair, we will divide by 2 to be normalized (Fc counts pairs) - */ - size_t track_step = std::ceil((float)(actual_track_list.size() / 2) / (float)actual_Fc); + */ + size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); /* Make sure step should be at least 2 */ track_step = std::max(1, (int)track_step); /* Adapt offset to the range of actual_track_list */ @@ -1081,38 +1080,35 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, /* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step */ int track_cnt = 0; + /* Keep assigning until we meet the Fc requirement */ for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + 2 * track_step) { /* Update pin2track map */ size_t chan_side_index = chan_side_manager.to_size_t(); size_t ipin_index = ipin_node - rr_graph->rr_node; + /* itrack may exceed the size of actual_track_list, adapt it */ + size_t actual_itrack = itrack % actual_track_list.size(); /* track_index may exceed the chan_width(), adapt it */ - size_t track_index = actual_track_list[itrack] % chan_width; + size_t track_index = actual_track_list[actual_itrack] % chan_width; (*track2ipin_map)[chan_side_index][track_index].push_back(ipin_index); /* track_index may exceed the chan_width(), adapt it */ - track_index = (actual_track_list[itrack] + 1) % chan_width; + track_index = (actual_track_list[actual_itrack] + 1) % chan_width; (*track2ipin_map)[chan_side_index][track_index].push_back(ipin_index); track_cnt += 2; - /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. - * So I comment it. And we just make sure its track_cnt >= actual_Fc - if (actual_Fc == track_cnt) { - break; - } - */ } /* Ensure the number of tracks is similar to Fc */ - //printf("Fc_in=%d, track_cnt=%d\n", actual_Fc, track_cnt); - assert (2 * actual_Fc <= track_cnt); /* Give a warning if Fc is < track_cnt */ - if (2 * actual_Fc < track_cnt) { + /* + if (actual_Fc != track_cnt) { vpr_printf(TIO_MESSAGE_INFO, - "IPIN Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than IPINs!\n", - ipin_node - rr_graph->rr_node, track_cnt, 2 * actual_Fc); + "IPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", + ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); } + */ } return; @@ -1174,7 +1170,7 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in */ - size_t track_step = std::ceil((float)actual_track_list.size() / (float)actual_Fc); + size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); /* Track step mush be a multiple of 2!!!*/ /* Make sure step should be at least 1 */ track_step = std::max(1, (int)track_step); @@ -1189,10 +1185,13 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, /* Assign tracks */ int track_cnt = 0; + /* Keep assigning until we meet the Fc requirement */ for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + track_step) { /* Update pin2track map */ size_t opin_side_index = opin_side_manager.to_size_t(); - size_t track_index = actual_track_list[itrack]; + /* itrack may exceed the size of actual_track_list, adapt it */ + size_t actual_itrack = itrack % actual_track_list.size(); + size_t track_index = actual_track_list[actual_itrack]; size_t track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index) - rr_graph->rr_node; (*opin2track_map)[opin_side_index][opin_node_id].push_back(track_rr_node_index); /* update track counter */ @@ -1206,14 +1205,14 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, } /* Ensure the number of tracks is similar to Fc */ - //printf("Fc_out=%lu, scaled_Fc_out=%d, track_cnt=%d, actual_track_cnt=%lu/%lu\n", Fc, actual_Fc, track_cnt, actual_track_list.size(), chan_width); - assert (actual_Fc <= track_cnt); /* Give a warning if Fc is < track_cnt */ - if (actual_Fc < track_cnt) { + /* + if (actual_Fc != track_cnt) { vpr_printf(TIO_MESSAGE_INFO, - "OPIN Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than OPINs!\n", + "OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", opin_node_id, track_cnt, actual_Fc); } + */ } return; From ae05c553d55bbaa171531c6e2461fbbaf3b2ecee Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 8 Jul 2019 09:48:33 -0600 Subject: [PATCH 13/24] Top module done --- .../verilog/verilog_compact_netlist.c | 14 ++--- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 52 ++++++++++++------ .../SRC/fpga_x2p/verilog/verilog_pbtypes.h | 3 +- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 54 +++++++++++++++++-- .../SRC/fpga_x2p/verilog/verilog_routing.c | 4 +- .../verilog/verilog_top_netlist_utils.c | 5 +- .../verilog/verilog_top_netlist_utils.h | 3 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 24 ++++++++- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 6 ++- 9 files changed, 131 insertions(+), 34 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 57be783cf..4d8471798 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -361,7 +361,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "module %s ( \n", subckt_name); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } @@ -378,7 +378,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf /* I/O PAD */ dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, 0, phy_block_type->capacity * phy_block_type->pb_type->physical_mode_num_iopads - 1, - VERILOG_PORT_INOUT); + VERILOG_PORT_INOUT, is_explicit_mapping); /* Print configuration ports */ /* Reserved configuration ports */ @@ -406,7 +406,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, 0, temp_conf_bits_msb - 1, - VERILOG_PORT_INPUT, is_explicit_mapping); // Should be modified to be VERILOG_PORT_INPUT + VERILOG_PORT_INPUT, false); // Should be modified to be VERILOG_PORT_INPUT fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -436,9 +436,9 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf /* Print all the pins */ /* Special Care for I/O grid */ if (IO_TYPE == phy_block_type) { - dump_compact_verilog_io_grid_block_subckt_pins(fp, phy_block_type, border_side, iz); + dump_compact_verilog_io_grid_block_subckt_pins(fp, phy_block_type, border_side, iz, is_explicit_mapping); } else { - dump_verilog_grid_block_subckt_pins(fp, iz, phy_block_type); + dump_verilog_grid_block_subckt_pins(fp, iz, phy_block_type, is_explicit_mapping); } /* Print configuration ports */ @@ -450,7 +450,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "\n//---- IOPAD ----\n"); dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, temp_iopad_lsb, temp_iopad_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); /* Reserved configuration ports */ if (0 < temp_reserved_conf_bits_msb) { fprintf(fp, ",\n"); @@ -631,7 +631,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, iopad_verilog_model->grid_index_low[ix][iy], iopad_verilog_model->grid_index_high[ix][iy] - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); /* Print configuration ports */ /* Reserved configuration ports */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 80ed46195..a779ee550 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -370,8 +370,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, port_prefix, pb_type_port->name); } else { if ((NULL != cur_pb_type->spice_model) - && (TRUE == dump_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + && (TRUE == dump_explicit_port_map)) { fprintf(fp, ".%s(", pb_type_port->spice_model_port->lib_name); } @@ -385,8 +384,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, } fprintf(fp, "}"); if ((NULL != cur_pb_type->spice_model) - && (TRUE == dump_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + && (TRUE == dump_explicit_port_map)) { fprintf(fp, ")"); } } @@ -1733,7 +1731,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, */ fprintf(fp, "\n"); /* dump global ports */ - if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { + if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } /* Simplify the port prefix, make SPICE netlist readable */ @@ -1742,7 +1740,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, stamped_iopad_cnt, iopad_verilog_model->cnt - 1, - VERILOG_PORT_INOUT); + VERILOG_PORT_INOUT, is_explicit_mapping); /* Print Configuration ports */ /* sram_verilog_model->cnt should be updated because all the child pbs have been dumped * stamped_sram_cnt remains the old sram_verilog_model->cnt before all the child pbs are dumped @@ -1848,7 +1846,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, gio_inout_prefix, stamped_iopad_cnt, stamped_iopad_cnt + child_pb_num_iopads - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); /* update stamped outpad counter */ stamped_iopad_cnt += child_pb_num_iopads; /* Print configuration ports */ @@ -1889,7 +1887,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, /* Print interconnections, set is_idle as TRUE*/ dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, cur_pb_graph_node, mode_index, - is_explicit_mapping); + false); /* Check each pins of pb_graph_node */ /* Check and update stamped_sram_cnt */ /* Now we only dump one Verilog for each pb_type, and instance them when num_pb > 1 @@ -2279,9 +2277,11 @@ char* verilog_get_grid_phy_block_subckt_name(int x, int y, int z, /* Print the pins of grid subblocks */ void dump_verilog_grid_block_subckt_pins(FILE* fp, int z, - t_type_ptr type_descriptor) { + t_type_ptr type_descriptor, + bool is_explicit_mapping) { int iport, ipin, side, dump_pin_cnt; int grid_pin_index, pin_height, side_pin_index; + t_port* cur_port; t_pb_graph_node* top_pb_graph_node = NULL; /* Check the file handler*/ @@ -2313,8 +2313,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->input_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_ ", convert_side_index_to_string(side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } dump_pin_cnt++; side_pin_index++; } @@ -2338,8 +2345,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->output_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_ ", convert_side_index_to_string(side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } dump_pin_cnt++; side_pin_index++; } @@ -2363,8 +2377,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->clock_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_ ", convert_side_index_to_string(side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } dump_pin_cnt++; side_pin_index++; } @@ -2381,7 +2402,8 @@ void dump_verilog_io_grid_block_subckt_pins(FILE* fp, int x, int y, int z, - t_type_ptr type_descriptor) { + t_type_ptr type_descriptor, + bool is_explicit_mapping) { int iport, ipin, side, dump_pin_cnt; int grid_pin_index, pin_height, side_pin_index; t_pb_graph_node* top_pb_graph_node = NULL; @@ -2552,7 +2574,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "module %s ( \n", gen_verilog_one_grid_module_name(ix, iy)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } @@ -2568,7 +2590,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, iopad_verilog_model->grid_index_low[ix][iy], iopad_verilog_model->grid_index_high[ix][iy] - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, is_explicit_mapping); /* Print configuration ports */ /* Reserved configuration ports */ @@ -2631,9 +2653,9 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, /* Print all the pins */ /* Special Care for I/O grid */ if (IO_TYPE == grid[ix][iy].type) { - dump_verilog_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type); + dump_verilog_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type, is_explicit_mapping); } else { - dump_verilog_grid_block_subckt_pins(fp, iz, grid[ix][iy].type); + dump_verilog_grid_block_subckt_pins(fp, iz, grid[ix][iy].type, is_explicit_mapping); } /* Print configuration ports */ temp_reserved_conf_bits_msb = grid[ix][iy].type->pb_type->physical_mode_num_reserved_conf_bits; @@ -2645,7 +2667,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, temp_iopad_lsb, temp_iopad_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); assert(!(0 > temp_conf_bits_msb - temp_conf_bits_lsb)); /* Reserved configuration ports */ if (0 < temp_reserved_conf_bits_msb) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h index 3ad43e94c..25ffcd85d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h @@ -127,7 +127,8 @@ char* get_grid_block_subckt_name(int x, void dump_verilog_grid_block_subckt_pins(FILE* fp, int z, - t_type_ptr type_descriptor); + t_type_ptr type_descriptor, + bool is_explicit_mapping); void dump_verilog_io_grid_block_subckt_pins(FILE* fp, int x, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index a735d36fb..3354a8938 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -610,7 +610,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, /* Connect inputs*/ /* Connect outputs*/ fprintf(fp, "//----- Input and output ports -----\n"); - dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, verilog_model->dump_explicit_port_map); + dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, "\n//----- SRAM ports -----\n"); /* check */ @@ -622,41 +622,89 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, case SPICE_SRAM_STANDALONE: break; case SPICE_SRAM_SCAN_CHAIN: + if (true == is_explicit_mapping) { + fprintf(fp, ".sram_out( "); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".sram_outb( "); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } if (0 < num_mode_sram) { fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".mode_out( "); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".mode_outb( "); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, 1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } } break; case SPICE_SRAM_MEMORY_BANK: + if (true == is_explicit_mapping) { + fprintf(fp, ".sram_out( "); + } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".sram_outb( "); + } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } if (0 < num_mode_sram) { fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".mode_out( "); + } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, - 0, VERILOG_PORT_CONKT); + 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".mode_outb( "); + } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, - 1, VERILOG_PORT_CONKT); + 1, VERILOG_PORT_CONKT); + } + if (true == is_explicit_mapping) { + fprintf(fp, ")"); } break; default: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 4ff427dcf..eced18e87 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -1900,7 +1900,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side, seg_id, TRUE, - is_explicit_mapping); + false); /* Put down configuration port */ /* output of each configuration bit */ @@ -1926,7 +1926,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_num_sram, esti_sram_cnt - 1, - VERILOG_PORT_INPUT, is_explicit_mapping); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 830cbf02c..3ae703e30 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -405,7 +405,7 @@ void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, iopad_verilog_model->grid_index_low[ix][iy], iopad_verilog_model->grid_index_high[ix][iy] - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); /* Print configuration ports */ /* Reserved configuration ports */ @@ -1433,7 +1433,8 @@ char* compact_verilog_get_grid_phy_block_subckt_name(t_type_ptr grid_type_descri void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp, t_type_ptr grid_type_descriptor, int border_side, - int z) { + int z, + bool is_explicit_mapping) { int iport, ipin, dump_pin_cnt; int grid_pin_index, pin_height, side_pin_index; t_pb_graph_node* top_pb_graph_node = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h index 91b185e08..c57d7694f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h @@ -52,6 +52,7 @@ char* compact_verilog_get_grid_phy_block_subckt_name(t_type_ptr grid_type_descri void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp, t_type_ptr grid_type_descriptor, int border_side, - int z) ; + int z, + bool is_explicit_mapping) ; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index c3287e7a7..90a010607 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2717,7 +2717,8 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, */ void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, char* general_port_prefix, int lsb, int msb, - enum e_dump_verilog_port_type dump_port_type) { + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping) { char* port_full_name = NULL; /* Check the file handler*/ @@ -3238,18 +3239,39 @@ void dump_verilog_mem_sram_submodule(FILE* fp, break; } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[0].prefix); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, -1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", \n"); // /* Output of Scan-chain DFF, should be connected to the output of its successor */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[1].prefix); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", \n"); // + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[2].prefix); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, 1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 8930d8068..a66fd48f2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -100,7 +100,8 @@ void dump_verilog_mux_sram_one_local_outport(FILE* fp, t_spice_model* cur_mux_spice_model, int mux_size, int sram_lsb, int sram_msb, int port_type_index, - enum e_dump_verilog_port_type dump_port_type); + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping); void dump_verilog_sram_one_local_outport(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, @@ -202,7 +203,8 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, char* general_port_prefix, int lsb, int msb, - enum e_dump_verilog_port_type dump_port_type); + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping); void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int lsb, int msb); From df0a3d23a33cfefa1857cd35708e1be727cce8e9 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 8 Jul 2019 10:23:14 -0600 Subject: [PATCH 14/24] Correction top module --- .../verilog/verilog_compact_netlist.c | 47 +++++++++++++++---- .../verilog/verilog_top_netlist_utils.c | 2 +- vpr7_x2p/vpr/regression_verilog.sh | 2 +- 3 files changed, 41 insertions(+), 10 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 4d8471798..7e1a0cd77 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -1075,16 +1075,28 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { switch (rr_chan.get_node(itrack)->direction) { case INC_DIRECTION: - fprintf(fp, "%s, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".in%d (",itrack); + } + fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, OUT_PORT)); - fprintf(fp, "\n"); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; case DEC_DIRECTION: - fprintf(fp, "%s, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".out%d (",itrack); + } + fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, IN_PORT)); - fprintf(fp, "\n"); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%u]!\n", @@ -1103,16 +1115,28 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { switch (rr_chan.get_node(itrack)->direction) { case INC_DIRECTION: - fprintf(fp, "%s, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".out%d (",itrack); + } + fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, IN_PORT)); - fprintf(fp, "\n"); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; case DEC_DIRECTION: - fprintf(fp, "%s, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".in%d (",itrack); + } + fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, OUT_PORT)); - fprintf(fp, "\n"); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%u]!\n", @@ -1125,9 +1149,16 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, /* output at middle point */ for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + if (true == is_explicit_mapping) { + fprintf(fp, ".mid_out%d (", + itrack); + } fprintf(fp, "%s_%d__%d__midout_%lu_ ", convert_chan_type_to_string(rr_chan.get_type()), x, y, itrack); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } if (itrack < rr_chan.get_chan_width() - 1) { fprintf(fp, ","); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 3ae703e30..f0edb1578 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -337,7 +337,7 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "\n"); dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_INPUT, - is_explicit_mapping); + false); fprintf(fp, ");\n"); diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index e19875026..8007363cf 100644 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd - # Run VPR -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis #--fpga_x2p_compact_routing_hierarchy +./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path From 5d5e09fcdb7baf7e9c3f7c8168ffaeecc45db7cb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2019 17:12:36 -0600 Subject: [PATCH 15/24] minor fix in trying to accelerate the unique routing functions --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index 45c67fa33..dc76ff55d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -1338,10 +1338,10 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, /* For each switch block, determine the size of array */ for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) { for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) { - RRGSB rr_gsb = build_rr_gsb(sb_range, ix, iy, - LL_num_rr_nodes, LL_rr_node, - LL_rr_node_indices, - num_segments, LL_rr_indexed_data); + const RRGSB& rr_gsb = build_rr_gsb(sb_range, ix, iy, + LL_num_rr_nodes, LL_rr_node, + LL_rr_node_indices, + num_segments, LL_rr_indexed_data); /* sort drive_rr_nodes */ sort_rr_gsb_drive_rr_nodes(rr_gsb); /* Add to device_rr_gsb */ From 25f5bc7792c8f0772c0f3cd11884c94fc2fff1e2 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Tue, 9 Jul 2019 08:34:01 -0600 Subject: [PATCH 16/24] Latest version, not stable yet but close --- vpr7_x2p/libarchfpga/tags | 2507 +++++++++-------- .../verilog/verilog_compact_netlist.c | 29 +- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 116 +- .../SRC/fpga_x2p/verilog/verilog_pbtypes.h | 10 +- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 28 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 2 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 2 +- .../verilog/verilog_top_netlist_utils.c | 25 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 65 +- vpr7_x2p/vpr/regression_verilog.sh | 2 + 10 files changed, 1514 insertions(+), 1272 deletions(-) mode change 100644 => 100755 vpr7_x2p/vpr/regression_verilog.sh diff --git a/vpr7_x2p/libarchfpga/tags b/vpr7_x2p/libarchfpga/tags index cefe670d6..d71681de4 100644 --- a/vpr7_x2p/libarchfpga/tags +++ b/vpr7_x2p/libarchfpga/tags @@ -4,1186 +4,1327 @@ !_TAG_PROGRAM_NAME Exuberant Ctags // !_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ !_TAG_PROGRAM_VERSION 5.8 // -ABSOLUTE include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type -ARCH_TYPES_H include/arch_types.h 9;" d -Aspect include/physical_types.h /^ float Aspect;$/;" m struct:s_clb_grid -BI_DIRECTIONAL include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality -BOTTOM include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side -BOUNDARY include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type -BUFSIZE include/util.h 23;" d -C include/arch_types_mrfpga.h /^ float C; $/;" m struct:s_memristor_inf -C include/arch_types_mrfpga.h /^ float C;$/;" m struct:s_buffer_inf -C include/physical_types.h /^ float C;$/;" m union:s_port_power::__anon3 -CAD_TYPES_H include/cad_types.h 5;" d -CHECK_RAND util.c 734;" d file: -CHUNK_SIZE util.c 208;" d file: -COL_REL include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type -COL_REPEAT include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type -COMPLETE_INTERC include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect -CONV include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -C_internal include/physical_types.h /^ float C_internal; \/*Internal capacitance of the pb *\/$/;" m struct:s_pb_type_power -C_ipin_cblock include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_arch -C_ipin_cblock include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_timing_inf -C_wire include/physical_types.h /^ float C_wire; \/* Wire capacitance (per meter) *\/$/;" m struct:s_clock_network -C_wire include/physical_types.h /^ float C_wire;$/;" m struct:s_pb_graph_pin_power -C_wire_local include/physical_types.h /^ float C_wire_local; \/* Capacitance of local interconnect (per meter) *\/$/;" m struct:s_power_arch -Chans include/physical_types.h /^ t_chan_width_dist Chans;$/;" m struct:s_arch -CheckElement read_xml_util.c /^void CheckElement(INP ezxml_t Node, INP const char *Name) {$/;" f -Cin include/physical_types.h /^ float Cin;$/;" m struct:s_switch_inf -Cmetal include/physical_types.h /^ float Cmetal;$/;" m struct:s_segment_inf -CountChildren read_xml_util.c /^extern int CountChildren(INP ezxml_t Node, INP const char *Name,$/;" f -CountTokens ReadLine.c /^int CountTokens(INP char **Tokens) {$/;" f -CountTokensInString read_xml_util.c /^extern void CountTokensInString(INP const char *Str, OUTP int *Num,$/;" f -Cout include/physical_types.h /^ float Cout;$/;" m struct:s_switch_inf -CreateModelLibrary read_xml_arch_file.c /^static void CreateModelLibrary(OUTP struct s_arch *arch) {$/;" f file: -Cseg_global include/arch_types_mrfpga.h /^ float Cseg_global;$/;" m struct:s_arch_mrfpga -DELTA include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat -DIRECT_INTERC include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect -DRIVER include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type -Directs include/physical_types.h /^ t_direct_inf *Directs;$/;" m struct:s_arch -EMPTY_TYPE read_xml_arch_file.c /^static t_type_ptr EMPTY_TYPE = NULL;$/;" v file: -EMPTY_TYPE_INDEX include/read_xml_arch_file.h 15;" d -ERRTAG include/util.h 26;" d -ERR_PORT include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -EZXML_BUFSIZE include/ezxml.h 37;" d -EZXML_DUP include/ezxml.h 40;" d -EZXML_ERRL include/ezxml.h 41;" d -EZXML_NAMEM include/ezxml.h 38;" d -EZXML_NIL ezxml.c /^char *EZXML_NIL[] = { NULL }; \/* empty, null terminated array of strings *\/$/;" v -EZXML_NOMMAP ezxml.c 26;" d file: -EZXML_TXTM include/ezxml.h 39;" d -EZXML_WS ezxml.c 64;" d file: -E_ANNOT_PIN_TO_PIN_CAPACITANCE include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE,$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_CAPACITANCE_C include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE_C = 0$/;" e enum:e_pin_to_pin_capacitance_annotations -E_ANNOT_PIN_TO_PIN_CONSTANT include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format -E_ANNOT_PIN_TO_PIN_DELAY include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY = 0,$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_MAX include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MAX,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_MIN include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MIN = 0,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_THOLD include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_THOLD$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_TSETUP include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_TSETUP,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_MATRIX include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format -E_ANNOT_PIN_TO_PIN_MODE_SELECT include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME = 0$/;" e enum:e_pin_to_pin_mode_select_annotations -E_ANNOT_PIN_TO_PIN_PACK_PATTERN include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN,$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME = 0$/;" e enum:e_pin_to_pin_pack_pattern_annotations -E_CUSTOM_PIN_DISTR include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr -E_SPREAD_PIN_DISTR include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr -EchoArch read_xml_arch_file.c /^void EchoArch(INP const char *EchoFile, INP const t_type_descriptor * Types,$/;" f -FALSE include/util.h /^ FALSE, TRUE$/;" e enum:__anon4 -FC_ABS read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: -FC_FRAC read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: -FC_FULL read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: -FF_size include/physical_types.h /^ float FF_size;$/;" m struct:s_power_arch -FILL include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type -FILL_TYPE read_xml_arch_file.c /^static t_type_ptr FILL_TYPE = NULL;$/;" v file: -FRACTIONAL include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type -FRAGMENT_THRESHOLD util.c 209;" d file: -FULL include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type -Fc include/physical_types.h /^ float *Fc; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -Fc_type read_xml_arch_file.c /^enum Fc_type {$/;" g file: -FindElement read_xml_util.c /^ezxml_t FindElement(INP ezxml_t Parent, INP const char *Name,$/;" f -FindFirstElement read_xml_util.c /^ezxml_t FindFirstElement(INP ezxml_t Parent, INP const char *Name,$/;" f -FindProperty read_xml_util.c /^FindProperty(INP ezxml_t Parent, INP const char *Name, INP boolean Required) {$/;" f -FreeNode read_xml_util.c /^void FreeNode(INOUTP ezxml_t Node) {$/;" f -FreeSpice read_xml_spice_util.c /^void FreeSpice(t_spice* spice) {$/;" f -FreeSpiceMeasParams read_xml_spice_util.c /^void FreeSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f -FreeSpiceModel read_xml_spice_util.c /^void FreeSpiceModel(t_spice_model* spice_model) {$/;" f -FreeSpiceModelBuffer read_xml_spice_util.c /^void FreeSpiceModelBuffer(t_spice_model_buffer* spice_model_buffer) {$/;" f -FreeSpiceModelNetlist read_xml_spice_util.c /^void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist) {$/;" f -FreeSpiceModelPassGateLogic read_xml_spice_util.c /^void FreeSpiceModelPassGateLogic(t_spice_model_pass_gate_logic* spice_model_pass_gate_logic) {$/;" f -FreeSpiceModelPort read_xml_spice_util.c /^void FreeSpiceModelPort(t_spice_model_port* spice_model_port) {$/;" f -FreeSpiceModelWireParam read_xml_spice_util.c /^void FreeSpiceModelWireParam(t_spice_model_wire_param* spice_model_wire_param) {$/;" f -FreeSpiceMonteCarloParams read_xml_spice_util.c /^void FreeSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f -FreeSpiceMuxArch read_xml_spice_util.c /^void FreeSpiceMuxArch(t_spice_mux_arch* spice_mux_arch) {$/;" f -FreeSpiceParams read_xml_spice_util.c /^void FreeSpiceParams(t_spice_params* params) {$/;" f -FreeSpiceStimulateParams read_xml_spice_util.c /^void FreeSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f -FreeSpiceVariationParams read_xml_spice_util.c /^void FreeSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f -FreeSramInf read_xml_spice_util.c /^void FreeSramInf(t_sram_inf* sram_inf) {$/;" f -FreeSramInfOrgz read_xml_spice_util.c /^void FreeSramInfOrgz(t_sram_inf_orgz* sram_inf_orgz) {$/;" f -FreeTokens ReadLine.c /^void FreeTokens(INOUTP char ***TokensPtr) {$/;" f -Fs include/physical_types.h /^ int Fs;$/;" m struct:s_arch -GAUSSIAN include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat -GetBooleanProperty read_xml_util.c /^extern boolean GetBooleanProperty(INP ezxml_t Parent, INP char *Name,$/;" f -GetFloatProperty read_xml_util.c /^extern float GetFloatProperty(INP ezxml_t Parent, INP char *Name,$/;" f -GetIntProperty read_xml_util.c /^extern int GetIntProperty(INP ezxml_t Parent, INP char *Name,$/;" f -GetNodeTokens read_xml_util.c /^GetNodeTokens(INP ezxml_t Node) {$/;" f -H include/physical_types.h /^ int H;$/;" m struct:s_clb_grid -IA util.c 731;" d file: -IC util.c 732;" d file: -IM util.c 733;" d file: -INOUTP include/util.h 21;" d -INOUT_PORT include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -INP include/util.h 19;" d -IN_PORT include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -IO_TYPE read_xml_arch_file.c /^static t_type_ptr IO_TYPE = NULL;$/;" v file: -IO_TYPE_INDEX include/read_xml_arch_file.h 16;" d -InitSpice read_xml_spice_util.c /^void InitSpice(t_spice* spice) {$/;" f -InitSpiceMeasParams read_xml_spice_util.c /^void InitSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f -InitSpiceMonteCarloParams read_xml_spice_util.c /^void InitSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f -InitSpiceParams read_xml_spice_util.c /^void InitSpiceParams(t_spice_params* params) {$/;" f -InitSpiceStimulateParams read_xml_spice_util.c /^void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f -InitSpiceVariationParams read_xml_spice_util.c /^void InitSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f -IsAuto include/physical_types.h /^ boolean IsAuto;$/;" m struct:s_clb_grid -IsWhitespace read_xml_util.c /^boolean IsWhitespace(char c) {$/;" f -LATCH_CLASS include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class -LEFT include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side -LINKEDLIST_H fpga_spice_include/linkedlist.h 2;" d -LOGIC_TYPES_H include/logic_types.h 10;" d -LUT_CLASS include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class -LUT_transistor_size include/physical_types.h /^ float LUT_transistor_size;$/;" m struct:s_power_arch -LookaheadNodeTokens read_xml_util.c /^LookaheadNodeTokens(INP ezxml_t Node) {$/;" f -MAX_CHANNEL_WIDTH include/arch_types.h 25;" d -MEMORY_CLASS include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class -MONO include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -MUX_INTERC include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect -NEM include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -NUM_MODELS_IN_LIBRARY include/read_xml_arch_file.h 14;" d -OPEN include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type -OUTP include/util.h 20;" d -OUT_PORT include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -PB_PIN_CLOCK include/physical_types.h /^ PB_PIN_CLOCK$/;" e enum:e_pb_graph_pin_type -PB_PIN_INPAD include/physical_types.h /^ PB_PIN_INPAD,$/;" e enum:e_pb_graph_pin_type -PB_PIN_NORMAL include/physical_types.h /^ PB_PIN_NORMAL = 0,$/;" e enum:e_pb_graph_pin_type -PB_PIN_OUTPAD include/physical_types.h /^ PB_PIN_OUTPAD,$/;" e enum:e_pb_graph_pin_type -PB_PIN_SEQUENTIAL include/physical_types.h /^ PB_PIN_SEQUENTIAL,$/;" e enum:e_pb_graph_pin_type -PB_PIN_TERMINAL include/physical_types.h /^ PB_PIN_TERMINAL,$/;" e enum:e_pb_graph_pin_type -PCRAM_Pierre include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -PCRAM_Xie include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -PHYSICAL_TYPES_H include/physical_types.h 27;" d -PORTS include/logic_types.h /^enum PORTS {$/;" g -POWER_BUFFER_TYPE_ABSOLUTE_SIZE include/physical_types.h /^ POWER_BUFFER_TYPE_ABSOLUTE_SIZE$/;" e enum:__anon2 -POWER_BUFFER_TYPE_AUTO include/physical_types.h /^ POWER_BUFFER_TYPE_AUTO,$/;" e enum:__anon2 -POWER_BUFFER_TYPE_NONE include/physical_types.h /^ POWER_BUFFER_TYPE_NONE,$/;" e enum:__anon2 -POWER_BUFFER_TYPE_UNDEFINED include/physical_types.h /^ POWER_BUFFER_TYPE_UNDEFINED = 0,$/;" e enum:__anon2 -POWER_METHOD_ABSOLUTE include/physical_types.h /^ POWER_METHOD_ABSOLUTE \/* Dynamic: Aboslute, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_AUTO_SIZES include/physical_types.h /^ POWER_METHOD_AUTO_SIZES, \/* Transistor-level, auto-sized buffers\/wires *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_C_INTERNAL include/physical_types.h /^ POWER_METHOD_C_INTERNAL, \/* Dynamic: Equiv. Internal capacitance, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_IGNORE include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_SPECIFY_SIZES include/physical_types.h /^ POWER_METHOD_SPECIFY_SIZES, \/* Transistor-level, user-specified buffers\/wires *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_SUM_OF_CHILDREN include/physical_types.h /^ POWER_METHOD_SUM_OF_CHILDREN, \/* Ignore power of this PB, but consider children *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_TOGGLE_PINS include/physical_types.h /^ POWER_METHOD_TOGGLE_PINS, \/* Dynamic: Energy per pin toggle, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_UNDEFINED include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ -POWER_WIRE_TYPE_ABSOLUTE_LENGTH include/physical_types.h /^ POWER_WIRE_TYPE_ABSOLUTE_LENGTH,$/;" e enum:__anon1 -POWER_WIRE_TYPE_AUTO include/physical_types.h /^ POWER_WIRE_TYPE_AUTO$/;" e enum:__anon1 -POWER_WIRE_TYPE_C include/physical_types.h /^ POWER_WIRE_TYPE_C,$/;" e enum:__anon1 -POWER_WIRE_TYPE_IGNORED include/physical_types.h /^ POWER_WIRE_TYPE_IGNORED,$/;" e enum:__anon1 -POWER_WIRE_TYPE_RELATIVE_LENGTH include/physical_types.h /^ POWER_WIRE_TYPE_RELATIVE_LENGTH,$/;" e enum:__anon1 -POWER_WIRE_TYPE_UNDEFINED include/physical_types.h /^ POWER_WIRE_TYPE_UNDEFINED = 0,$/;" e enum:__anon1 -PULSE include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat -PrintPb_types_rec read_xml_arch_file.c /^static void PrintPb_types_rec(INP FILE * Echo, INP const t_pb_type * pb_type,$/;" f file: -ProcessCB_SB read_xml_arch_file.c /^static void ProcessCB_SB(INOUTP ezxml_t Node, INOUTP boolean * list,$/;" f file: -ProcessChanWidthDistr read_xml_arch_file.c /^static void ProcessChanWidthDistr(INOUTP ezxml_t Node,$/;" f file: -ProcessChanWidthDistrDir read_xml_arch_file.c /^static void ProcessChanWidthDistrDir(INOUTP ezxml_t Node, OUTP t_chan * chan) {$/;" f file: -ProcessClocks read_xml_arch_file.c /^static void ProcessClocks(ezxml_t Parent, t_clock_arch * clocks) {$/;" f file: -ProcessComplexBlockProps read_xml_arch_file.c /^static void ProcessComplexBlockProps(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: -ProcessComplexBlocks read_xml_arch_file.c /^static void ProcessComplexBlocks(INOUTP ezxml_t Node,$/;" f file: -ProcessDevice read_xml_arch_file.c /^static void ProcessDevice(INOUTP ezxml_t Node, OUTP struct s_arch *arch,$/;" f file: -ProcessDirects read_xml_arch_file.c /^static void ProcessDirects(INOUTP ezxml_t Parent, OUTP t_direct_inf **Directs,$/;" f file: -ProcessInterconnect read_xml_arch_file.c /^static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {$/;" f file: -ProcessLayout read_xml_arch_file.c /^static void ProcessLayout(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: -ProcessLutClass read_xml_arch_file.c /^void ProcessLutClass(INOUTP t_pb_type *lut_pb_type) {$/;" f -ProcessMemoryClass read_xml_arch_file.c /^static void ProcessMemoryClass(INOUTP t_pb_type *mem_pb_type) {$/;" f file: -ProcessMode read_xml_arch_file.c /^static void ProcessMode(INOUTP ezxml_t Parent, t_mode * mode,$/;" f file: -ProcessModels read_xml_arch_file.c /^static void ProcessModels(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: -ProcessMrFPGATiming read_xml_mrfpga.c /^void ProcessMrFPGATiming(INOUTP ezxml_t Cur, $/;" f -ProcessPb_Type read_xml_arch_file.c /^static void ProcessPb_Type(INOUTP ezxml_t Parent, t_pb_type * pb_type,$/;" f file: -ProcessPb_TypePort read_xml_arch_file.c /^static void ProcessPb_TypePort(INOUTP ezxml_t Parent, t_port * port,$/;" f file: -ProcessPb_TypePort_Power read_xml_arch_file.c /^static void ProcessPb_TypePort_Power(ezxml_t Parent, t_port * port,$/;" f file: -ProcessPb_TypePower read_xml_arch_file.c /^static void ProcessPb_TypePower(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: -ProcessPb_TypePowerEstMethod read_xml_arch_file.c /^static void ProcessPb_TypePowerEstMethod(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: -ProcessPb_TypePowerPinToggle read_xml_arch_file.c /^static void ProcessPb_TypePowerPinToggle(ezxml_t parent, t_pb_type * pb_type) {$/;" f file: -ProcessPinToPinAnnotations read_xml_arch_file.c /^static void ProcessPinToPinAnnotations(ezxml_t Parent,$/;" f file: -ProcessPower read_xml_arch_file.c /^static void ProcessPower( INOUTP ezxml_t parent,$/;" f file: -ProcessSegments read_xml_arch_file.c /^static void ProcessSegments(INOUTP ezxml_t Parent,$/;" f file: -ProcessSpiceMCVariationParams read_xml_spice.c /^static void ProcessSpiceMCVariationParams(ezxml_t Parent,$/;" f file: -ProcessSpiceMeasParams read_xml_spice.c /^static void ProcessSpiceMeasParams(ezxml_t Parent,$/;" f file: -ProcessSpiceModel read_xml_spice.c /^static void ProcessSpiceModel(ezxml_t Parent,$/;" f file: -ProcessSpiceModelBuffer read_xml_spice.c /^static void ProcessSpiceModelBuffer(ezxml_t Node,$/;" f file: -ProcessSpiceModelPassGateLogic read_xml_spice.c /^static void ProcessSpiceModelPassGateLogic(ezxml_t Node,$/;" f file: -ProcessSpiceModelPort read_xml_spice.c /^static void ProcessSpiceModelPort(ezxml_t Node,$/;" f file: -ProcessSpiceModelWireParam read_xml_spice.c /^static void ProcessSpiceModelWireParam(ezxml_t Parent,$/;" f file: -ProcessSpiceMonteCarloParams read_xml_spice.c /^static void ProcessSpiceMonteCarloParams(ezxml_t Parent, $/;" f file: -ProcessSpiceParams read_xml_spice.c /^static void ProcessSpiceParams(ezxml_t Parent,$/;" f file: -ProcessSpiceSRAM read_xml_spice.c /^void ProcessSpiceSRAM(INOUTP ezxml_t Node, OUTP struct s_arch* arch) {$/;" f -ProcessSpiceSRAMOrganization read_xml_spice.c /^void ProcessSpiceSRAMOrganization(INOUTP ezxml_t Node, $/;" f file: -ProcessSpiceSettings read_xml_spice.c /^void ProcessSpiceSettings(ezxml_t Parent,$/;" f -ProcessSpiceStimulateParams read_xml_spice.c /^static void ProcessSpiceStimulateParams(ezxml_t Parent,$/;" f file: -ProcessSpiceStimulateParamsRiseFall read_xml_spice.c /^static void ProcessSpiceStimulateParamsRiseFall(ezxml_t Parent,$/;" f file: -ProcessSpiceTechLibTransistors read_xml_spice.c /^static void ProcessSpiceTechLibTransistors(ezxml_t Parent,$/;" f file: -ProcessSpiceTransistorType read_xml_spice.c /^static void ProcessSpiceTransistorType(ezxml_t Parent,$/;" f file: -ProcessSwitchSegmentPatterns read_xml_arch_file.c /^static void ProcessSwitchSegmentPatterns(INOUTP ezxml_t Parent,$/;" f file: -ProcessSwitches read_xml_arch_file.c /^static void ProcessSwitches(INOUTP ezxml_t Parent,$/;" f file: -ProcessTechComp read_xml_mrfpga.c /^ProcessTechComp(INOUTP ezxml_t Node,$/;" f -ProcessTechHack read_xml_mrfpga.c /^ProcessTechHack(INOUTP ezxml_t Node,$/;" f -ProcessTechnology read_xml_mrfpga.c /^ProcessTechnology(INOUTP ezxml_t Node,$/;" f -ProcessWireBuffer read_xml_mrfpga.c /^ProcessWireBuffer(INOUTP ezxml_t Node,$/;" f -Process_Fc read_xml_arch_file.c /^static void Process_Fc(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: -ProcessmrFPGA read_xml_mrfpga.c /^ProcessmrFPGA(INOUTP ezxml_t Node,$/;" f -R include/arch_types_mrfpga.h /^ float R; $/;" m struct:s_memristor_inf -R include/arch_types_mrfpga.h /^ float R;$/;" m struct:s_buffer_inf -R include/physical_types.h /^ float R;$/;" m struct:s_switch_inf -READLINE_H include/ReadLine.h 2;" d -READ_XML_ARCH_FILE_H include/read_xml_arch_file.h 2;" d -READ_XML_UTIL_H include/read_xml_util.h 2;" d -RECEIVER include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type -RIGHT include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side -R_minW_nmos include/physical_types.h /^ float R_minW_nmos;$/;" m struct:s_arch -R_minW_pmos include/physical_types.h /^ float R_minW_pmos;$/;" m struct:s_arch -R_opin_cblock include/arch_types_mrfpga.h /^ float R_opin_cblock;$/;" m struct:s_arch_mrfpga -R_opin_cblock include/physical_types.h /^ float R_opin_cblock;$/;" m struct:s_timing_inf -ReadLineTokens ReadLine.c /^ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum) {$/;" f -Rmetal include/physical_types.h /^ float Rmetal;$/;" m struct:s_segment_inf -Rseg_global include/arch_types_mrfpga.h /^ float Rseg_global;$/;" m struct:s_arch_mrfpga -SBType include/physical_types.h /^ enum e_switch_block_type SBType;$/;" m struct:s_arch typeref:enum:s_arch::e_switch_block_type -SDCFile include/physical_types.h /^ char * SDCFile; \/* only here for convenience of passing to path_delay.c *\/$/;" m struct:s_timing_inf -SPICE_ABS fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type -SPICE_FRAC fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type -SPICE_LIB_ACADEMIA fpga_spice_include/spice_types.h /^ SPICE_LIB_INDUSTRY,SPICE_LIB_ACADEMIA$/;" e enum:e_spice_tech_lib_type -SPICE_LIB_INDUSTRY fpga_spice_include/spice_types.h /^ SPICE_LIB_INDUSTRY,SPICE_LIB_ACADEMIA$/;" e enum:e_spice_tech_lib_type -SPICE_MODEL_BUF_BUF fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_BUF$/;" e enum:e_spice_model_buffer_type -SPICE_MODEL_BUF_INV fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_INV, $/;" e enum:e_spice_model_buffer_type -SPICE_MODEL_CHAN_WIRE fpga_spice_include/spice_types.h /^ SPICE_MODEL_CHAN_WIRE, $/;" e enum:e_spice_model_type -SPICE_MODEL_DESIGN_CMOS fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_CMOS, $/;" e enum:e_spice_model_design_tech -SPICE_MODEL_DESIGN_RRAM fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_RRAM$/;" e enum:e_spice_model_design_tech -SPICE_MODEL_FF fpga_spice_include/spice_types.h /^ SPICE_MODEL_FF, $/;" e enum:e_spice_model_type -SPICE_MODEL_GND fpga_spice_include/spice_types.h /^ SPICE_MODEL_GND, $/;" e enum:e_spice_model_type -SPICE_MODEL_HARDLOGIC fpga_spice_include/spice_types.h /^ SPICE_MODEL_HARDLOGIC,$/;" e enum:e_spice_model_type -SPICE_MODEL_INVBUF fpga_spice_include/spice_types.h /^ SPICE_MODEL_INVBUF, $/;" e enum:e_spice_model_type -SPICE_MODEL_IOPAD fpga_spice_include/spice_types.h /^ SPICE_MODEL_IOPAD, $/;" e enum:e_spice_model_type -SPICE_MODEL_LUT fpga_spice_include/spice_types.h /^ SPICE_MODEL_LUT, $/;" e enum:e_spice_model_type -SPICE_MODEL_MUX fpga_spice_include/spice_types.h /^ SPICE_MODEL_MUX, $/;" e enum:e_spice_model_type -SPICE_MODEL_PASSGATE fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASSGATE $/;" e enum:e_spice_model_type -SPICE_MODEL_PASS_GATE_TRANSISTOR fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSMISSION, SPICE_MODEL_PASS_GATE_TRANSISTOR$/;" e enum:e_spice_model_pass_gate_logic_type -SPICE_MODEL_PASS_GATE_TRANSMISSION fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSMISSION, SPICE_MODEL_PASS_GATE_TRANSISTOR$/;" e enum:e_spice_model_pass_gate_logic_type -SPICE_MODEL_PORT_BL fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BL,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_BLB fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BLB,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_CLOCK fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_CLOCK, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_INOUT fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INOUT, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_INPUT fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INPUT, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_OUTPUT fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_OUTPUT, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_SRAM fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_SRAM,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_WL fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WL,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_WLB fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WLB$/;" e enum:e_spice_model_port_type -SPICE_MODEL_SCFF fpga_spice_include/spice_types.h /^ SPICE_MODEL_SCFF,$/;" e enum:e_spice_model_type -SPICE_MODEL_SRAM fpga_spice_include/spice_types.h /^ SPICE_MODEL_SRAM, $/;" e enum:e_spice_model_type -SPICE_MODEL_STRUCTURE_CROSSBAR fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_CROSSBAR $/;" e enum:e_spice_model_structure -SPICE_MODEL_STRUCTURE_MULTILEVEL fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_MULTILEVEL, $/;" e enum:e_spice_model_structure -SPICE_MODEL_STRUCTURE_ONELEVEL fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_ONELEVEL, $/;" e enum:e_spice_model_structure -SPICE_MODEL_STRUCTURE_TREE fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_TREE, $/;" e enum:e_spice_model_structure -SPICE_MODEL_VDD fpga_spice_include/spice_types.h /^ SPICE_MODEL_VDD, $/;" e enum:e_spice_model_type -SPICE_MODEL_WIRE fpga_spice_include/spice_types.h /^ SPICE_MODEL_WIRE, $/;" e enum:e_spice_model_type -SPICE_SRAM_MEMORY_BANK fpga_spice_include/spice_types.h /^ SPICE_SRAM_MEMORY_BANK$/;" e enum:e_sram_orgz -SPICE_SRAM_SCAN_CHAIN fpga_spice_include/spice_types.h /^ SPICE_SRAM_SCAN_CHAIN,$/;" e enum:e_sram_orgz -SPICE_SRAM_STANDALONE fpga_spice_include/spice_types.h /^ SPICE_SRAM_STANDALONE,$/;" e enum:e_sram_orgz -SPICE_TRANS_IO_NMOS fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type -SPICE_TRANS_IO_PMOS fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type -SPICE_TRANS_NMOS fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type -SPICE_TRANS_PMOS fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type -STTRAM include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -SUBSET include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type -SWSEG_UNBUF_CB include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type -SWSEG_UNBUF_SB include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type -Segments include/physical_types.h /^ t_segment_inf * Segments;$/;" m struct:s_arch -SetupEmptyType read_xml_arch_file.c /^static void SetupEmptyType(void) {$/;" f file: -SetupGridLocations read_xml_arch_file.c /^static void SetupGridLocations(ezxml_t Locations, t_type_descriptor * Type) {$/;" f file: -SetupPinEquivalenceAutoDetect read_xml_arch_file.c /^void SetupPinEquivalenceAutoDetect(ezxml_t Parent, t_type_descriptor* Type) {$/;" f file: -SetupPinLocationsAndPinClasses read_xml_arch_file.c /^static void SetupPinLocationsAndPinClasses(ezxml_t Locations,$/;" f file: -Switches include/physical_types.h /^ struct s_switch_inf *Switches;$/;" m struct:s_arch typeref:struct:s_arch::s_switch_inf -SyncModelsPbTypes read_xml_arch_file.c /^static void SyncModelsPbTypes(INOUTP struct s_arch *arch,$/;" f file: -SyncModelsPbTypes_rec read_xml_arch_file.c /^static void SyncModelsPbTypes_rec(INOUTP struct s_arch *arch,$/;" f file: -TOKENS include/arch_types.h 19;" d -TOP include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side -TRUE include/util.h /^ FALSE, TRUE$/;" e enum:__anon4 -T_ipin_cblock include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_arch -T_ipin_cblock include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_timing_inf -T_opin_cblock include/arch_types_mrfpga.h /^ float T_opin_cblock;$/;" m struct:s_arch_mrfpga -T_opin_cblock include/physical_types.h /^ float T_opin_cblock;$/;" m struct:s_timing_inf -Tdel include/arch_types_mrfpga.h /^ float Tdel; $/;" m struct:s_memristor_inf -Tdel include/arch_types_mrfpga.h /^ float Tdel;$/;" m struct:s_buffer_inf -Tdel include/physical_types.h /^ float Tdel;$/;" m struct:s_switch_inf -UNDEFINED include/arch_types.h 22;" d -UNIFORM include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat -UNIVERSAL include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type -UNI_DIRECTIONAL include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality -UNKNOWN_CLASS include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class -UTIL_H include/util.h 2;" d -UpdateAndCheckModels read_xml_arch_file.c /^static void UpdateAndCheckModels(INOUTP struct s_arch *arch) {$/;" f file: -VPR_VERSION include/arch_types.h 16;" d -W include/physical_types.h /^ int W;$/;" m struct:s_clb_grid -WARNTAG include/util.h 27;" d -WILTON include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type -WIRE_MODEL_PIE fpga_spice_include/spice_types.h /^ WIRE_MODEL_PIE,$/;" e enum:e_wire_model_type -WIRE_MODEL_T fpga_spice_include/spice_types.h /^ WIRE_MODEL_T$/;" e enum:e_wire_model_type -XmlReadArch read_xml_arch_file.c /^void XmlReadArch(INP const char *ArchFile, INP boolean timing_enabled,$/;" f -_EZXML_H include/ezxml.h 26;" d -abs_variation fpga_spice_include/spice_types.h /^ float abs_variation;$/;" m struct:s_spice_mc_variation_params -absolute_length include/physical_types.h /^ float absolute_length;$/;" m union:s_port_power::__anon3 -absolute_power_per_instance include/physical_types.h /^ t_power_usage absolute_power_per_instance; \/* User-provided absolute power per block *\/$/;" m struct:s_pb_type_power -accuracy fpga_spice_include/spice_types.h /^ float accuracy;$/;" m struct:s_spice_meas_params -accuracy_type fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type accuracy_type;$/;" m struct:s_spice_meas_params typeref:enum:s_spice_meas_params::e_spice_accuracy_type -addr fpga_spice_include/spice_types.h /^ int addr; \/* Address to write the value *\/$/;" m struct:s_conf_bit -advanced_rram_design fpga_spice_include/spice_types.h /^ boolean advanced_rram_design;$/;" m struct:s_spice_model_design_tech_info -alloc_and_load_default_child_for_pb_type read_xml_arch_file.c /^static void alloc_and_load_default_child_for_pb_type( INOUTP t_pb_type *pb_type,$/;" f file: -alloc_ivector_and_copy_int_list util.c /^void alloc_ivector_and_copy_int_list(t_linked_int ** list_head_ptr,$/;" f -alloc_matrix util.c /^alloc_matrix(int nrmin, int nrmax, int ncmin, int ncmax, size_t elsize) {$/;" f -alloc_matrix3 util.c /^alloc_matrix3(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f -alloc_matrix4 util.c /^alloc_matrix4(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f -annotations include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_interconnect -annotations include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_pb_type -arch_mrfpga include/physical_types.h /^ t_arch_mrfpga arch_mrfpga;$/;" m struct:s_arch -area fpga_spice_include/spice_types.h /^ float area; \/\/Xifan TANG$/;" m struct:s_sram_inf -area include/physical_types.h /^ float area;$/;" m struct:s_type_descriptor -attr include/ezxml.h /^ char ***attr; \/* default attributes *\/$/;" m struct:ezxml_root -attr include/ezxml.h /^ char **attr; \/* tag attributes { name, value, name, value, ... NULL } *\/$/;" m struct:ezxml -auto_select_sim_num_clk_cycle fpga_spice_include/spice_types.h /^ int auto_select_sim_num_clk_cycle;$/;" m struct:s_spice_meas_params -autosize_buffer include/physical_types.h /^ boolean autosize_buffer; \/* autosize clock buffers *\/$/;" m struct:s_clock_network -available_in_packing include/physical_types.h /^ int available_in_packing;$/;" m struct:s_mode -base_cost include/cad_types.h /^ float base_cost; \/* base cost of pattern eg. If a group of logical blocks match a pattern of smaller primitives, that is better than the same group using bigger primitives *\/$/;" m struct:s_pack_patterns -base_cost include/cad_types.h /^ float base_cost; \/* cost independant of current status of packing *\/$/;" m struct:s_cluster_placement_primitive -bl fpga_spice_include/spice_types.h /^ t_conf_bit* bl;$/;" m struct:s_conf_bit_info -blif_model include/physical_types.h /^ char *blif_model;$/;" m struct:s_pb_type -block_id include/cad_types.h /^ int block_id;$/;" m struct:s_pack_pattern_block -boolean include/util.h /^typedef int boolean;$/;" t -boolean include/util.h /^} boolean;$/;" t typeref:enum:__anon4 -buf_size include/physical_types.h /^ float buf_size;$/;" m struct:s_switch_inf -buffer_info fpga_spice_include/spice_types.h /^ t_spice_model_buffer* buffer_info;$/;" m struct:s_spice_model_design_tech_info -buffer_size include/physical_types.h /^ float buffer_size; \/* if not autosized, the clock buffer size *\/$/;" m struct:s_clock_network -buffer_size include/physical_types.h /^ float buffer_size;$/;" m struct:s_pb_graph_pin_power -buffer_size include/physical_types.h /^ float buffer_size;$/;" m struct:s_port_power -buffer_type include/physical_types.h /^ e_power_buffer_type buffer_type;$/;" m struct:s_port_power -buffered include/physical_types.h /^ boolean buffered;$/;" m struct:s_switch_inf -cap_val fpga_spice_include/spice_types.h /^ float cap_val; $/;" m struct:s_spice_model_wire_param -capacitance include/physical_types.h /^ float capacitance;$/;" m struct:s_pb_graph_edge -capacity include/physical_types.h /^ int capacity;$/;" m struct:s_type_descriptor -captab fpga_spice_include/spice_types.h /^ int captab;$/;" m struct:s_spice_params -cat_llists linkedlist.c /^t_llist* cat_llists(t_llist* head1,$/;" f -cb include/physical_types.h /^ boolean *cb;$/;" m struct:s_segment_inf -cb_len include/physical_types.h /^ int cb_len;$/;" m struct:s_segment_inf -cb_switches include/physical_types.h /^ t_switch_inf* cb_switches;$/;" m struct:s_arch -cb_type_descriptors read_xml_arch_file.c /^static struct s_type_descriptor *cb_type_descriptors;$/;" v typeref:struct:s_type_descriptor file: -cbx_index_high fpga_spice_include/spice_types.h /^ int** cbx_index_high;$/;" m struct:s_spice_model -cbx_index_low fpga_spice_include/spice_types.h /^ int** cbx_index_low;$/;" m struct:s_spice_model -cby_index_high fpga_spice_include/spice_types.h /^ int** cby_index_high;$/;" m struct:s_spice_model -cby_index_low fpga_spice_include/spice_types.h /^ int** cby_index_low;$/;" m struct:s_spice_model -chain_name include/physical_types.h /^ char *chain_name;$/;" m struct:s_port -chain_root_pin include/cad_types.h /^ t_pb_graph_pin *chain_root_pin; \/* pointer to logic block input pin that drives this chain from the preceding logic block *\/ $/;" m struct:s_pack_patterns -chan_length fpga_spice_include/spice_types.h /^ float chan_length;$/;" m struct:s_spice_transistor_type -chan_width_io include/physical_types.h /^ float chan_width_io;$/;" m struct:s_chan_width_dist -chan_x_dist include/physical_types.h /^ t_chan chan_x_dist;$/;" m struct:s_chan_width_dist -chan_y_dist include/physical_types.h /^ t_chan chan_y_dist;$/;" m struct:s_chan_width_dist -check_spice_models read_xml_spice.c /^static void check_spice_models(int num_spice_model,$/;" f file: -check_tech_lib read_xml_spice.c /^static void check_tech_lib(t_spice_tech_lib tech_lib, $/;" f file: -child include/ezxml.h /^ ezxml_t child; \/* head of sub tag list, NULL if none *\/$/;" m struct:ezxml -child_pb_graph_nodes include/physical_types.h /^ struct s_pb_graph_node ***child_pb_graph_nodes; \/* [0..num_modes-1][0..num_pb_type_in_mode-1][0..num_pb-1] *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node -chunk_ptr_head include/util.h /^ struct s_linked_vptr *chunk_ptr_head; $/;" m struct:s_chunk typeref:struct:s_chunk::s_linked_vptr -class_inf include/physical_types.h /^ struct s_class *class_inf; \/* [0..num_class-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_class -class_type include/physical_types.h /^ enum e_pb_type_class class_type;$/;" m struct:s_pb_type typeref:enum:s_pb_type::e_pb_type_class -clb_grid include/physical_types.h /^ struct s_clb_grid clb_grid;$/;" m struct:s_arch typeref:struct:s_arch::s_clb_grid -clock include/physical_types.h /^ char * clock;$/;" m struct:s_pin_to_pin_annotation -clock_inf include/physical_types.h /^ t_clock_network *clock_inf; \/* Details about each clock *\/$/;" m struct:s_clock_arch -clock_pins include/physical_types.h /^ t_pb_graph_pin **clock_pins; \/* [0..num_clock_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node -clock_slew_fall_time fpga_spice_include/spice_types.h /^ float clock_slew_fall_time; $/;" m struct:s_spice_stimulate_params -clock_slew_fall_type fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -clock_slew_rise_time fpga_spice_include/spice_types.h /^ float clock_slew_rise_time; $/;" m struct:s_spice_stimulate_params -clock_slew_rise_type fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -clocks include/physical_types.h /^ t_clock_arch * clocks;$/;" m struct:s_arch -close ezxml.c 61;" d file: -cluster_placement_primitive include/physical_types.h /^ struct s_cluster_placement_primitive *cluster_placement_primitive; \/* pointer to indexing structure useful during packing stage *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_cluster_placement_primitive -cmos_variation fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params cmos_variation;$/;" m struct:s_spice_mc_params -cnt fpga_spice_include/spice_types.h /^ int cnt; \/* Used in mux_testbench only*\/$/;" m struct:s_spice_mux_model -cnt fpga_spice_include/spice_types.h /^ int cnt;$/;" m struct:s_spice_model -col_rel include/physical_types.h /^ float col_rel;$/;" m struct:s_grid_loc_def -conf_bit_head fpga_spice_include/spice_types.h /^ t_llist* conf_bit_head; $/;" m struct:s_sram_orgz_info -connections include/cad_types.h /^ struct s_pack_pattern_connections *connections; \/* linked list of connections of logic blocks in pattern *\/$/;" m struct:s_pack_pattern_block typeref:struct:s_pack_pattern_block::s_pack_pattern_connections -cont util.c /^static int cont; \/* line continued? *\/$/;" v file: -create_llist linkedlist.c /^t_llist* create_llist(int len) {$/;" f -cur include/ezxml.h /^ ezxml_t cur; \/* current xml tree insertion point *\/$/;" m struct:ezxml_root -current_random util.c /^static unsigned int current_random = 0;$/;" v file: -data include/util.h /^ int data;$/;" m struct:s_linked_int -data_vptr include/util.h /^ void *data_vptr;$/;" m struct:s_linked_vptr -dc include/physical_types.h /^ float dc;$/;" m struct:s_chan -default_mode_num_conf_bits include/physical_types.h /^ int default_mode_num_conf_bits;$/;" m struct:s_pb_type -default_mode_num_iopads include/physical_types.h /^ int default_mode_num_iopads;$/;" m struct:s_pb_type -default_mode_num_mode_bits include/physical_types.h /^ int default_mode_num_mode_bits;$/;" m struct:s_pb_type -default_mode_num_reserved_conf_bits include/physical_types.h /^ int default_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type -default_val fpga_spice_include/spice_types.h /^ int default_val;$/;" m struct:s_spice_model_port -define_idle_mode include/physical_types.h /^ int define_idle_mode; $/;" m struct:s_mode -define_physical_mode include/physical_types.h /^ int define_physical_mode; $/;" m struct:s_mode -delay_max include/physical_types.h /^ float delay_max;$/;" m struct:s_pb_graph_edge -delay_min include/physical_types.h /^ float delay_min;$/;" m struct:s_pb_graph_edge -delete_in_vptr_list util.c /^delete_in_vptr_list(struct s_linked_vptr *head) {$/;" f -dens include/physical_types.h /^ float dens; \/* Switching density of net assigned to this clock *\/$/;" m struct:s_clock_network -density fpga_spice_include/spice_types.h /^ float density;$/;" m struct:s_spice_net_info -depth include/physical_types.h /^ int depth; \/* depth of pb_type *\/$/;" m struct:s_pb_type -design_tech fpga_spice_include/spice_types.h /^ enum e_spice_model_design_tech design_tech;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_design_tech -design_tech_info fpga_spice_include/spice_types.h /^ t_spice_model_design_tech_info design_tech_info;$/;" m struct:s_spice_model -dir include/logic_types.h /^ enum PORTS dir; \/* port direction *\/$/;" m struct:s_model_ports typeref:enum:s_model_ports::PORTS -directionality include/physical_types.h /^ enum e_directionality directionality;$/;" m struct:s_segment_inf typeref:enum:s_segment_inf::e_directionality -dptr fpga_spice_include/linkedlist.h /^ void* dptr;$/;" m struct:s_llist -driver_pin include/physical_types.h /^ int driver_pin;$/;" m struct:s_pb_graph_edge -driver_set include/physical_types.h /^ int driver_set;$/;" m struct:s_pb_graph_edge -dump_structural_verilog fpga_spice_include/spice_types.h /^ boolean dump_structural_verilog;$/;" m struct:s_spice_model -dynamic include/physical_types.h /^ float dynamic;$/;" m struct:s_power_usage -e include/ezxml.h /^ char *e; \/* end of work area *\/$/;" m struct:ezxml_root -e_Fc_type include/physical_types.h /^enum e_Fc_type {$/;" g -e_directionality include/physical_types.h /^enum e_directionality {$/;" g -e_grid_loc_type include/physical_types.h /^enum e_grid_loc_type {$/;" g -e_interconnect include/physical_types.h /^enum e_interconnect {$/;" g -e_pb_graph_pin_type include/physical_types.h /^enum e_pb_graph_pin_type {$/;" g -e_pb_type_class include/physical_types.h /^enum e_pb_type_class {$/;" g -e_pin_location_distr include/physical_types.h /^enum e_pin_location_distr {$/;" g -e_pin_to_pin_annotation_format include/physical_types.h /^enum e_pin_to_pin_annotation_format {$/;" g -e_pin_to_pin_annotation_type include/physical_types.h /^enum e_pin_to_pin_annotation_type {$/;" g -e_pin_to_pin_capacitance_annotations include/physical_types.h /^enum e_pin_to_pin_capacitance_annotations {$/;" g -e_pin_to_pin_delay_annotations include/physical_types.h /^enum e_pin_to_pin_delay_annotations {$/;" g -e_pin_to_pin_mode_select_annotations include/physical_types.h /^enum e_pin_to_pin_mode_select_annotations {$/;" g -e_pin_to_pin_pack_pattern_annotations include/physical_types.h /^enum e_pin_to_pin_pack_pattern_annotations {$/;" g -e_pin_type include/physical_types.h /^enum e_pin_type {$/;" g -e_power_buffer_type include/physical_types.h /^} e_power_buffer_type;$/;" t typeref:enum:__anon2 -e_power_estimation_method include/physical_types.h /^typedef enum e_power_estimation_method_ e_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ -e_power_estimation_method_ include/physical_types.h /^enum e_power_estimation_method_ {$/;" g -e_power_wire_type include/physical_types.h /^} e_power_wire_type;$/;" t typeref:enum:__anon1 -e_side include/physical_types.h /^enum e_side {$/;" g -e_spice_accuracy_type fpga_spice_include/spice_types.h /^enum e_spice_accuracy_type {$/;" g -e_spice_model_buffer_type fpga_spice_include/spice_types.h /^enum e_spice_model_buffer_type {$/;" g -e_spice_model_design_tech fpga_spice_include/spice_types.h /^enum e_spice_model_design_tech {$/;" g -e_spice_model_pass_gate_logic_type fpga_spice_include/spice_types.h /^enum e_spice_model_pass_gate_logic_type {$/;" g -e_spice_model_port_type fpga_spice_include/spice_types.h /^enum e_spice_model_port_type {$/;" g -e_spice_model_structure fpga_spice_include/spice_types.h /^enum e_spice_model_structure {$/;" g -e_spice_model_type fpga_spice_include/spice_types.h /^enum e_spice_model_type {$/;" g -e_spice_tech_lib_type fpga_spice_include/spice_types.h /^enum e_spice_tech_lib_type {$/;" g -e_spice_trans_type fpga_spice_include/spice_types.h /^enum e_spice_trans_type {$/;" g -e_sram_orgz fpga_spice_include/spice_types.h /^enum e_sram_orgz {$/;" g -e_stat include/physical_types.h /^enum e_stat {$/;" g -e_switch_block_type include/physical_types.h /^enum e_switch_block_type {$/;" g -e_swseg_pattern_type include/physical_types.h /^enum e_swseg_pattern_type {$/;" g -e_tech_comp include/arch_types_mrfpga.h /^enum e_tech_comp { $/;" g -e_wire_model_type fpga_spice_include/spice_types.h /^enum e_wire_model_type {$/;" g -energy_per_toggle include/physical_types.h /^ float energy_per_toggle;$/;" m struct:s_port_power -ent include/ezxml.h /^ char **ent; \/* general entities (ampersand sequences) *\/$/;" m struct:ezxml_root -equivalent include/physical_types.h /^ boolean equivalent;$/;" m struct:s_port -err include/ezxml.h /^ char err[EZXML_ERRL]; \/* error string *\/$/;" m struct:ezxml_root -estimation_method include/physical_types.h /^ e_power_estimation_method estimation_method;$/;" m struct:s_pb_type_power -exist fpga_spice_include/spice_types.h /^ int exist;$/;" m struct:s_spice_model_buffer -ezxml include/ezxml.h /^struct ezxml {$/;" s -ezxml_add_child ezxml.c /^ezxml_t ezxml_add_child(ezxml_t xml, char *name, size_t off) {$/;" f -ezxml_add_child_d include/ezxml.h 149;" d -ezxml_ampencode ezxml.c /^ezxml_ampencode(const char *s, size_t len, char **dst, size_t * dlen,$/;" f file: -ezxml_attr ezxml.c /^ezxml_attr(ezxml_t xml, const char *attr) {$/;" f -ezxml_char_content ezxml.c /^static void ezxml_char_content(ezxml_root_t root, char *s,$/;" f file: -ezxml_child ezxml.c /^ezxml_t ezxml_child(ezxml_t xml, const char *name) {$/;" f -ezxml_close_tag ezxml.c /^static ezxml_t ezxml_close_tag(ezxml_root_t root, char *name, char *s) {$/;" f file: -ezxml_cut ezxml.c /^ezxml_t ezxml_cut(ezxml_t xml) {$/;" f -ezxml_decode ezxml.c /^ezxml_decode(char *s, char **ent, char t) {$/;" f file: -ezxml_ent_ok ezxml.c /^static int ezxml_ent_ok(char *name, char *s, char **ent) {$/;" f file: -ezxml_err ezxml.c /^static ezxml_t ezxml_err(ezxml_root_t root, char *s, const char *err, ...) {$/;" f file: -ezxml_error ezxml.c /^ezxml_error(ezxml_t xml) {$/;" f -ezxml_free ezxml.c /^void ezxml_free(ezxml_t xml) {$/;" f -ezxml_free_attr ezxml.c /^static void ezxml_free_attr(char **attr) {$/;" f file: -ezxml_get ezxml.c /^ezxml_t ezxml_get(ezxml_t xml, ...) {$/;" f -ezxml_idx ezxml.c /^ezxml_t ezxml_idx(ezxml_t xml, int idx) {$/;" f -ezxml_insert ezxml.c /^ezxml_t ezxml_insert(ezxml_t xml, ezxml_t dest, size_t off) {$/;" f -ezxml_internal_dtd ezxml.c /^static short ezxml_internal_dtd(ezxml_root_t root, char *s,$/;" f file: -ezxml_move include/ezxml.h 178;" d -ezxml_name include/ezxml.h 108;" d -ezxml_new ezxml.c /^ezxml_t ezxml_new(char *name) {$/;" f -ezxml_new_d include/ezxml.h 142;" d -ezxml_next include/ezxml.h 101;" d -ezxml_open_tag ezxml.c /^static void ezxml_open_tag(ezxml_root_t root, int line, char *name, char **attr) {$/;" f file: -ezxml_parse_fd ezxml.c /^ezxml_t ezxml_parse_fd(int fd) {$/;" f -ezxml_parse_file ezxml.c /^ezxml_t ezxml_parse_file(const char *file) {$/;" f -ezxml_parse_fp ezxml.c /^ezxml_t ezxml_parse_fp(FILE * fp) {$/;" f -ezxml_parse_str ezxml.c /^ezxml_t ezxml_parse_str(char *s, size_t len) {$/;" f -ezxml_pi ezxml.c /^ezxml_pi(ezxml_t xml, const char *target) {$/;" f -ezxml_proc_inst ezxml.c /^static void ezxml_proc_inst(ezxml_root_t root, char *s, size_t len) {$/;" f file: -ezxml_remove include/ezxml.h 181;" d -ezxml_root include/ezxml.h /^struct ezxml_root { \/* additional data for the root tag *\/$/;" s -ezxml_root_t include/ezxml.h /^typedef struct ezxml_root *ezxml_root_t;$/;" t typeref:struct:ezxml_root -ezxml_set_attr ezxml.c /^ezxml_t ezxml_set_attr(ezxml_t xml, char *name, char *value) {$/;" f -ezxml_set_attr_d include/ezxml.h 164;" d -ezxml_set_flag ezxml.c /^ezxml_t ezxml_set_flag(ezxml_t xml, short flag) {$/;" f -ezxml_set_txt ezxml.c /^ezxml_t ezxml_set_txt(ezxml_t xml, char *txt) {$/;" f -ezxml_set_txt_d include/ezxml.h 156;" d -ezxml_str2utf8 ezxml.c /^ezxml_str2utf8(char **s, size_t * len) {$/;" f file: -ezxml_t include/ezxml.h /^typedef struct ezxml *ezxml_t;$/;" t typeref:struct:ezxml -ezxml_toxml ezxml.c /^ezxml_toxml(ezxml_t xml) {$/;" f -ezxml_toxml_r ezxml.c /^ezxml_toxml_r(ezxml_t xml, char **s, size_t * len, size_t * max, size_t start,$/;" f file: -ezxml_txt include/ezxml.h 111;" d -ezxml_vget ezxml.c /^ezxml_t ezxml_vget(ezxml_t xml, va_list ap) {$/;" f -f_per_stage fpga_spice_include/spice_types.h /^ int f_per_stage;$/;" m struct:s_spice_model_buffer -fan_in include/physical_types.h /^ int fan_in;$/;" m struct:s_interconnect -fan_out include/physical_types.h /^ int fan_out;$/;" m struct:s_interconnect -fast fpga_spice_include/spice_types.h /^ int fast;$/;" m struct:s_spice_params -file_exists util.c /^boolean file_exists(const char * filename) {$/;" f -file_line_number util.c /^int file_line_number; \/* file in line number being parsed *\/$/;" v -findPortByName read_xml_arch_file.c /^static t_port * findPortByName(const char * name, t_pb_type * pb_type,$/;" f file: -find_length_llist linkedlist.c /^int find_length_llist(t_llist* head) {$/;" f -flags include/ezxml.h /^ short flags; \/* additional information *\/$/;" m struct:ezxml -format include/physical_types.h /^ enum e_pin_to_pin_annotation_format format;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_format -frac_cb include/physical_types.h /^ float frac_cb;$/;" m struct:s_segment_inf -frac_sb include/physical_types.h /^ float frac_sb;$/;" m struct:s_segment_inf -free_chunk_memory util.c /^void free_chunk_memory(t_chunk *chunk_info) {$/;" f -free_int_list util.c /^void free_int_list(t_linked_int ** int_list_head_ptr) {$/;" f -free_ivec_matrix util.c /^void free_ivec_matrix(struct s_ivec **ivec_matrix, int nrmin, int nrmax,$/;" f -free_ivec_matrix3 util.c /^void free_ivec_matrix3(struct s_ivec ***ivec_matrix3, int nrmin, int nrmax,$/;" f -free_ivec_vector util.c /^void free_ivec_vector(struct s_ivec *ivec_vector, int nrmin, int nrmax) {$/;" f -free_llist linkedlist.c /^void free_llist(t_llist* head) {$/;" f -free_matrix util.c /^void free_matrix(void *vptr, int nrmin, int nrmax, int ncmin, size_t elsize) {$/;" f -free_matrix3 util.c /^void free_matrix3(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f -free_matrix4 util.c /^void free_matrix4(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f -freq fpga_spice_include/spice_types.h /^ float freq; $/;" m struct:s_spice_net_info -frequency include/physical_types.h /^ int frequency;$/;" m struct:s_segment_inf -from_block include/cad_types.h /^ t_pack_pattern_block *from_block;$/;" m struct:s_pack_pattern_connections -from_pin include/cad_types.h /^ t_pb_graph_pin *from_pin;$/;" m struct:s_pack_pattern_connections -from_pin include/physical_types.h /^ char *from_pin;$/;" m struct:s_direct_inf -grid_conf_bits_lsb fpga_spice_include/spice_types.h /^ int** grid_conf_bits_lsb;$/;" m struct:s_sram_orgz_info -grid_conf_bits_msb fpga_spice_include/spice_types.h /^ int** grid_conf_bits_msb;$/;" m struct:s_sram_orgz_info -grid_index_high fpga_spice_include/spice_types.h /^ int** grid_index_high;$/;" m struct:s_spice_model -grid_index_low fpga_spice_include/spice_types.h /^ int** grid_index_low;$/;" m struct:s_spice_model -grid_loc_def include/physical_types.h /^ struct s_grid_loc_def *grid_loc_def; \/* [0..num_def-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_grid_loc_def -grid_loc_type include/physical_types.h /^ enum e_grid_loc_type grid_loc_type;$/;" m struct:s_grid_loc_def typeref:enum:s_grid_loc_def::e_grid_loc_type -grid_logic_tile_area include/physical_types.h /^ float grid_logic_tile_area;$/;" m struct:s_arch -grid_reserved_conf_bits fpga_spice_include/spice_types.h /^ int** grid_reserved_conf_bits;$/;" m struct:s_sram_orgz_info -height include/physical_types.h /^ int height;$/;" m struct:s_type_descriptor -idle_mode_name include/physical_types.h /^ char* idle_mode_name;$/;" m struct:s_pb_type -include_netlist fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlist;$/;" m struct:s_spice_model -include_netlists fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlists; $/;" m struct:s_spice -included fpga_spice_include/spice_types.h /^ int included;$/;" m struct:s_spice_model_netlist -incremental_cost include/cad_types.h /^ float incremental_cost; \/* cost dependant on current status of packing *\/$/;" m struct:s_cluster_placement_primitive -index fpga_spice_include/spice_types.h /^ int index;$/;" m struct:s_conf_bit_info -index include/cad_types.h /^ int index; \/* array index for pattern*\/$/;" m struct:s_pack_patterns -index include/logic_types.h /^ int index; \/* indexing for array look-up *\/$/;" m struct:s_model_ports -index include/logic_types.h /^ int index;$/;" m struct:s_model -index include/physical_types.h /^ int index; \/* index of type descriptor in array (allows for index referencing) *\/$/;" m struct:s_type_descriptor -index include/physical_types.h /^ int index;$/;" m struct:s_mode -index include/physical_types.h /^ int index;$/;" m struct:s_port -index_in_top_tb fpga_spice_include/spice_types.h /^ int index_in_top_tb;$/;" m struct:s_conf_bit_info -infer_annotations include/physical_types.h /^ boolean infer_annotations;$/;" m struct:s_interconnect -infer_pattern include/physical_types.h /^ boolean infer_pattern; \/*If TRUE, infer pattern based on patterns connected to it*\/$/;" m struct:s_pb_graph_edge -init_arch_mrfpga read_xml_mrfpga.c /^void init_arch_mrfpga(t_arch_mrfpga* arch_mrfpga) {$/;" f -init_buffer_inf read_xml_mrfpga.c /^void init_buffer_inf(t_buffer_inf* buffer_inf) {$/;" f -init_memristor_inf read_xml_mrfpga.c /^void init_memristor_inf(t_memristor_inf* memristor_inf) {$/;" f -init_val fpga_spice_include/spice_types.h /^ int init_val;$/;" m struct:s_spice_net_info -inport_link_pin include/cad_types.h /^ int inport_link_pin; \/* applicable pin of chain input port *\/$/;" m struct:s_model_chain_pattern -input_buffer fpga_spice_include/spice_types.h /^ t_spice_model_buffer* input_buffer;$/;" m struct:s_spice_model -input_edges include/physical_types.h /^ struct s_pb_graph_edge** input_edges; \/* [0..num_input_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge -input_level fpga_spice_include/spice_types.h /^ int* input_level; \/* [0...num_input] *\/$/;" m struct:s_spice_mux_arch -input_link_port include/cad_types.h /^ t_model_ports *input_link_port; \/* pointer to port of chain input *\/$/;" m struct:s_model_chain_pattern -input_offset fpga_spice_include/spice_types.h /^ int* input_offset; \/* [0...num_input] *\/ $/;" m struct:s_spice_mux_arch -input_pin_class_size include/physical_types.h /^ int *input_pin_class_size; \/* Stores the number of pins that belong to a particular input pin class *\/$/;" m struct:s_pb_graph_node -input_pins include/physical_types.h /^ char * input_pins;$/;" m struct:s_pin_to_pin_annotation -input_pins include/physical_types.h /^ struct s_pb_graph_pin *** input_pins; \/\/ [0..num_input_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin -input_pins include/physical_types.h /^ t_pb_graph_pin **input_pins; \/* [0..num_input_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node -input_pins include/physical_types.h /^ t_pb_graph_pin **input_pins;$/;" m struct:s_pb_graph_edge -input_ports_eq_auto_detect include/physical_types.h /^ boolean input_ports_eq_auto_detect;$/;" m struct:s_type_descriptor -input_slew_fall_time fpga_spice_include/spice_types.h /^ float input_slew_fall_time; $/;" m struct:s_spice_stimulate_params -input_slew_fall_type fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -input_slew_rise_time fpga_spice_include/spice_types.h /^ float input_slew_rise_time; $/;" m struct:s_spice_stimulate_params -input_slew_rise_type fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -input_string include/physical_types.h /^ char *input_string;$/;" m struct:s_interconnect -input_thres_pct_fall fpga_spice_include/spice_types.h /^ float input_thres_pct_fall;$/;" m struct:s_spice_meas_params -input_thres_pct_rise fpga_spice_include/spice_types.h /^ float input_thres_pct_rise;$/;" m struct:s_spice_meas_params -inputs include/logic_types.h /^ t_model_ports *inputs; \/* linked list of input\/clock ports *\/$/;" m struct:s_model -insert_in_int_list util.c /^insert_in_int_list(t_linked_int * head, int data,$/;" f -insert_in_vptr_list util.c /^insert_in_vptr_list(struct s_linked_vptr *head, void *vptr_to_add) {$/;" f -insert_llist_node linkedlist.c /^t_llist* insert_llist_node(t_llist* cur) {$/;" f -insert_llist_node_before_head linkedlist.c /^t_llist* insert_llist_node_before_head(t_llist* old_head) {$/;" f -insert_node_to_int_list util.c /^insert_node_to_int_list(struct s_linked_int *head, int int_to_add) {$/;" f -instances include/logic_types.h /^ void *instances;$/;" m struct:s_model -interconnect include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_interconnect_pins -interconnect include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_pb_graph_edge -interconnect include/physical_types.h /^ t_interconnect *interconnect;$/;" m struct:s_mode -interconnect_pins include/physical_types.h /^ t_interconnect_pins ** interconnect_pins; \/* [0..num_modes-1][0..num_interconnect_in_mode] *\/$/;" m struct:s_pb_graph_node -interconnect_power include/physical_types.h /^ t_interconnect_power * interconnect_power;$/;" m struct:s_interconnect -inv_spice_model fpga_spice_include/spice_types.h /^ t_spice_model* inv_spice_model;$/;" m struct:s_spice_model_port -inv_spice_model_name fpga_spice_include/spice_types.h /^ char* inv_spice_model_name;$/;" m struct:s_spice_model_port -io_vdd fpga_spice_include/spice_types.h /^ float io_vdd;$/;" m struct:s_spice_tech_lib -ipin_mux_trans_size include/physical_types.h /^ float ipin_mux_trans_size;$/;" m struct:s_arch -ipow util.c /^int ipow(int base, int exp) {$/;" f -is_Fc_frac include/physical_types.h /^ boolean *is_Fc_frac; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -is_Fc_full_flex include/physical_types.h /^ boolean *is_Fc_full_flex; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -is_accurate include/arch_types_mrfpga.h /^ boolean is_accurate;$/;" m struct:s_arch_mrfpga -is_block_optional include/cad_types.h /^ boolean *is_block_optional; \/* [0..num_blocks-1] is the block_id in this pattern mandatory or optional to form a molecule *\/$/;" m struct:s_pack_patterns -is_chain include/cad_types.h /^ boolean is_chain; \/* Does this pattern chain across logic blocks *\/$/;" m struct:s_pack_patterns -is_clock include/logic_types.h /^ boolean is_clock; \/* clock? *\/$/;" m struct:s_model_ports -is_clock include/physical_types.h /^ boolean is_clock;$/;" m struct:s_port -is_config_enable fpga_spice_include/spice_types.h /^ boolean is_config_enable;$/;" m struct:s_spice_model_port -is_default fpga_spice_include/spice_types.h /^ int is_default;$/;" m struct:s_spice_model -is_forced_connection include/physical_types.h /^ boolean is_forced_connection; \/* This output pin connects to one and only one input pin *\/$/;" m struct:s_pb_graph_pin -is_global fpga_spice_include/spice_types.h /^ boolean is_global;$/;" m struct:s_spice_model_port -is_global_pin include/physical_types.h /^ boolean *is_global_pin; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -is_isolation include/arch_types_mrfpga.h /^ boolean is_isolation;$/;" m struct:s_arch_mrfpga -is_junction include/arch_types_mrfpga.h /^ boolean is_junction;$/;" m struct:s_arch_mrfpga -is_mrFPGA include/arch_types_mrfpga.h /^ boolean is_mrFPGA;$/;" m struct:s_arch_mrfpga -is_non_clock_global include/logic_types.h /^ boolean is_non_clock_global; \/* not a clock but is a special, global, control signal (eg global asynchronous reset, etc) *\/$/;" m struct:s_model_ports -is_non_clock_global include/physical_types.h /^ boolean is_non_clock_global;$/;" m struct:s_port -is_opin_cblock_defined include/arch_types_mrfpga.h /^ int is_opin_cblock_defined;$/;" m struct:s_arch_mrfpga -is_prog fpga_spice_include/spice_types.h /^ boolean is_prog;$/;" m struct:s_spice_model_port -is_reset fpga_spice_include/spice_types.h /^ boolean is_reset;$/;" m struct:s_spice_model_port -is_set fpga_spice_include/spice_types.h /^ boolean is_set;$/;" m struct:s_spice_model_port -is_show_pass_trans include/arch_types_mrfpga.h /^ boolean is_show_pass_trans;$/;" m struct:s_arch_mrfpga -is_show_sram include/arch_types_mrfpga.h /^ boolean is_show_sram;$/;" m struct:s_arch_mrfpga -is_stack include/arch_types_mrfpga.h /^ boolean is_stack;$/;" m struct:s_arch_mrfpga -is_wire_buffer include/arch_types_mrfpga.h /^ boolean is_wire_buffer;$/;" m struct:s_arch_mrfpga -leakage include/physical_types.h /^ float leakage;$/;" m struct:s_power_usage -leakage_default_mode include/physical_types.h /^ int leakage_default_mode; \/* Default mode for leakage analysis, if block has no set mode *\/$/;" m struct:s_pb_type_power -len include/ezxml.h /^ size_t len; \/* length of allocated memory for mmap, -1 for malloc *\/$/;" m struct:ezxml_root -length include/physical_types.h /^ int length;$/;" m struct:s_segment_inf -level fpga_spice_include/spice_types.h /^ int level;$/;" m struct:s_spice_model_wire_param -limit_value util.c /^int limit_value(int cur, int max, const char *name) {$/;" f -line include/ezxml.h /^ int line;$/;" m struct:ezxml -line include/physical_types.h /^ int line;$/;" m struct:s_direct_inf -line_num include/physical_types.h /^ int line_num; \/* Interconnect is processed later, need to know what line number it messed up on to give proper error message *\/$/;" m struct:s_interconnect -line_num include/physical_types.h /^ int line_num; \/* used to report what line number this annotation is found in architecture file *\/$/;" m struct:s_pin_to_pin_annotation -list include/util.h /^ int *list;$/;" m struct:s_ivec -list_of_connectable_input_pin_ptrs include/physical_types.h /^ struct s_pb_graph_pin ***list_of_connectable_input_pin_ptrs; \/* [0..depth-1][0..num_connectable_primtive_input_pins-1] what input pins this output can connect to without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin -local_interc_factor include/physical_types.h /^ float local_interc_factor;$/;" m struct:s_power_arch -logical_effort_factor include/physical_types.h /^ float logical_effort_factor;$/;" m struct:s_power_arch -longline include/physical_types.h /^ boolean longline;$/;" m struct:s_segment_inf -lut_input_buffer fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_input_buffer;$/;" m struct:s_spice_model -m include/ezxml.h /^ char *m; \/* original xml string *\/$/;" m struct:ezxml_root -main ezxml.c /^main(int argc,$/;" f -main main.c /^int main(int argc, char **argv) {$/;" f -main_best_buffer_list include/arch_types_mrfpga.h /^ t_linked_int* main_best_buffer_list;$/;" m struct:s_arch_mrfpga -max_internal_delay include/physical_types.h /^ float max_internal_delay;$/;" m struct:s_pb_type -max_pins_per_side include/arch_types_mrfpga.h /^ int max_pins_per_side;$/;" m struct:s_arch_mrfpga -mc_params fpga_spice_include/spice_types.h /^ t_spice_mc_params mc_params;$/;" m struct:s_spice_params -mc_sim fpga_spice_include/spice_types.h /^ boolean mc_sim;$/;" m struct:s_spice_mc_params -meas_params fpga_spice_include/spice_types.h /^ t_spice_meas_params meas_params;$/;" m struct:s_spice_params -mem_avail include/util.h /^ int mem_avail; \/* number of bytes left in the current chunk *\/$/;" m struct:s_chunk -mem_bank_info fpga_spice_include/spice_types.h /^ t_mem_bank_info* mem_bank_info; \/* Only be allocated when orgz type is memory bank *\/$/;" m struct:s_sram_orgz_info -mem_model fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_mem_bank_info -mem_model fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_scff_info -mem_model fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_standalone_sram_info -memristor_inf include/arch_types_mrfpga.h /^ t_memristor_inf memristor_inf;$/;" m struct:s_arch_mrfpga -messagelogger include/util.h /^typedef unsigned char (*messagelogger)( TIO_MessageMode_t messageMode,$/;" t -min_size include/logic_types.h /^ int min_size; \/* minimum number of pins *\/$/;" m struct:s_model_ports -min_width fpga_spice_include/spice_types.h /^ float min_width;$/;" m struct:s_spice_transistor_type -mode_bits include/physical_types.h /^ char* mode_bits; \/* Mode bits to select *\/$/;" m struct:s_pb_type -mode_power include/physical_types.h /^ t_mode_power * mode_power;$/;" m struct:s_mode -mode_select fpga_spice_include/spice_types.h /^ boolean mode_select;$/;" m struct:s_spice_model_port -model include/cad_types.h /^ t_model *model; \/* block associated with chain *\/$/;" m struct:s_model_chain_pattern -model include/physical_types.h /^ t_model *model;$/;" m struct:s_pb_type -model_library include/physical_types.h /^ t_model *model_library;$/;" m struct:s_arch -model_name fpga_spice_include/spice_types.h /^ char* model_name;$/;" m struct:s_spice_transistor_type -model_netlist fpga_spice_include/spice_types.h /^ char* model_netlist; \/* SPICE netlist provided by user *\/$/;" m struct:s_spice_model -model_port include/physical_types.h /^ t_model_ports *model_port;$/;" m struct:s_port -model_ref fpga_spice_include/spice_types.h /^ char* model_ref;$/;" m struct:s_spice_tech_lib -models include/physical_types.h /^ t_model *models;$/;" m struct:s_arch -modes include/physical_types.h /^ t_mode *modes; \/* [0..num_modes-1] *\/$/;" m struct:s_pb_type -mux_num_level fpga_spice_include/spice_types.h /^ int mux_num_level;$/;" m struct:s_spice_model_design_tech_info -mux_trans_size include/physical_types.h /^ float mux_trans_size;$/;" m struct:s_switch_inf -mux_transistor_size include/physical_types.h /^ float mux_transistor_size;$/;" m struct:s_power_arch -my_atoi util.c /^int my_atoi(const char *str) {$/;" f -my_calloc util.c /^my_calloc(size_t nelem, size_t size) {$/;" f -my_chunk_malloc util.c /^my_chunk_malloc(size_t size, t_chunk *chunk_info) {$/;" f -my_fgets util.c /^my_fgets(char *buf, int max_size, FILE * fp) {$/;" f -my_fopen util.c /^my_fopen(const char *fname, const char *flag, int prompt) {$/;" f -my_frand util.c /^float my_frand(void) {$/;" f -my_free read_xml_spice_util.c /^void my_free(void* ptr) {$/;" f -my_irand util.c /^int my_irand(int imax) {$/;" f -my_malloc util.c /^my_malloc(size_t size) {$/;" f -my_realloc util.c /^my_realloc(void *ptr, size_t size) {$/;" f -my_srandom util.c /^void my_srandom(int seed) {$/;" f -my_strdup util.c /^my_strdup(const char *str) {$/;" f -my_strncpy util.c /^my_strncpy(char *dest, const char *src, size_t size) {$/;" f -my_strtok util.c /^my_strtok(char *ptr, const char *tokens, FILE * fp, char *buf) {$/;" f -name fpga_spice_include/spice_types.h /^ char* name;$/;" m struct:s_spice_model -name include/cad_types.h /^ char *name; \/* name of this chain of logic *\/$/;" m struct:s_model_chain_pattern -name include/cad_types.h /^ char *name; \/* name of this logic model pattern *\/$/;" m struct:s_pack_patterns -name include/ezxml.h /^ char *name; \/* tag name *\/$/;" m struct:ezxml -name include/logic_types.h /^ char *name; \/* name of this logic model *\/$/;" m struct:s_model -name include/logic_types.h /^ char *name; \/* name of this port *\/$/;" m struct:s_model_ports -name include/physical_types.h /^ char *name;$/;" m struct:s_direct_inf -name include/physical_types.h /^ char *name;$/;" m struct:s_interconnect -name include/physical_types.h /^ char *name;$/;" m struct:s_switch_inf -name include/physical_types.h /^ char *name;$/;" m struct:s_type_descriptor -name include/physical_types.h /^ char* name;$/;" m struct:s_mode -name include/physical_types.h /^ char* name;$/;" m struct:s_pb_type -name include/physical_types.h /^ char* name;$/;" m struct:s_port -nelem include/util.h /^ int nelem;$/;" m struct:s_ivec -next fpga_spice_include/linkedlist.h /^ t_llist* next;$/;" m struct:s_llist -next include/cad_types.h /^ struct s_model_chain_pattern *next; \/* next chain (linked list) *\/$/;" m struct:s_model_chain_pattern typeref:struct:s_model_chain_pattern::s_model_chain_pattern -next include/cad_types.h /^ struct s_pack_pattern_connections *next;$/;" m struct:s_pack_pattern_connections typeref:struct:s_pack_pattern_connections::s_pack_pattern_connections -next include/ezxml.h /^ ezxml_t next; \/* next tag with same name in this section at this depth *\/$/;" m struct:ezxml -next include/logic_types.h /^ struct s_model *next; \/* next model (linked list) *\/$/;" m struct:s_model typeref:struct:s_model::s_model -next include/logic_types.h /^ struct s_model_ports *next; \/* next port *\/$/;" m struct:s_model_ports typeref:struct:s_model_ports::s_model_ports -next include/util.h /^ struct s_linked_int *next;$/;" m struct:s_linked_int typeref:struct:s_linked_int::s_linked_int -next include/util.h /^ struct s_linked_vptr *next;$/;" m struct:s_linked_vptr typeref:struct:s_linked_vptr::s_linked_vptr -next_mem_loc_ptr include/util.h /^ char *next_mem_loc_ptr;\/* pointer to the first available (free) *$/;" m struct:s_chunk -next_primitive include/cad_types.h /^ struct s_cluster_placement_primitive *next_primitive;$/;" m struct:s_cluster_placement_primitive typeref:struct:s_cluster_placement_primitive::s_cluster_placement_primitive -nint include/util.h 24;" d -nmos_size fpga_spice_include/spice_types.h /^ float nmos_size;$/;" m struct:s_spice_model_pass_gate_logic -nominal_vdd fpga_spice_include/spice_types.h /^ float nominal_vdd;$/;" m struct:s_spice_tech_lib -num_annotations include/physical_types.h /^ int num_annotations;$/;" m struct:s_interconnect -num_annotations include/physical_types.h /^ int num_annotations;$/;" m struct:s_pb_type -num_bl fpga_spice_include/spice_types.h /^ int num_bl; \/* Number of Bit Lines in total *\/$/;" m struct:s_mem_bank_info -num_blocks include/cad_types.h /^ int num_blocks; \/* number of blocks in pattern *\/$/;" m struct:s_pack_patterns -num_cb_switch include/physical_types.h /^ int num_cb_switch;$/;" m struct:s_arch -num_class include/physical_types.h /^ int num_class;$/;" m struct:s_type_descriptor -num_clock_pins include/physical_types.h /^ int *num_clock_pins; \/* [0..num_clock_ports - 1] *\/$/;" m struct:s_pb_graph_node -num_clock_pins include/physical_types.h /^ int num_clock_pins;$/;" m struct:s_pb_type -num_clock_ports include/physical_types.h /^ int num_clock_ports;$/;" m struct:s_pb_graph_node -num_clocks fpga_spice_include/spice_types.h /^ int num_clocks;$/;" m struct:s_spice_stimulate_params -num_connectable_primtive_input_pins include/physical_types.h /^ int *num_connectable_primtive_input_pins; \/* [0..depth-1] number of input pins that this output pin can reach without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin -num_directs include/physical_types.h /^ int num_directs;$/;" m struct:s_arch -num_drivers include/physical_types.h /^ int num_drivers;$/;" m struct:s_type_descriptor -num_global_clocks include/physical_types.h /^ int num_global_clocks;$/;" m struct:s_clock_arch -num_grid_loc_def include/physical_types.h /^ int num_grid_loc_def;$/;" m struct:s_type_descriptor -num_include_netlist fpga_spice_include/spice_types.h /^ int num_include_netlist;$/;" m struct:s_spice -num_input fpga_spice_include/spice_types.h /^ int num_input;$/;" m struct:s_spice_mux_arch -num_input_basis fpga_spice_include/spice_types.h /^ int num_input_basis;$/;" m struct:s_spice_mux_arch -num_input_edges include/physical_types.h /^ int num_input_edges;$/;" m struct:s_pb_graph_pin -num_input_last_level fpga_spice_include/spice_types.h /^ int num_input_last_level;$/;" m struct:s_spice_mux_arch -num_input_per_level fpga_spice_include/spice_types.h /^ int* num_input_per_level; \/* [0...num_level] *\/$/;" m struct:s_spice_mux_arch -num_input_pin_class include/physical_types.h /^ int num_input_pin_class; \/* number of pin classes that this input pb_graph_node has *\/$/;" m struct:s_pb_graph_node -num_input_pins include/physical_types.h /^ int *num_input_pins; \/* [0..num_input_ports - 1] *\/$/;" m struct:s_pb_graph_node -num_input_pins include/physical_types.h /^ int num_input_pins; \/* inputs not including clock pins *\/$/;" m struct:s_pb_type -num_input_pins include/physical_types.h /^ int num_input_pins;$/;" m struct:s_pb_graph_edge -num_input_ports include/physical_types.h /^ int num_input_ports;$/;" m struct:s_interconnect_power -num_input_ports include/physical_types.h /^ int num_input_ports;$/;" m struct:s_pb_graph_node -num_interconnect include/physical_types.h /^ int num_interconnect;$/;" m struct:s_mode -num_level fpga_spice_include/spice_types.h /^ int num_level;$/;" m struct:s_spice_mux_arch -num_mc_points fpga_spice_include/spice_types.h /^ int num_mc_points;$/;" m struct:s_spice_mc_params -num_mem_bit fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_mem_bank_info -num_mem_bit fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_scff_info -num_mem_bit fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_standalone_sram_info -num_modes include/physical_types.h /^ int num_modes;$/;" m struct:s_pb_type -num_mux include/physical_types.h /^ int num_mux;$/;" m struct:s_interconnect -num_normal_switch include/arch_types_mrfpga.h /^ short num_normal_switch;$/;" m struct:s_arch_mrfpga -num_output_edges include/physical_types.h /^ int num_output_edges;$/;" m struct:s_pb_graph_pin -num_output_pin_class include/physical_types.h /^ int num_output_pin_class; \/* number of output pin classes that this pb_graph_node has *\/$/;" m struct:s_pb_graph_node -num_output_pins include/physical_types.h /^ int *num_output_pins; \/* [0..num_output_ports - 1] *\/$/;" m struct:s_pb_graph_node -num_output_pins include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_graph_edge -num_output_pins include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_type -num_output_ports include/physical_types.h /^ int num_output_ports;$/;" m struct:s_interconnect_power -num_output_ports include/physical_types.h /^ int num_output_ports;$/;" m struct:s_pb_graph_node -num_pack_patterns include/physical_types.h /^ int num_pack_patterns;$/;" m struct:s_pb_graph_edge -num_pb include/physical_types.h /^ int num_pb;$/;" m struct:s_pb_type -num_pb_type_children include/physical_types.h /^ int num_pb_type_children;$/;" m struct:s_mode -num_pin_loc_assignments include/physical_types.h /^ int **num_pin_loc_assignments; \/* [0..height-1][0..3] *\/$/;" m struct:s_type_descriptor -num_pin_timing include/physical_types.h /^ int num_pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin -num_pins include/physical_types.h /^ int num_pins;$/;" m struct:s_class -num_pins include/physical_types.h /^ int num_pins;$/;" m struct:s_port -num_pins include/physical_types.h /^ int num_pins;$/;" m struct:s_type_descriptor -num_pins_per_port include/physical_types.h /^ int num_pins_per_port;$/;" m struct:s_interconnect_power -num_port fpga_spice_include/spice_types.h /^ int num_port;$/;" m struct:s_spice_model -num_ports include/physical_types.h /^ int num_ports;$/;" m struct:s_pb_type -num_receivers include/physical_types.h /^ int num_receivers;$/;" m struct:s_type_descriptor -num_scff fpga_spice_include/spice_types.h /^ int num_scff; \/* Number of Scan-chain flip-flops *\/$/;" m struct:s_scff_info -num_segments include/physical_types.h /^ int num_segments;$/;" m struct:s_arch -num_sigma fpga_spice_include/spice_types.h /^ int num_sigma;$/;" m struct:s_spice_mc_variation_params -num_sim_clock_cycles fpga_spice_include/spice_types.h /^ int num_sim_clock_cycles;$/;" m struct:s_spicetb_info -num_spice_model fpga_spice_include/spice_types.h /^ int num_spice_model;$/;" m struct:s_spice -num_sram fpga_spice_include/spice_types.h /^ int num_sram; \/* Number of SRAMs in total *\/$/;" m struct:s_standalone_sram_info -num_switches include/physical_types.h /^ int num_switches;$/;" m struct:s_arch -num_swseg_pattern include/physical_types.h /^ int num_swseg_pattern;$/;" m struct:s_arch -num_transistor_type fpga_spice_include/spice_types.h /^ int num_transistor_type;$/;" m struct:s_spice_tech_lib -num_value_prop_pairs include/physical_types.h /^ int num_value_prop_pairs;$/;" m struct:s_pin_to_pin_annotation -num_wl fpga_spice_include/spice_types.h /^ int num_wl; \/* Number of Word Lines in total *\/$/;" m struct:s_mem_bank_info -off include/ezxml.h /^ size_t off; \/* tag offset from start of parent tag character content *\/$/;" m struct:ezxml -op_clock_freq fpga_spice_include/spice_types.h /^ float op_clock_freq; \/* Operation clock frequency*\/$/;" m struct:s_spice_stimulate_params -open ezxml.c 58;" d file: -opin_switch include/physical_types.h /^ short opin_switch;$/;" m struct:s_segment_inf -opin_to_cb include/physical_types.h /^ boolean opin_to_cb;$/;" m struct:s_type_descriptor -ordered include/ezxml.h /^ ezxml_t ordered; \/* next tag, same section and depth, in original order *\/$/;" m struct:ezxml -out_file_prefix util.c /^char *out_file_prefix = NULL;$/;" v -outport_link_pin include/cad_types.h /^ int outport_link_pin; \/* applicable pin of chain output port *\/$/;" m struct:s_model_chain_pattern -output_buffer fpga_spice_include/spice_types.h /^ t_spice_model_buffer* output_buffer;$/;" m struct:s_spice_model -output_edges include/physical_types.h /^ struct s_pb_graph_edge** output_edges; \/* [0..num_output_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge -output_link_port include/cad_types.h /^ t_model_ports *output_link_port; \/* pointer to port of chain output *\/$/;" m struct:s_model_chain_pattern -output_pin_class_size include/physical_types.h /^ int *output_pin_class_size; \/* Stores the number of pins that belong to a particular output pin class *\/$/;" m struct:s_pb_graph_node -output_pins include/physical_types.h /^ char * output_pins;$/;" m struct:s_pin_to_pin_annotation -output_pins include/physical_types.h /^ struct s_pb_graph_pin *** output_pins; \/\/ [0..num_output_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin -output_pins include/physical_types.h /^ t_pb_graph_pin **output_pins; \/* [0..num_output_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node -output_pins include/physical_types.h /^ t_pb_graph_pin **output_pins;$/;" m struct:s_pb_graph_edge -output_ports_eq_auto_detect include/physical_types.h /^ boolean output_ports_eq_auto_detect;$/;" m struct:s_type_descriptor -output_string include/physical_types.h /^ char *output_string;$/;" m struct:s_interconnect -output_thres_pct_fall fpga_spice_include/spice_types.h /^ float output_thres_pct_fall;$/;" m struct:s_spice_meas_params -output_thres_pct_rise fpga_spice_include/spice_types.h /^ float output_thres_pct_rise;$/;" m struct:s_spice_meas_params -outputs include/logic_types.h /^ t_model_ports *outputs; \/* linked list of output ports *\/$/;" m struct:s_model -pack_pattern_indices include/physical_types.h /^ int *pack_pattern_indices; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge -pack_pattern_names include/physical_types.h /^ char **pack_pattern_names; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge -parent include/ezxml.h /^ ezxml_t parent; \/* parent tag, NULL if current tag is root tag *\/$/;" m struct:ezxml -parent_mode include/physical_types.h /^ t_mode * parent_mode;$/;" m struct:s_interconnect -parent_mode include/physical_types.h /^ t_mode *parent_mode;$/;" m struct:s_pb_type -parent_mode_index include/physical_types.h /^ int parent_mode_index;$/;" m struct:s_interconnect -parent_node include/physical_types.h /^ struct s_pb_graph_node *parent_node;$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_node -parent_pb_graph_node include/physical_types.h /^ struct s_pb_graph_node *parent_pb_graph_node;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node -parent_pb_type include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type -parent_pb_type include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_port typeref:struct:s_port::s_pb_type -parent_pin_class include/physical_types.h /^ int *parent_pin_class; \/* [0..depth-1] the grouping of pins that this particular pin belongs to *\/$/;" m struct:s_pb_graph_pin -parent_spice_model fpga_spice_include/spice_types.h /^ t_spice_model* parent_spice_model;$/;" m struct:s_conf_bit_info -parent_spice_model_index fpga_spice_include/spice_types.h /^ int parent_spice_model_index;$/;" m struct:s_conf_bit_info -pass_gate_info fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_info;$/;" m struct:s_spice_model_design_tech_info -pass_gate_logic fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_logic;$/;" m struct:s_spice_model -path fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_model_netlist -path fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_tech_lib -pattern_index include/cad_types.h /^ int pattern_index; \/* index of pattern that this block is a part of *\/$/;" m struct:s_pack_pattern_block -pattern_length include/physical_types.h /^ int pattern_length;$/;" m struct:s_swseg_pattern_inf -patterns include/physical_types.h /^ boolean* patterns;$/;" m struct:s_swseg_pattern_inf -pb_graph_head include/physical_types.h /^ t_pb_graph_node *pb_graph_head;$/;" m struct:s_type_descriptor -pb_graph_node include/cad_types.h /^ t_pb_graph_node *pb_graph_node;$/;" m struct:s_cluster_placement_primitive -pb_node_power include/physical_types.h /^ t_pb_graph_node_power * pb_node_power;$/;" m struct:s_pb_graph_node -pb_type include/cad_types.h /^ const t_pb_type *pb_type; \/* pb_type that this block is an instance of *\/$/;" m struct:s_pack_pattern_block -pb_type include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_type -pb_type include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_pb_type -pb_type_children include/physical_types.h /^ struct s_pb_type *pb_type_children; \/* [0..num_child_pb_types] *\/$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type -pb_type_power include/physical_types.h /^ t_pb_type_power * pb_type_power;$/;" m struct:s_pb_type -pb_types include/logic_types.h /^ struct s_linked_vptr *pb_types; \/* Physical block types that implement this model *\/$/;" m struct:s_model typeref:struct:s_model::s_linked_vptr -peak include/physical_types.h /^ float peak;$/;" m struct:s_chan -period include/physical_types.h /^ float period; \/* Period of clock *\/$/;" m struct:s_clock_network -physical_mode_name include/physical_types.h /^ char* physical_mode_name;$/;" m struct:s_pb_type -physical_mode_num_conf_bits include/physical_types.h /^ int physical_mode_num_conf_bits;$/;" m struct:s_pb_type -physical_mode_num_iopads include/physical_types.h /^ int physical_mode_num_iopads;$/;" m struct:s_pb_type -physical_mode_num_reserved_conf_bits include/physical_types.h /^ int physical_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type -pi include/ezxml.h /^ char ***pi; \/* processing instructions *\/$/;" m struct:ezxml_root -pin_class include/physical_types.h /^ int *pin_class; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -pin_class include/physical_types.h /^ int pin_class;$/;" m struct:s_pb_graph_pin -pin_count_in_cluster include/physical_types.h /^ int pin_count_in_cluster;$/;" m struct:s_pb_graph_pin -pin_height include/physical_types.h /^ int *pin_height; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -pin_index_per_side include/physical_types.h /^ int* pin_index_per_side;$/;" m struct:s_type_descriptor -pin_loc_assignments include/physical_types.h /^ char ****pin_loc_assignments; \/* [0..height-1][0..3][0..num_tokens-1][0..string_name] *\/$/;" m struct:s_type_descriptor -pin_location_distribution include/physical_types.h /^ enum e_pin_location_distr pin_location_distribution;$/;" m struct:s_type_descriptor typeref:enum:s_type_descriptor::e_pin_location_distr -pin_number include/physical_types.h /^ int pin_number;$/;" m struct:s_pb_graph_pin -pin_power include/physical_types.h /^ t_pb_graph_pin_power * pin_power;$/;" m struct:s_pb_graph_pin -pin_ptc_to_side include/physical_types.h /^ int* pin_ptc_to_side;$/;" m struct:s_type_descriptor -pin_timing include/physical_types.h /^ struct s_pb_graph_pin** pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin -pin_timing_del_max include/physical_types.h /^ float *pin_timing_del_max; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin -pin_toggle_initialized include/physical_types.h /^ boolean pin_toggle_initialized;$/;" m struct:s_port_power -pinlist include/physical_types.h /^ int *pinlist; \/* [0..num_pins - 1] *\/$/;" m struct:s_class -pinloc include/physical_types.h /^ int ***pinloc; \/* [0..height-1][0..3][0..num_pins-1] *\/$/;" m struct:s_type_descriptor -placement_index include/physical_types.h /^ int placement_index;$/;" m struct:s_pb_graph_node -pmos_size fpga_spice_include/spice_types.h /^ float pmos_size;$/;" m struct:s_spice_model_pass_gate_logic -pn_ratio fpga_spice_include/spice_types.h /^ float pn_ratio;$/;" m struct:s_spice_tech_lib -port include/physical_types.h /^ t_port *port;$/;" m struct:s_pb_graph_pin -port_class include/physical_types.h /^ char * port_class;$/;" m struct:s_port -port_index_by_type include/physical_types.h /^ int port_index_by_type;$/;" m struct:s_port -port_info_initialized include/physical_types.h /^ boolean port_info_initialized;$/;" m struct:s_interconnect_power -port_power include/physical_types.h /^ t_port_power * port_power;$/;" m struct:s_port -ports fpga_spice_include/spice_types.h /^ t_spice_model_port* ports;$/;" m struct:s_spice_model -ports include/physical_types.h /^ t_port *ports; \/* [0..num_ports] *\/$/;" m struct:s_pb_type -post fpga_spice_include/spice_types.h /^ int post;$/;" m struct:s_spice_params -power include/physical_types.h /^ t_power_arch * power;$/;" m struct:s_arch -power_buffer_size include/physical_types.h /^ float power_buffer_size;$/;" m struct:s_switch_inf -power_buffer_type include/physical_types.h /^ e_power_buffer_type power_buffer_type;$/;" m struct:s_switch_inf -power_gated fpga_spice_include/spice_types.h /^ boolean power_gated;$/;" m struct:s_spice_model_design_tech_info -power_method_inherited read_xml_arch_file.c /^e_power_estimation_method power_method_inherited($/;" f -power_usage include/physical_types.h /^ t_power_usage power_usage; \/* Power usage of this mode *\/$/;" m struct:s_mode_power -power_usage include/physical_types.h /^ t_power_usage power_usage; \/* Total power usage of this pb type *\/$/;" m struct:s_pb_type_power -power_usage include/physical_types.h /^ t_power_usage power_usage;$/;" m struct:s_interconnect_power -power_usage_bufs_wires include/physical_types.h /^ t_power_usage power_usage_bufs_wires; \/* Power dissipated in local buffers and wire switching (Subset of total power) *\/$/;" m struct:s_pb_type_power -prefix fpga_spice_include/spice_types.h /^ char* prefix; $/;" m struct:s_spice_model_port -prefix fpga_spice_include/spice_types.h /^ char* prefix; \/* Prefix when it show up in the spice netlist *\/$/;" m struct:s_spice_model -print_help main.c /^void print_help() {$/;" f -print_int_matrix3 util.c /^void print_int_matrix3(int ***vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f -priority include/physical_types.h /^ int priority;$/;" m struct:s_grid_loc_def -prob include/physical_types.h /^ float prob; \/* Static probability of net assigned to this clock *\/$/;" m struct:s_clock_network -probability fpga_spice_include/spice_types.h /^ float probability;$/;" m struct:s_spice_net_info -prog_clock_freq fpga_spice_include/spice_types.h /^ float prog_clock_freq; \/* Programming clock frequency, used during programming phase only *\/$/;" m struct:s_spice_stimulate_params -prop include/physical_types.h /^ int * prop; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation -pwh fpga_spice_include/spice_types.h /^ float pwh;$/;" m struct:s_spice_net_info -pwl fpga_spice_include/spice_types.h /^ float pwl;$/;" m struct:s_spice_net_info -read ezxml.c 59;" d file: -read_xml_spice include/physical_types.h /^ boolean read_xml_spice;$/;" m struct:s_arch -relative_length include/physical_types.h /^ float relative_length;$/;" m union:s_port_power::__anon3 -remove_llist_node linkedlist.c /^void remove_llist_node(t_llist* cur) { $/;" f -repeat include/physical_types.h /^ int repeat;$/;" m struct:s_grid_loc_def -res_val fpga_spice_include/spice_types.h /^ float res_val;$/;" m struct:s_spice_model_wire_param -reserved_bl fpga_spice_include/spice_types.h /^ int reserved_bl; \/* Number of reserved BLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info -reserved_wl fpga_spice_include/spice_types.h /^ int reserved_wl; \/* Number of reserved WLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info -reverse_llist linkedlist.c /^t_llist* reverse_llist(t_llist* head) {$/;" f -reverse_scaled include/physical_types.h /^ boolean reverse_scaled; \/* Scale by (1-prob) *\/$/;" m struct:s_port_power -roff fpga_spice_include/spice_types.h /^ float roff;$/;" m struct:s_spice_model_design_tech_info -ron fpga_spice_include/spice_types.h /^ float ron;$/;" m struct:s_spice_model_design_tech_info -root_block include/cad_types.h /^ t_pack_pattern_block *root_block; \/* root block used by this pattern *\/$/;" m struct:s_pack_patterns -rram_pass_tran_value include/arch_types_mrfpga.h /^ float rram_pass_tran_value;$/;" m struct:s_arch_mrfpga -rram_variation fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params rram_variation;$/;" m struct:s_spice_mc_params -s include/ezxml.h /^ char *s; \/* start of work area *\/$/;" m struct:ezxml_root -s_arch include/physical_types.h /^struct s_arch {$/;" s -s_arch_mrfpga include/arch_types_mrfpga.h /^struct s_arch_mrfpga {$/;" s -s_buffer_inf include/arch_types_mrfpga.h /^struct s_buffer_inf { $/;" s -s_chan include/physical_types.h /^typedef struct s_chan {$/;" s -s_chan_width_dist include/physical_types.h /^typedef struct s_chan_width_dist {$/;" s -s_chunk include/util.h /^typedef struct s_chunk {$/;" s -s_class include/physical_types.h /^struct s_class {$/;" s -s_clb_grid include/physical_types.h /^struct s_clb_grid {$/;" s -s_clock_arch include/physical_types.h /^struct s_clock_arch {$/;" s -s_clock_network include/physical_types.h /^struct s_clock_network {$/;" s -s_cluster_placement_primitive include/cad_types.h /^typedef struct s_cluster_placement_primitive {$/;" s -s_conf_bit fpga_spice_include/spice_types.h /^struct s_conf_bit {$/;" s -s_conf_bit_info fpga_spice_include/spice_types.h /^struct s_conf_bit_info {$/;" s -s_direct_inf include/physical_types.h /^typedef struct s_direct_inf {$/;" s -s_grid_loc_def include/physical_types.h /^typedef struct s_grid_loc_def {$/;" s -s_interconnect include/physical_types.h /^struct s_interconnect {$/;" s -s_interconnect_pins include/physical_types.h /^struct s_interconnect_pins {$/;" s -s_interconnect_power include/physical_types.h /^struct s_interconnect_power {$/;" s -s_ivec include/util.h /^typedef struct s_ivec {$/;" s -s_linked_int include/util.h /^typedef struct s_linked_int {$/;" s -s_linked_vptr include/util.h /^typedef struct s_linked_vptr {$/;" s -s_llist fpga_spice_include/linkedlist.h /^struct s_llist$/;" s -s_mem_bank_info fpga_spice_include/spice_types.h /^struct s_mem_bank_info {$/;" s -s_memristor_inf include/arch_types_mrfpga.h /^struct s_memristor_inf { $/;" s -s_mode include/physical_types.h /^struct s_mode {$/;" s -s_mode_power include/physical_types.h /^struct s_mode_power {$/;" s -s_model include/logic_types.h /^typedef struct s_model {$/;" s -s_model_chain_pattern include/cad_types.h /^typedef struct s_model_chain_pattern {$/;" s -s_model_ports include/logic_types.h /^typedef struct s_model_ports {$/;" s -s_pack_pattern_block include/cad_types.h /^typedef struct s_pack_pattern_block {$/;" s -s_pack_pattern_connections include/cad_types.h /^typedef struct s_pack_pattern_connections {$/;" s -s_pack_patterns include/cad_types.h /^typedef struct s_pack_patterns {$/;" s -s_pb_graph_edge include/physical_types.h /^struct s_pb_graph_edge {$/;" s -s_pb_graph_node include/physical_types.h /^struct s_pb_graph_node {$/;" s -s_pb_graph_node_power include/physical_types.h /^struct s_pb_graph_node_power {$/;" s -s_pb_graph_pin include/physical_types.h /^struct s_pb_graph_pin {$/;" s -s_pb_graph_pin_power include/physical_types.h /^struct s_pb_graph_pin_power {$/;" s -s_pb_type include/physical_types.h /^struct s_pb_type {$/;" s -s_pb_type_power include/physical_types.h /^struct s_pb_type_power {$/;" s -s_pin_to_pin_annotation include/physical_types.h /^struct s_pin_to_pin_annotation {$/;" s -s_port include/physical_types.h /^struct s_port {$/;" s -s_port_power include/physical_types.h /^struct s_port_power {$/;" s -s_power_arch include/physical_types.h /^struct s_power_arch {$/;" s -s_power_usage include/physical_types.h /^struct s_power_usage {$/;" s -s_reserved_syntax_char fpga_spice_include/spice_types.h /^struct s_reserved_syntax_char {$/;" s -s_scff_info fpga_spice_include/spice_types.h /^struct s_scff_info {$/;" s -s_segment_inf include/physical_types.h /^typedef struct s_segment_inf {$/;" s -s_spice fpga_spice_include/spice_types.h /^struct s_spice {$/;" s -s_spice_mc_params fpga_spice_include/spice_types.h /^struct s_spice_mc_params {$/;" s -s_spice_mc_variation_params fpga_spice_include/spice_types.h /^struct s_spice_mc_variation_params {$/;" s -s_spice_meas_params fpga_spice_include/spice_types.h /^struct s_spice_meas_params {$/;" s -s_spice_model fpga_spice_include/spice_types.h /^struct s_spice_model {$/;" s -s_spice_model_buffer fpga_spice_include/spice_types.h /^struct s_spice_model_buffer {$/;" s -s_spice_model_design_tech_info fpga_spice_include/spice_types.h /^struct s_spice_model_design_tech_info {$/;" s -s_spice_model_netlist fpga_spice_include/spice_types.h /^struct s_spice_model_netlist {$/;" s -s_spice_model_pass_gate_logic fpga_spice_include/spice_types.h /^struct s_spice_model_pass_gate_logic {$/;" s -s_spice_model_port fpga_spice_include/spice_types.h /^struct s_spice_model_port {$/;" s -s_spice_model_wire_param fpga_spice_include/spice_types.h /^struct s_spice_model_wire_param {$/;" s -s_spice_mux_arch fpga_spice_include/spice_types.h /^struct s_spice_mux_arch {$/;" s -s_spice_mux_model fpga_spice_include/spice_types.h /^struct s_spice_mux_model {$/;" s -s_spice_net_info fpga_spice_include/spice_types.h /^struct s_spice_net_info {$/;" s -s_spice_params fpga_spice_include/spice_types.h /^struct s_spice_params {$/;" s -s_spice_stimulate_params fpga_spice_include/spice_types.h /^struct s_spice_stimulate_params {$/;" s -s_spice_tech_lib fpga_spice_include/spice_types.h /^struct s_spice_tech_lib {$/;" s -s_spice_transistor_type fpga_spice_include/spice_types.h /^struct s_spice_transistor_type {$/;" s -s_spicetb_info fpga_spice_include/spice_types.h /^struct s_spicetb_info {$/;" s -s_sram_inf fpga_spice_include/spice_types.h /^struct s_sram_inf {$/;" s -s_sram_inf_orgz fpga_spice_include/spice_types.h /^struct s_sram_inf_orgz {$/;" s -s_sram_orgz_info fpga_spice_include/spice_types.h /^struct s_sram_orgz_info {$/;" s -s_standalone_sram_info fpga_spice_include/spice_types.h /^struct s_standalone_sram_info {$/;" s -s_switch_inf include/physical_types.h /^typedef struct s_switch_inf {$/;" s -s_swseg_pattern_inf include/physical_types.h /^struct s_swseg_pattern_inf {$/;" s -s_timing_inf include/physical_types.h /^typedef struct s_timing_inf {$/;" s -s_type_descriptor include/physical_types.h /^struct s_type_descriptor \/* TODO rename this. maybe physical type descriptor or complex logic block or physical logic block*\/$/;" s -sb include/physical_types.h /^ boolean *sb;$/;" m struct:s_segment_inf -sb_index_high fpga_spice_include/spice_types.h /^ int** sb_index_high;$/;" m struct:s_spice_model -sb_index_low fpga_spice_include/spice_types.h /^ int** sb_index_low;$/;" m struct:s_spice_model -sb_len include/physical_types.h /^ int sb_len;$/;" m struct:s_segment_inf -scaled_by_pin include/physical_types.h /^ t_pb_graph_pin * scaled_by_pin;$/;" m struct:s_pb_graph_pin_power -scaled_by_port include/physical_types.h /^ t_port * scaled_by_port;$/;" m struct:s_port_power -scaled_by_port_pin_idx include/physical_types.h /^ int scaled_by_port_pin_idx;$/;" m struct:s_port_power -scff_info fpga_spice_include/spice_types.h /^ t_scff_info* scff_info; \/* Only be allocated when orgz type is scan-chain *\/$/;" m struct:s_sram_orgz_info -scratch_pad include/physical_types.h /^ int scratch_pad; \/* temporary data structure useful to store traversal info *\/$/;" m struct:s_pb_graph_pin -search_in_int_list util.c /^t_linked_int* search_in_int_list(t_linked_int* int_list_head, $/;" f -search_llist_tail linkedlist.c /^t_llist* search_llist_tail(t_llist* head) {$/;" f -seg_direction_type include/physical_types.h /^ enum e_directionality seg_direction_type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_directionality -seg_length include/physical_types.h /^ int seg_length;$/;" m struct:s_swseg_pattern_inf -seg_switch include/physical_types.h /^ short seg_switch;$/;" m struct:s_segment_inf -sibling include/ezxml.h /^ ezxml_t sibling; \/* next tag with different name in same section and depth *\/$/;" m struct:ezxml -sim_clock_freq_slack fpga_spice_include/spice_types.h /^ float sim_clock_freq_slack;$/;" m struct:s_spice_stimulate_params -sim_num_clock_cycle fpga_spice_include/spice_types.h /^ int sim_num_clock_cycle; \/* Number of clock cycle in simulation *\/$/;" m struct:s_spice_meas_params -sim_temp fpga_spice_include/spice_types.h /^ int sim_temp; \/* Simulation Temperature*\/$/;" m struct:s_spice_params -size fpga_spice_include/spice_types.h /^ float size;$/;" m struct:s_spice_model_buffer -size fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_model_port -size fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_mux_model -size include/logic_types.h /^ int size; \/* maximum number of pins *\/$/;" m struct:s_model_ports -slew_fall fpga_spice_include/spice_types.h /^ float slew_fall;$/;" m struct:s_spice_net_info -slew_lower_thres_pct_fall fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_fall;$/;" m struct:s_spice_meas_params -slew_lower_thres_pct_rise fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_rise;$/;" m struct:s_spice_meas_params -slew_rise fpga_spice_include/spice_types.h /^ float slew_rise;$/;" m struct:s_spice_net_info -slew_upper_thres_pct_fall fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_fall;$/;" m struct:s_spice_meas_params -slew_upper_thres_pct_rise fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_rise;$/;" m struct:s_spice_meas_params -snprintf ezxml.c 57;" d file: -spice include/physical_types.h /^ t_spice* spice;$/;" m struct:s_arch -spice_model fpga_spice_include/spice_types.h /^ t_spice_model* spice_model; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz -spice_model fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_buffer -spice_model fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_pass_gate_logic -spice_model fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_port -spice_model fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_mux_model -spice_model include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_interconnect -spice_model include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_pb_type -spice_model include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_segment_inf -spice_model include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_switch_inf -spice_model_name fpga_spice_include/spice_types.h /^ char* spice_model_name; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz -spice_model_name fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_buffer -spice_model_name fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_pass_gate_logic -spice_model_name fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_port -spice_model_name include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_interconnect -spice_model_name include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_pb_type -spice_model_name include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_segment_inf -spice_model_name include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_switch_inf -spice_model_port include/physical_types.h /^ t_spice_model_port* spice_model_port;$/;" m struct:s_port -spice_models fpga_spice_include/spice_types.h /^ t_spice_model* spice_models;$/;" m struct:s_spice -spice_mux_arch fpga_spice_include/spice_types.h /^ t_spice_mux_arch* spice_mux_arch;$/;" m struct:s_spice_mux_model -spice_params fpga_spice_include/spice_types.h /^ t_spice_params spice_params;$/;" m struct:s_spice -spice_reserved fpga_spice_include/spice_types.h /^ boolean spice_reserved;$/;" m struct:s_reserved_syntax_char -spice_sram_inf_orgz fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* spice_sram_inf_orgz;$/;" m struct:s_sram_inf -spot_int_in_array util.c /^int spot_int_in_array(int array_len, int* array,$/;" f -sram_bit fpga_spice_include/spice_types.h /^ t_conf_bit* sram_bit;$/;" m struct:s_conf_bit_info -sram_inf include/physical_types.h /^ t_sram_inf sram_inf;$/;" m struct:s_arch -standalone include/ezxml.h /^ short standalone; \/* non-zero if *\/$/;" m struct:ezxml_root -standalone_sram_info fpga_spice_include/spice_types.h /^ t_standalone_sram_info* standalone_sram_info; \/* Only be allocated when orgz type is standalone *\/$/;" m struct:s_sram_orgz_info -start_col include/physical_types.h /^ int start_col;$/;" m struct:s_grid_loc_def -start_seg_switch include/arch_types_mrfpga.h /^ short start_seg_switch;$/;" m struct:s_arch_mrfpga -stimulate_params fpga_spice_include/spice_types.h /^ t_spice_stimulate_params stimulate_params;$/;" m struct:s_spice_params -structure fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_model_design_tech_info typeref:enum:s_spice_model_design_tech_info::e_spice_model_structure -structure fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_mux_arch typeref:enum:s_spice_mux_arch::e_spice_model_structure -structure include/physical_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_switch_inf typeref:enum:s_switch_inf::e_spice_model_structure -switch_num_level include/physical_types.h /^ int switch_num_level;$/;" m struct:s_switch_inf -swseg_patterns include/physical_types.h /^ t_swseg_pattern_inf* swseg_patterns;$/;" m struct:s_arch -syntax_char fpga_spice_include/spice_types.h /^ char syntax_char;$/;" m struct:s_reserved_syntax_char -t_arch include/physical_types.h /^typedef struct s_arch t_arch;$/;" t typeref:struct:s_arch -t_arch_mrfpga include/arch_types_mrfpga.h /^typedef struct s_arch_mrfpga t_arch_mrfpga;$/;" t typeref:struct:s_arch_mrfpga -t_buffer_inf include/arch_types_mrfpga.h /^typedef struct s_buffer_inf t_buffer_inf;$/;" t typeref:struct:s_buffer_inf -t_chan include/physical_types.h /^} t_chan;$/;" t typeref:struct:s_chan -t_chan_width_dist include/physical_types.h /^} t_chan_width_dist;$/;" t typeref:struct:s_chan_width_dist -t_chunk include/util.h /^} t_chunk;$/;" t typeref:struct:s_chunk -t_class include/physical_types.h /^typedef struct s_class t_class;$/;" t typeref:struct:s_class -t_clock_arch include/physical_types.h /^typedef struct s_clock_arch t_clock_arch;$/;" t typeref:struct:s_clock_arch -t_clock_network include/physical_types.h /^typedef struct s_clock_network t_clock_network;$/;" t typeref:struct:s_clock_network -t_cluster_placement_primitive include/cad_types.h /^} t_cluster_placement_primitive;$/;" t typeref:struct:s_cluster_placement_primitive -t_conf_bit fpga_spice_include/spice_types.h /^typedef struct s_conf_bit t_conf_bit;$/;" t typeref:struct:s_conf_bit -t_conf_bit_info fpga_spice_include/spice_types.h /^typedef struct s_conf_bit_info t_conf_bit_info;$/;" t typeref:struct:s_conf_bit_info -t_direct_inf include/physical_types.h /^} t_direct_inf;$/;" t typeref:struct:s_direct_inf -t_grid_loc_def include/physical_types.h /^} t_grid_loc_def;$/;" t typeref:struct:s_grid_loc_def -t_interconnect include/physical_types.h /^typedef struct s_interconnect t_interconnect;$/;" t typeref:struct:s_interconnect -t_interconnect_pins include/physical_types.h /^typedef struct s_interconnect_pins t_interconnect_pins;$/;" t typeref:struct:s_interconnect_pins -t_interconnect_power include/physical_types.h /^typedef struct s_interconnect_power t_interconnect_power;$/;" t typeref:struct:s_interconnect_power -t_ivec include/util.h /^} t_ivec;$/;" t typeref:struct:s_ivec -t_linked_int include/util.h /^} t_linked_int;$/;" t typeref:struct:s_linked_int -t_linked_vptr include/util.h /^} t_linked_vptr;$/;" t typeref:struct:s_linked_vptr -t_llist fpga_spice_include/linkedlist.h /^typedef struct s_llist t_llist;$/;" t typeref:struct:s_llist -t_mem_bank_info fpga_spice_include/spice_types.h /^typedef struct s_mem_bank_info t_mem_bank_info;$/;" t typeref:struct:s_mem_bank_info -t_memristor_inf include/arch_types_mrfpga.h /^typedef struct s_memristor_inf t_memristor_inf;$/;" t typeref:struct:s_memristor_inf -t_mode include/physical_types.h /^typedef struct s_mode t_mode;$/;" t typeref:struct:s_mode -t_mode_power include/physical_types.h /^typedef struct s_mode_power t_mode_power;$/;" t typeref:struct:s_mode_power -t_model include/logic_types.h /^} t_model;$/;" t typeref:struct:s_model -t_model_chain_pattern include/cad_types.h /^} t_model_chain_pattern;$/;" t typeref:struct:s_model_chain_pattern -t_model_ports include/logic_types.h /^} t_model_ports;$/;" t typeref:struct:s_model_ports -t_pack_pattern_block include/cad_types.h /^} t_pack_pattern_block;$/;" t typeref:struct:s_pack_pattern_block -t_pack_pattern_connections include/cad_types.h /^} t_pack_pattern_connections;$/;" t typeref:struct:s_pack_pattern_connections -t_pack_patterns include/cad_types.h /^} t_pack_patterns;$/;" t typeref:struct:s_pack_patterns -t_pb_graph_edge include/physical_types.h /^typedef struct s_pb_graph_edge t_pb_graph_edge;$/;" t typeref:struct:s_pb_graph_edge -t_pb_graph_node include/physical_types.h /^typedef struct s_pb_graph_node t_pb_graph_node;$/;" t typeref:struct:s_pb_graph_node -t_pb_graph_node_power include/physical_types.h /^typedef struct s_pb_graph_node_power t_pb_graph_node_power;$/;" t typeref:struct:s_pb_graph_node_power -t_pb_graph_pin include/physical_types.h /^typedef struct s_pb_graph_pin t_pb_graph_pin;$/;" t typeref:struct:s_pb_graph_pin -t_pb_graph_pin_power include/physical_types.h /^typedef struct s_pb_graph_pin_power t_pb_graph_pin_power;$/;" t typeref:struct:s_pb_graph_pin_power -t_pb_type include/physical_types.h /^typedef struct s_pb_type t_pb_type;$/;" t typeref:struct:s_pb_type -t_pb_type_power include/physical_types.h /^typedef struct s_pb_type_power t_pb_type_power;$/;" t typeref:struct:s_pb_type_power -t_pin_to_pin_annotation include/physical_types.h /^typedef struct s_pin_to_pin_annotation t_pin_to_pin_annotation;$/;" t typeref:struct:s_pin_to_pin_annotation -t_port include/physical_types.h /^typedef struct s_port t_port;$/;" t typeref:struct:s_port -t_port_power include/physical_types.h /^typedef struct s_port_power t_port_power;$/;" t typeref:struct:s_port_power -t_power_arch include/physical_types.h /^typedef struct s_power_arch t_power_arch;$/;" t typeref:struct:s_power_arch -t_power_estimation_method include/physical_types.h /^typedef enum e_power_estimation_method_ t_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ -t_power_usage include/physical_types.h /^typedef struct s_power_usage t_power_usage;$/;" t typeref:struct:s_power_usage -t_reserved_syntax_char fpga_spice_include/spice_types.h /^typedef struct s_reserved_syntax_char t_reserved_syntax_char;$/;" t typeref:struct:s_reserved_syntax_char -t_scff_info fpga_spice_include/spice_types.h /^typedef struct s_scff_info t_scff_info;$/;" t typeref:struct:s_scff_info -t_segment_inf include/physical_types.h /^} t_segment_inf;$/;" t typeref:struct:s_segment_inf -t_spice fpga_spice_include/spice_types.h /^typedef struct s_spice t_spice;$/;" t typeref:struct:s_spice -t_spice_mc_params fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_params t_spice_mc_params;$/;" t typeref:struct:s_spice_mc_params -t_spice_mc_variation_params fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_variation_params t_spice_mc_variation_params;$/;" t typeref:struct:s_spice_mc_variation_params -t_spice_meas_params fpga_spice_include/spice_types.h /^typedef struct s_spice_meas_params t_spice_meas_params;$/;" t typeref:struct:s_spice_meas_params -t_spice_model fpga_spice_include/spice_types.h /^typedef struct s_spice_model t_spice_model;$/;" t typeref:struct:s_spice_model -t_spice_model_buffer fpga_spice_include/spice_types.h /^typedef struct s_spice_model_buffer t_spice_model_buffer;$/;" t typeref:struct:s_spice_model_buffer -t_spice_model_design_tech_info fpga_spice_include/spice_types.h /^typedef struct s_spice_model_design_tech_info t_spice_model_design_tech_info;$/;" t typeref:struct:s_spice_model_design_tech_info -t_spice_model_netlist fpga_spice_include/spice_types.h /^typedef struct s_spice_model_netlist t_spice_model_netlist;$/;" t typeref:struct:s_spice_model_netlist -t_spice_model_pass_gate_logic fpga_spice_include/spice_types.h /^typedef struct s_spice_model_pass_gate_logic t_spice_model_pass_gate_logic;$/;" t typeref:struct:s_spice_model_pass_gate_logic -t_spice_model_port fpga_spice_include/spice_types.h /^typedef struct s_spice_model_port t_spice_model_port;$/;" t typeref:struct:s_spice_model_port -t_spice_model_wire_param fpga_spice_include/spice_types.h /^typedef struct s_spice_model_wire_param t_spice_model_wire_param;$/;" t typeref:struct:s_spice_model_wire_param -t_spice_mux_arch fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_arch t_spice_mux_arch;$/;" t typeref:struct:s_spice_mux_arch -t_spice_mux_model fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_model t_spice_mux_model;$/;" t typeref:struct:s_spice_mux_model -t_spice_net_info fpga_spice_include/spice_types.h /^typedef struct s_spice_net_info t_spice_net_info;$/;" t typeref:struct:s_spice_net_info -t_spice_params fpga_spice_include/spice_types.h /^typedef struct s_spice_params t_spice_params;$/;" t typeref:struct:s_spice_params -t_spice_stimulate_params fpga_spice_include/spice_types.h /^typedef struct s_spice_stimulate_params t_spice_stimulate_params;$/;" t typeref:struct:s_spice_stimulate_params -t_spice_tech_lib fpga_spice_include/spice_types.h /^typedef struct s_spice_tech_lib t_spice_tech_lib;$/;" t typeref:struct:s_spice_tech_lib -t_spice_transistor_type fpga_spice_include/spice_types.h /^typedef struct s_spice_transistor_type t_spice_transistor_type;$/;" t typeref:struct:s_spice_transistor_type -t_spicetb_info fpga_spice_include/spice_types.h /^typedef struct s_spicetb_info t_spicetb_info;$/;" t typeref:struct:s_spicetb_info -t_sram_inf fpga_spice_include/spice_types.h /^typedef struct s_sram_inf t_sram_inf;$/;" t typeref:struct:s_sram_inf -t_sram_inf_orgz fpga_spice_include/spice_types.h /^typedef struct s_sram_inf_orgz t_sram_inf_orgz;$/;" t typeref:struct:s_sram_inf_orgz -t_sram_orgz_info fpga_spice_include/spice_types.h /^typedef struct s_sram_orgz_info t_sram_orgz_info;$/;" t typeref:struct:s_sram_orgz_info -t_standalone_sram_info fpga_spice_include/spice_types.h /^typedef struct s_standalone_sram_info t_standalone_sram_info;$/;" t typeref:struct:s_standalone_sram_info -t_switch_block_type include/physical_types.h /^typedef enum e_switch_block_type t_switch_block_type;$/;" t typeref:enum:e_switch_block_type -t_switch_inf include/physical_types.h /^} t_switch_inf;$/;" t typeref:struct:s_switch_inf -t_swseg_pattern_inf include/physical_types.h /^typedef struct s_swseg_pattern_inf t_swseg_pattern_inf;$/;" t typeref:struct:s_swseg_pattern_inf -t_timing_inf include/physical_types.h /^} t_timing_inf;$/;" t typeref:struct:s_timing_inf -t_type_descriptor include/physical_types.h /^typedef struct s_type_descriptor t_type_descriptor;$/;" t typeref:struct:s_type_descriptor -t_type_ptr include/physical_types.h /^typedef const struct s_type_descriptor *t_type_ptr;$/;" t typeref:struct:s_type_descriptor -tap_buf_level fpga_spice_include/spice_types.h /^ int tap_buf_level;$/;" m struct:s_spice_model_buffer -tapered_buf fpga_spice_include/spice_types.h /^ int tapered_buf; \/*Valid only when this is a buffer*\/$/;" m struct:s_spice_model_buffer -tb_cnt fpga_spice_include/spice_types.h /^ int tb_cnt;$/;" m struct:s_spice_model -tb_name fpga_spice_include/spice_types.h /^ char* tb_name;$/;" m struct:s_spicetb_info -tech_comp include/arch_types_mrfpga.h /^ enum e_tech_comp tech_comp;$/;" m struct:s_arch_mrfpga typeref:enum:s_arch_mrfpga::e_tech_comp -tech_lib fpga_spice_include/spice_types.h /^ t_spice_tech_lib tech_lib;$/;" m struct:s_spice -temp_net_num include/physical_types.h /^ int temp_net_num;$/;" m struct:s_pb_graph_pin -temp_scratch_pad include/physical_types.h /^ void *temp_scratch_pad; \/* temporary data, useful for keeping track of things when traversing data structure *\/$/;" m struct:s_pb_graph_node -timing_analysis_enabled include/physical_types.h /^ boolean timing_analysis_enabled;$/;" m struct:s_timing_inf -to_block include/cad_types.h /^ t_pack_pattern_block *to_block;$/;" m struct:s_pack_pattern_connections -to_pin include/cad_types.h /^ t_pb_graph_pin *to_pin;$/;" m struct:s_pack_pattern_connections -to_pin include/physical_types.h /^ char *to_pin;$/;" m struct:s_direct_inf -total_pb_pins include/physical_types.h /^ int total_pb_pins; \/* only valid for top-level *\/$/;" m struct:s_pb_graph_node -transistor_cnt include/physical_types.h /^ float transistor_cnt;$/;" m struct:s_interconnect_power -transistor_cnt_buffers include/physical_types.h /^ float transistor_cnt_buffers;$/;" m struct:s_pb_graph_node_power -transistor_cnt_interc include/physical_types.h /^ float transistor_cnt_interc; \/* Total transistor size of the interconnect in this pb *\/$/;" m struct:s_pb_graph_node_power -transistor_cnt_pb_children include/physical_types.h /^ float transistor_cnt_pb_children; \/* Total transistor size of this pb *\/$/;" m struct:s_pb_graph_node_power -transistor_type fpga_spice_include/spice_types.h /^ char* transistor_type;$/;" m struct:s_spice_tech_lib -transistor_types fpga_spice_include/spice_types.h /^ t_spice_transistor_type* transistor_types;$/;" m struct:s_spice_tech_lib -transistors_per_SRAM_bit include/physical_types.h /^ float transistors_per_SRAM_bit;$/;" m struct:s_power_arch -tsu_tco include/physical_types.h /^ float tsu_tco; \/* For sequential logic elements, this is the setup time (if input) or clock-to-q time (if output) *\/$/;" m struct:s_pb_graph_pin -txt include/ezxml.h /^ char *txt; \/* tag character content, empty string if none *\/$/;" m struct:ezxml -type fpga_spice_include/spice_types.h /^ enum e_spice_model_buffer_type type;$/;" m struct:s_spice_model_buffer typeref:enum:s_spice_model_buffer::e_spice_model_buffer_type -type fpga_spice_include/spice_types.h /^ enum e_spice_model_pass_gate_logic_type type;$/;" m struct:s_spice_model_pass_gate_logic typeref:enum:s_spice_model_pass_gate_logic::e_spice_model_pass_gate_logic_type -type fpga_spice_include/spice_types.h /^ enum e_spice_model_port_type type;$/;" m struct:s_spice_model_port typeref:enum:s_spice_model_port::e_spice_model_port_type -type fpga_spice_include/spice_types.h /^ enum e_spice_model_type type;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_type -type fpga_spice_include/spice_types.h /^ enum e_spice_tech_lib_type type;$/;" m struct:s_spice_tech_lib typeref:enum:s_spice_tech_lib::e_spice_tech_lib_type -type fpga_spice_include/spice_types.h /^ enum e_spice_trans_type type;$/;" m struct:s_spice_transistor_type typeref:enum:s_spice_transistor_type::e_spice_trans_type -type fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_inf_orgz typeref:enum:s_sram_inf_orgz::e_sram_orgz -type fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_orgz_info typeref:enum:s_sram_orgz_info::e_sram_orgz -type fpga_spice_include/spice_types.h /^ enum e_wire_model_type type;$/;" m struct:s_spice_model_wire_param typeref:enum:s_spice_model_wire_param::e_wire_model_type -type include/physical_types.h /^ enum PORTS type;$/;" m struct:s_port typeref:enum:s_port::PORTS -type include/physical_types.h /^ enum e_interconnect type;$/;" m struct:s_interconnect typeref:enum:s_interconnect::e_interconnect -type include/physical_types.h /^ enum e_pb_graph_pin_type type; \/* Is a sequential logic element (TRUE), inpad\/outpad (TRUE), or neither (FALSE) *\/$/;" m struct:s_pb_graph_pin typeref:enum:s_pb_graph_pin::e_pb_graph_pin_type -type include/physical_types.h /^ enum e_pin_to_pin_annotation_type type;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_type -type include/physical_types.h /^ enum e_pin_type type;$/;" m struct:s_class typeref:enum:s_class::e_pin_type -type include/physical_types.h /^ enum e_stat type;$/;" m struct:s_chan typeref:enum:s_chan::e_stat -type include/physical_types.h /^ char* type;$/;" m struct:s_switch_inf -type include/physical_types.h /^ enum e_swseg_pattern_type type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_swseg_pattern_type -u include/ezxml.h /^ char *u; \/* UTF-8 conversion of string if original was UTF-16 *\/$/;" m struct:ezxml_root -unbuf_switch include/physical_types.h /^ short unbuf_switch;$/;" m struct:s_swseg_pattern_inf -used include/logic_types.h /^ int used;$/;" m struct:s_model -val fpga_spice_include/spice_types.h /^ int val; \/* binary value to be writtent: either 0 or 1 *\/$/;" m struct:s_conf_bit -valid include/cad_types.h /^ boolean valid;$/;" m struct:s_cluster_placement_primitive -value include/physical_types.h /^ char ** value; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation -variation_on fpga_spice_include/spice_types.h /^ boolean variation_on;$/;" m struct:s_spice_mc_variation_params -verilog_netlist fpga_spice_include/spice_types.h /^ char* verilog_netlist; \/* Verilog netlist provided by user *\/$/;" m struct:s_spice_model -verilog_reserved fpga_spice_include/spice_types.h /^ boolean verilog_reserved;$/;" m struct:s_reserved_syntax_char -verilog_sram_inf_orgz fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* verilog_sram_inf_orgz;$/;" m struct:s_sram_inf -vpr_crit_path_delay fpga_spice_include/spice_types.h /^ float vpr_crit_path_delay; \/* Reference operation clock frequency *\/$/;" m struct:s_spice_stimulate_params -vpr_printf util.c /^messagelogger vpr_printf = PrintHandlerMessage;$/;" v -width include/physical_types.h /^ float width;$/;" m struct:s_chan -wire include/physical_types.h /^ } wire;$/;" m struct:s_port_power typeref:union:s_port_power::__anon3 -wire_buffer_inf include/arch_types_mrfpga.h /^ t_buffer_inf wire_buffer_inf;$/;" m struct:s_arch_mrfpga -wire_param fpga_spice_include/spice_types.h /^ t_spice_model_wire_param* wire_param;$/;" m struct:s_spice_model -wire_switch include/physical_types.h /^ short wire_switch;$/;" m struct:s_segment_inf -wire_type include/physical_types.h /^ e_power_wire_type wire_type;$/;" m struct:s_port_power -wl fpga_spice_include/spice_types.h /^ t_conf_bit* wl;$/;" m struct:s_conf_bit_info -wprog_reset_nmos fpga_spice_include/spice_types.h /^ float wprog_reset_nmos;$/;" m struct:s_spice_model_design_tech_info -wprog_reset_pmos fpga_spice_include/spice_types.h /^ float wprog_reset_pmos;$/;" m struct:s_spice_model_design_tech_info -wprog_set_nmos fpga_spice_include/spice_types.h /^ float wprog_set_nmos;$/;" m struct:s_spice_model_design_tech_info -wprog_set_pmos fpga_spice_include/spice_types.h /^ float wprog_set_pmos;$/;" m struct:s_spice_model_design_tech_info -write ezxml.c 60;" d file: -x_offset include/physical_types.h /^ int x_offset;$/;" m struct:s_direct_inf -xml include/ezxml.h /^ struct ezxml xml; \/* is a super-struct built on top of ezxml struct *\/$/;" m struct:ezxml_root typeref:struct:ezxml_root::ezxml -xpeak include/physical_types.h /^ float xpeak;$/;" m struct:s_chan -y_offset include/physical_types.h /^ int y_offset;$/;" m struct:s_direct_inf -z_offset include/physical_types.h /^ int z_offset;$/;" m struct:s_direct_inf +ABSOLUTE SRC/include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type +ARCH_TYPES_H SRC/include/arch_types.h 9;" d +Aspect SRC/include/physical_types.h /^ float Aspect;$/;" m struct:s_clb_grid +BEST_CORNER SRC/fpga_spice_include/spice_types.h /^ BEST_CORNER,$/;" e enum:e_process_corner +BI_DIRECTIONAL SRC/include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality +BOTTOM SRC/include/sides.h /^ BOTTOM = 2, $/;" e enum:e_side +BOUNDARY SRC/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +BUFSIZE SRC/include/util.h 23;" d +C SRC/include/arch_types_mrfpga.h /^ float C; $/;" m struct:s_memristor_inf +C SRC/include/arch_types_mrfpga.h /^ float C;$/;" m struct:s_buffer_inf +C SRC/include/physical_types.h /^ float C;$/;" m union:s_port_power::__anon3 +CAD_TYPES_H SRC/include/cad_types.h 5;" d +CHECK_RAND SRC/util.c 734;" d file: +CHUNK_SIZE SRC/util.c 208;" d file: +COL_REL SRC/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +COL_REPEAT SRC/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +COMPLETE_INTERC SRC/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect +CONV SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +C_internal SRC/include/physical_types.h /^ float C_internal; \/*Internal capacitance of the pb *\/$/;" m struct:s_pb_type_power +C_ipin_cblock SRC/include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_arch +C_ipin_cblock SRC/include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_timing_inf +C_wire SRC/include/physical_types.h /^ float C_wire; \/* Wire capacitance (per meter) *\/$/;" m struct:s_clock_network +C_wire SRC/include/physical_types.h /^ float C_wire;$/;" m struct:s_pb_graph_pin_power +C_wire_local SRC/include/physical_types.h /^ float C_wire_local; \/* Capacitance of local interconnect (per meter) *\/$/;" m struct:s_power_arch +Chans SRC/include/physical_types.h /^ t_chan_width_dist Chans;$/;" m struct:s_arch +CheckElement SRC/read_xml_util.c /^void CheckElement(INP ezxml_t Node, INP const char *Name) {$/;" f +Cin SRC/include/physical_types.h /^ float Cin;$/;" m struct:s_switch_inf +Cmetal SRC/include/physical_types.h /^ float Cmetal;$/;" m struct:s_segment_inf +CountChildren SRC/read_xml_util.c /^extern int CountChildren(INP ezxml_t Node, INP const char *Name,$/;" f +CountTokens SRC/ReadLine.c /^int CountTokens(INP char **Tokens) {$/;" f +CountTokensInString SRC/read_xml_util.c /^extern void CountTokensInString(INP const char *Str, OUTP int *Num,$/;" f +Cout SRC/include/physical_types.h /^ float Cout;$/;" m struct:s_switch_inf +CreateModelLibrary SRC/read_xml_arch_file.c /^static void CreateModelLibrary(OUTP struct s_arch *arch) {$/;" f file: +Cseg_global SRC/include/arch_types_mrfpga.h /^ float Cseg_global;$/;" m struct:s_arch_mrfpga +DELTA SRC/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +DIRECT_INTERC SRC/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect +DRIVER SRC/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type +Directs SRC/include/physical_types.h /^ t_direct_inf *Directs;$/;" m struct:s_arch +EMPTY_TYPE SRC/read_xml_arch_file.c /^static t_type_ptr EMPTY_TYPE = NULL;$/;" v file: +EMPTY_TYPE_INDEX SRC/include/read_xml_arch_file.h 15;" d +ERRTAG SRC/include/util.h 26;" d +ERR_PORT SRC/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +EZXML_BUFSIZE SRC/include/ezxml.h 37;" d +EZXML_DUP SRC/include/ezxml.h 40;" d +EZXML_ERRL SRC/include/ezxml.h 41;" d +EZXML_NAMEM SRC/include/ezxml.h 38;" d +EZXML_NIL SRC/ezxml.c /^char *EZXML_NIL[] = { NULL }; \/* empty, null terminated array of strings *\/$/;" v +EZXML_NOMMAP SRC/ezxml.c 26;" d file: +EZXML_TXTM SRC/include/ezxml.h 39;" d +EZXML_WS SRC/ezxml.c 64;" d file: +E_ANNOT_PIN_TO_PIN_CAPACITANCE SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE,$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_CAPACITANCE_C SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE_C = 0$/;" e enum:e_pin_to_pin_capacitance_annotations +E_ANNOT_PIN_TO_PIN_CONSTANT SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format +E_ANNOT_PIN_TO_PIN_DELAY SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY = 0,$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_MAX SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MAX,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_MIN SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MIN = 0,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_THOLD SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_THOLD$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_TSETUP SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_TSETUP,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_MATRIX SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format +E_ANNOT_PIN_TO_PIN_MODE_SELECT SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME = 0$/;" e enum:e_pin_to_pin_mode_select_annotations +E_ANNOT_PIN_TO_PIN_PACK_PATTERN SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN,$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME = 0$/;" e enum:e_pin_to_pin_pack_pattern_annotations +E_CUSTOM_PIN_DISTR SRC/include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr +E_SPREAD_PIN_DISTR SRC/include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr +EchoArch SRC/read_xml_arch_file.c /^void EchoArch(INP const char *EchoFile, INP const t_type_descriptor * Types,$/;" f +FALSE SRC/include/util.h /^ FALSE, TRUE$/;" e enum:__anon4 +FC_ABS SRC/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: +FC_FRAC SRC/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: +FC_FULL SRC/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: +FF_FE SRC/fpga_spice_include/spice_types.h /^ FF_RE, FF_FE$/;" e enum:e_spice_ff_trigger_type +FF_RE SRC/fpga_spice_include/spice_types.h /^ FF_RE, FF_FE$/;" e enum:e_spice_ff_trigger_type +FF_size SRC/include/physical_types.h /^ float FF_size;$/;" m struct:s_power_arch +FILL SRC/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +FILL_TYPE SRC/read_xml_arch_file.c /^static t_type_ptr FILL_TYPE = NULL;$/;" v file: +FRACTIONAL SRC/include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type +FRAGMENT_THRESHOLD SRC/util.c 209;" d file: +FULL SRC/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +Fc SRC/include/physical_types.h /^ float *Fc; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +Fc_type SRC/read_xml_arch_file.c /^enum Fc_type {$/;" g file: +FindElement SRC/read_xml_util.c /^ezxml_t FindElement(INP ezxml_t Parent, INP const char *Name,$/;" f +FindFirstElement SRC/read_xml_util.c /^ezxml_t FindFirstElement(INP ezxml_t Parent, INP const char *Name,$/;" f +FindProperty SRC/read_xml_util.c /^FindProperty(INP ezxml_t Parent, INP const char *Name, INP boolean Required) {$/;" f +FreeNode SRC/read_xml_util.c /^void FreeNode(INOUTP ezxml_t Node) {$/;" f +FreeSpice SRC/read_xml_spice_util.c /^void FreeSpice(t_spice* spice) {$/;" f +FreeSpiceMeasParams SRC/read_xml_spice_util.c /^void FreeSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f +FreeSpiceModel SRC/read_xml_spice_util.c /^void FreeSpiceModel(t_spice_model* spice_model) {$/;" f +FreeSpiceModelBuffer SRC/read_xml_spice_util.c /^void FreeSpiceModelBuffer(t_spice_model_buffer* spice_model_buffer) {$/;" f +FreeSpiceModelNetlist SRC/read_xml_spice_util.c /^void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist) {$/;" f +FreeSpiceModelPassGateLogic SRC/read_xml_spice_util.c /^void FreeSpiceModelPassGateLogic(t_spice_model_pass_gate_logic* spice_model_pass_gate_logic) {$/;" f +FreeSpiceModelPort SRC/read_xml_spice_util.c /^void FreeSpiceModelPort(t_spice_model_port* spice_model_port) {$/;" f +FreeSpiceModelWireParam SRC/read_xml_spice_util.c /^void FreeSpiceModelWireParam(t_spice_model_wire_param* spice_model_wire_param) {$/;" f +FreeSpiceMonteCarloParams SRC/read_xml_spice_util.c /^void FreeSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f +FreeSpiceMuxArch SRC/read_xml_spice_util.c /^void FreeSpiceMuxArch(t_spice_mux_arch* spice_mux_arch) {$/;" f +FreeSpiceParams SRC/read_xml_spice_util.c /^void FreeSpiceParams(t_spice_params* params) {$/;" f +FreeSpiceStimulateParams SRC/read_xml_spice_util.c /^void FreeSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f +FreeSpiceVariationParams SRC/read_xml_spice_util.c /^void FreeSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f +FreeSramInf SRC/read_xml_spice_util.c /^void FreeSramInf(t_sram_inf* sram_inf) {$/;" f +FreeSramInfOrgz SRC/read_xml_spice_util.c /^void FreeSramInfOrgz(t_sram_inf_orgz* sram_inf_orgz) {$/;" f +FreeTokens SRC/ReadLine.c /^void FreeTokens(INOUTP char ***TokensPtr) {$/;" f +Fs SRC/include/physical_types.h /^ int Fs;$/;" m struct:s_arch +GAUSSIAN SRC/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +GetBooleanProperty SRC/read_xml_util.c /^extern boolean GetBooleanProperty(INP ezxml_t Parent, INP char *Name,$/;" f +GetFloatProperty SRC/read_xml_util.c /^extern float GetFloatProperty(INP ezxml_t Parent, INP char *Name,$/;" f +GetIntProperty SRC/read_xml_util.c /^extern int GetIntProperty(INP ezxml_t Parent, INP char *Name,$/;" f +GetNodeTokens SRC/read_xml_util.c /^GetNodeTokens(INP ezxml_t Node) {$/;" f +H SRC/include/physical_types.h /^ int H;$/;" m struct:s_clb_grid +IA SRC/util.c 731;" d file: +IC SRC/util.c 732;" d file: +IM SRC/util.c 733;" d file: +INOUTP SRC/include/util.h 21;" d +INOUT_PORT SRC/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +INP SRC/include/util.h 19;" d +INPUT2INPUT_INTERC SRC/fpga_spice_include/spice_types.h /^ INPUT2INPUT_INTERC, $/;" e enum:e_spice_pin2pin_interc_type +IN_PORT SRC/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +IO_TYPE SRC/read_xml_arch_file.c /^static t_type_ptr IO_TYPE = NULL;$/;" v file: +IO_TYPE_INDEX SRC/include/read_xml_arch_file.h 16;" d +InitSpice SRC/read_xml_spice_util.c /^void InitSpice(t_spice* spice) {$/;" f +InitSpiceMeasParams SRC/read_xml_spice_util.c /^void InitSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f +InitSpiceMonteCarloParams SRC/read_xml_spice_util.c /^void InitSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f +InitSpiceParams SRC/read_xml_spice_util.c /^void InitSpiceParams(t_spice_params* params) {$/;" f +InitSpiceStimulateParams SRC/read_xml_spice_util.c /^void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f +InitSpiceVariationParams SRC/read_xml_spice_util.c /^void InitSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f +IsAuto SRC/include/physical_types.h /^ boolean IsAuto;$/;" m struct:s_clb_grid +IsWhitespace SRC/read_xml_util.c /^boolean IsWhitespace(char c) {$/;" f +LATCH_CLASS SRC/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +LEFT SRC/include/sides.h /^ LEFT = 3,$/;" e enum:e_side +LINKEDLIST_H SRC/fpga_spice_include/linkedlist.h 2;" d +LOGIC_TYPES_H SRC/include/logic_types.h 10;" d +LUT_CLASS SRC/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +LUT_transistor_size SRC/include/physical_types.h /^ float LUT_transistor_size;$/;" m struct:s_power_arch +LookaheadNodeTokens SRC/read_xml_util.c /^LookaheadNodeTokens(INP ezxml_t Node) {$/;" f +MAX_CHANNEL_WIDTH SRC/include/arch_types.h 25;" d +MEMORY_CLASS SRC/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +MONO SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +MUX_INTERC SRC/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect +MY_FREE_FWD_H SRC/fpga_spice_include/my_free_fwd.h 2;" d +NEM SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +NUM_MODELS_IN_LIBRARY SRC/include/read_xml_arch_file.h 14;" d +NUM_SIDES SRC/include/sides.h /^ NUM_SIDES$/;" e enum:e_side +OPEN SRC/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type +OUTP SRC/include/util.h 20;" d +OUTPUT2OUTPUT_INTERC SRC/fpga_spice_include/spice_types.h /^ OUTPUT2OUTPUT_INTERC$/;" e enum:e_spice_pin2pin_interc_type +OUT_PORT SRC/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +PB_PIN_CLOCK SRC/include/physical_types.h /^ PB_PIN_CLOCK$/;" e enum:e_pb_graph_pin_type +PB_PIN_INPAD SRC/include/physical_types.h /^ PB_PIN_INPAD,$/;" e enum:e_pb_graph_pin_type +PB_PIN_INPUT SRC/include/physical_types.h /^ PB_PIN_INPUT,$/;" e enum:e_pb_graph_pin_type +PB_PIN_NORMAL SRC/include/physical_types.h /^ PB_PIN_NORMAL = 0,$/;" e enum:e_pb_graph_pin_type +PB_PIN_OUTPAD SRC/include/physical_types.h /^ PB_PIN_OUTPAD,$/;" e enum:e_pb_graph_pin_type +PB_PIN_OUTPUT SRC/include/physical_types.h /^ PB_PIN_OUTPUT,$/;" e enum:e_pb_graph_pin_type +PB_PIN_SEQUENTIAL SRC/include/physical_types.h /^ PB_PIN_SEQUENTIAL,$/;" e enum:e_pb_graph_pin_type +PB_PIN_TERMINAL SRC/include/physical_types.h /^ PB_PIN_TERMINAL,$/;" e enum:e_pb_graph_pin_type +PCRAM_Pierre SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +PCRAM_Xie SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +PHYSICAL_TYPES_H SRC/include/physical_types.h 27;" d +PORTS SRC/include/logic_types.h /^enum PORTS {$/;" g +POWER_BUFFER_TYPE_ABSOLUTE_SIZE SRC/include/physical_types.h /^ POWER_BUFFER_TYPE_ABSOLUTE_SIZE$/;" e enum:__anon2 +POWER_BUFFER_TYPE_AUTO SRC/include/physical_types.h /^ POWER_BUFFER_TYPE_AUTO,$/;" e enum:__anon2 +POWER_BUFFER_TYPE_NONE SRC/include/physical_types.h /^ POWER_BUFFER_TYPE_NONE,$/;" e enum:__anon2 +POWER_BUFFER_TYPE_UNDEFINED SRC/include/physical_types.h /^ POWER_BUFFER_TYPE_UNDEFINED = 0,$/;" e enum:__anon2 +POWER_METHOD_ABSOLUTE SRC/include/physical_types.h /^ POWER_METHOD_ABSOLUTE \/* Dynamic: Aboslute, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_AUTO_SIZES SRC/include/physical_types.h /^ POWER_METHOD_AUTO_SIZES, \/* Transistor-level, auto-sized buffers\/wires *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_C_INTERNAL SRC/include/physical_types.h /^ POWER_METHOD_C_INTERNAL, \/* Dynamic: Equiv. Internal capacitance, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_IGNORE SRC/include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_SPECIFY_SIZES SRC/include/physical_types.h /^ POWER_METHOD_SPECIFY_SIZES, \/* Transistor-level, user-specified buffers\/wires *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_SUM_OF_CHILDREN SRC/include/physical_types.h /^ POWER_METHOD_SUM_OF_CHILDREN, \/* Ignore power of this PB, but consider children *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_TOGGLE_PINS SRC/include/physical_types.h /^ POWER_METHOD_TOGGLE_PINS, \/* Dynamic: Energy per pin toggle, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_UNDEFINED SRC/include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ +POWER_WIRE_TYPE_ABSOLUTE_LENGTH SRC/include/physical_types.h /^ POWER_WIRE_TYPE_ABSOLUTE_LENGTH,$/;" e enum:__anon1 +POWER_WIRE_TYPE_AUTO SRC/include/physical_types.h /^ POWER_WIRE_TYPE_AUTO$/;" e enum:__anon1 +POWER_WIRE_TYPE_C SRC/include/physical_types.h /^ POWER_WIRE_TYPE_C,$/;" e enum:__anon1 +POWER_WIRE_TYPE_IGNORED SRC/include/physical_types.h /^ POWER_WIRE_TYPE_IGNORED,$/;" e enum:__anon1 +POWER_WIRE_TYPE_RELATIVE_LENGTH SRC/include/physical_types.h /^ POWER_WIRE_TYPE_RELATIVE_LENGTH,$/;" e enum:__anon1 +POWER_WIRE_TYPE_UNDEFINED SRC/include/physical_types.h /^ POWER_WIRE_TYPE_UNDEFINED = 0,$/;" e enum:__anon1 +PULSE SRC/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +PrintPb_types_rec SRC/read_xml_arch_file.c /^static void PrintPb_types_rec(INP FILE * Echo, INP const t_pb_type * pb_type,$/;" f file: +ProcessCB_SB SRC/read_xml_arch_file.c /^static void ProcessCB_SB(INOUTP ezxml_t Node, INOUTP boolean * list,$/;" f file: +ProcessChanWidthDistr SRC/read_xml_arch_file.c /^static void ProcessChanWidthDistr(INOUTP ezxml_t Node,$/;" f file: +ProcessChanWidthDistrDir SRC/read_xml_arch_file.c /^static void ProcessChanWidthDistrDir(INOUTP ezxml_t Node, OUTP t_chan * chan) {$/;" f file: +ProcessClocks SRC/read_xml_arch_file.c /^static void ProcessClocks(ezxml_t Parent, t_clock_arch * clocks) {$/;" f file: +ProcessComplexBlockProps SRC/read_xml_arch_file.c /^static void ProcessComplexBlockProps(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: +ProcessComplexBlocks SRC/read_xml_arch_file.c /^static void ProcessComplexBlocks(INOUTP ezxml_t Node,$/;" f file: +ProcessDevice SRC/read_xml_arch_file.c /^static void ProcessDevice(INOUTP ezxml_t Node, OUTP struct s_arch *arch,$/;" f file: +ProcessDirects SRC/read_xml_arch_file.c /^static void ProcessDirects(INOUTP ezxml_t Parent, OUTP t_direct_inf **Directs,$/;" f file: +ProcessInterconnect SRC/read_xml_arch_file.c /^static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {$/;" f file: +ProcessLayout SRC/read_xml_arch_file.c /^static void ProcessLayout(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: +ProcessLutClass SRC/read_xml_arch_file.c /^void ProcessLutClass(INOUTP t_pb_type *lut_pb_type) {$/;" f +ProcessMemoryClass SRC/read_xml_arch_file.c /^static void ProcessMemoryClass(INOUTP t_pb_type *mem_pb_type) {$/;" f file: +ProcessMode SRC/read_xml_arch_file.c /^static void ProcessMode(INOUTP ezxml_t Parent, t_mode * mode,$/;" f file: +ProcessModels SRC/read_xml_arch_file.c /^static void ProcessModels(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: +ProcessMrFPGATiming SRC/read_xml_mrfpga.c /^void ProcessMrFPGATiming(INOUTP ezxml_t Cur, $/;" f +ProcessPb_Type SRC/read_xml_arch_file.c /^static void ProcessPb_Type(INOUTP ezxml_t Parent, t_pb_type * pb_type,$/;" f file: +ProcessPb_TypePort SRC/read_xml_arch_file.c /^static void ProcessPb_TypePort(INOUTP ezxml_t Parent, t_port * port,$/;" f file: +ProcessPb_TypePort_Power SRC/read_xml_arch_file.c /^static void ProcessPb_TypePort_Power(ezxml_t Parent, t_port * port,$/;" f file: +ProcessPb_TypePower SRC/read_xml_arch_file.c /^static void ProcessPb_TypePower(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: +ProcessPb_TypePowerEstMethod SRC/read_xml_arch_file.c /^static void ProcessPb_TypePowerEstMethod(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: +ProcessPb_TypePowerPinToggle SRC/read_xml_arch_file.c /^static void ProcessPb_TypePowerPinToggle(ezxml_t parent, t_pb_type * pb_type) {$/;" f file: +ProcessPinToPinAnnotations SRC/read_xml_arch_file.c /^static void ProcessPinToPinAnnotations(ezxml_t Parent,$/;" f file: +ProcessPower SRC/read_xml_arch_file.c /^static void ProcessPower( INOUTP ezxml_t parent,$/;" f file: +ProcessSegments SRC/read_xml_arch_file.c /^static void ProcessSegments(INOUTP ezxml_t Parent,$/;" f file: +ProcessSpiceMCVariationParams SRC/read_xml_spice.c /^static void ProcessSpiceMCVariationParams(ezxml_t Parent,$/;" f file: +ProcessSpiceMeasParams SRC/read_xml_spice.c /^static void ProcessSpiceMeasParams(ezxml_t Parent,$/;" f file: +ProcessSpiceModel SRC/read_xml_spice.c /^static void ProcessSpiceModel(ezxml_t Parent,$/;" f file: +ProcessSpiceModelBuffer SRC/read_xml_spice.c /^static void ProcessSpiceModelBuffer(ezxml_t Node,$/;" f file: +ProcessSpiceModelDelayInfo SRC/read_xml_spice.c /^void ProcessSpiceModelDelayInfo(ezxml_t Node, $/;" f file: +ProcessSpiceModelGate SRC/read_xml_spice.c /^static void ProcessSpiceModelGate(ezxml_t Node, $/;" f file: +ProcessSpiceModelLUT SRC/read_xml_spice.c /^static void ProcessSpiceModelLUT(ezxml_t Node, $/;" f file: +ProcessSpiceModelMUX SRC/read_xml_spice.c /^static void ProcessSpiceModelMUX(ezxml_t Node, $/;" f file: +ProcessSpiceModelPassGateLogic SRC/read_xml_spice.c /^static void ProcessSpiceModelPassGateLogic(ezxml_t Node,$/;" f file: +ProcessSpiceModelPort SRC/read_xml_spice.c /^static void ProcessSpiceModelPort(ezxml_t Node,$/;" f file: +ProcessSpiceModelPortLutOutputMask SRC/read_xml_spice.c /^static void ProcessSpiceModelPortLutOutputMask(ezxml_t Node,$/;" f file: +ProcessSpiceModelRRAM SRC/read_xml_spice.c /^static void ProcessSpiceModelRRAM(ezxml_t Node, $/;" f file: +ProcessSpiceModelWireParam SRC/read_xml_spice.c /^static void ProcessSpiceModelWireParam(ezxml_t Parent,$/;" f file: +ProcessSpiceMonteCarloParams SRC/read_xml_spice.c /^static void ProcessSpiceMonteCarloParams(ezxml_t Parent, $/;" f file: +ProcessSpiceParams SRC/read_xml_spice.c /^static void ProcessSpiceParams(ezxml_t Parent,$/;" f file: +ProcessSpiceSRAM SRC/read_xml_spice.c /^void ProcessSpiceSRAM(INOUTP ezxml_t Node, OUTP struct s_arch* arch) {$/;" f +ProcessSpiceSRAMOrganization SRC/read_xml_spice.c /^void ProcessSpiceSRAMOrganization(INOUTP ezxml_t Node, $/;" f file: +ProcessSpiceSettings SRC/read_xml_spice.c /^void ProcessSpiceSettings(ezxml_t Parent,$/;" f +ProcessSpiceStimulateParams SRC/read_xml_spice.c /^static void ProcessSpiceStimulateParams(ezxml_t Parent,$/;" f file: +ProcessSpiceStimulateParamsRiseFall SRC/read_xml_spice.c /^static void ProcessSpiceStimulateParamsRiseFall(ezxml_t Parent,$/;" f file: +ProcessSpiceTechLibTransistors SRC/read_xml_spice.c /^static void ProcessSpiceTechLibTransistors(ezxml_t Parent,$/;" f file: +ProcessSpiceTransistorType SRC/read_xml_spice.c /^static void ProcessSpiceTransistorType(ezxml_t Parent,$/;" f file: +ProcessSwitchSegmentPatterns SRC/read_xml_arch_file.c /^static void ProcessSwitchSegmentPatterns(INOUTP ezxml_t Parent,$/;" f file: +ProcessSwitches SRC/read_xml_arch_file.c /^static void ProcessSwitches(INOUTP ezxml_t Parent,$/;" f file: +ProcessTechComp SRC/read_xml_mrfpga.c /^ProcessTechComp(INOUTP ezxml_t Node,$/;" f +ProcessTechHack SRC/read_xml_mrfpga.c /^ProcessTechHack(INOUTP ezxml_t Node,$/;" f +ProcessTechnology SRC/read_xml_mrfpga.c /^ProcessTechnology(INOUTP ezxml_t Node,$/;" f +ProcessWireBuffer SRC/read_xml_mrfpga.c /^ProcessWireBuffer(INOUTP ezxml_t Node,$/;" f +Process_Fc SRC/read_xml_arch_file.c /^static void Process_Fc(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: +ProcessmrFPGA SRC/read_xml_mrfpga.c /^ProcessmrFPGA(INOUTP ezxml_t Node,$/;" f +R SRC/include/arch_types_mrfpga.h /^ float R; $/;" m struct:s_memristor_inf +R SRC/include/arch_types_mrfpga.h /^ float R;$/;" m struct:s_buffer_inf +R SRC/include/physical_types.h /^ float R;$/;" m struct:s_switch_inf +READLINE_H SRC/include/ReadLine.h 2;" d +READ_XML_ARCH_FILE_H SRC/include/read_xml_arch_file.h 2;" d +READ_XML_SPICE_UTIL_H SRC/fpga_spice_include/read_xml_spice_util.h 2;" d +READ_XML_UTIL_H SRC/include/read_xml_util.h 2;" d +RECEIVER SRC/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type +RIGHT SRC/include/sides.h /^ RIGHT = 1, $/;" e enum:e_side +R_minW_nmos SRC/include/physical_types.h /^ float R_minW_nmos;$/;" m struct:s_arch +R_minW_pmos SRC/include/physical_types.h /^ float R_minW_pmos;$/;" m struct:s_arch +R_opin_cblock SRC/include/arch_types_mrfpga.h /^ float R_opin_cblock;$/;" m struct:s_arch_mrfpga +R_opin_cblock SRC/include/physical_types.h /^ float R_opin_cblock;$/;" m struct:s_timing_inf +ReadLineTokens SRC/ReadLine.c /^ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum) {$/;" f +Rmetal SRC/include/physical_types.h /^ float Rmetal;$/;" m struct:s_segment_inf +Rseg_global SRC/include/arch_types_mrfpga.h /^ float Rseg_global;$/;" m struct:s_arch_mrfpga +SBType SRC/include/physical_types.h /^ enum e_switch_block_type SBType;$/;" m struct:s_arch typeref:enum:s_arch::e_switch_block_type +SDCFile SRC/include/physical_types.h /^ char * SDCFile; \/* only here for convenience of passing to path_delay.c *\/$/;" m struct:s_timing_inf +SIDES_H SRC/include/sides.h 2;" d +SPICE_ABS SRC/fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type +SPICE_CB_MUX_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_CB_MUX_TB, $/;" e enum:e_spice_tb_type +SPICE_CB_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_CB_TB,$/;" e enum:e_spice_tb_type +SPICE_FRAC SRC/fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type +SPICE_GRID_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_GRID_TB,$/;" e enum:e_spice_tb_type +SPICE_HARDLOGIC_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_HARDLOGIC_TB$/;" e enum:e_spice_tb_type +SPICE_IO_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_IO_TB,$/;" e enum:e_spice_tb_type +SPICE_LIB_ACADEMIA SRC/fpga_spice_include/spice_types.h /^ SPICE_LIB_ACADEMIA$/;" e enum:e_spice_tech_lib_type +SPICE_LIB_INDUSTRY SRC/fpga_spice_include/spice_types.h /^ SPICE_LIB_INDUSTRY,$/;" e enum:e_spice_tech_lib_type +SPICE_LUT_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_LUT_TB,$/;" e enum:e_spice_tb_type +SPICE_MODEL_BUF_BUF SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_BUF$/;" e enum:e_spice_model_buffer_type +SPICE_MODEL_BUF_INV SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_INV, $/;" e enum:e_spice_model_buffer_type +SPICE_MODEL_CHAN_WIRE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_CHAN_WIRE, $/;" e enum:e_spice_model_type +SPICE_MODEL_DELAY_FALL SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DELAY_FALL$/;" e enum:spice_model_delay_type +SPICE_MODEL_DELAY_RISE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DELAY_RISE, $/;" e enum:spice_model_delay_type +SPICE_MODEL_DESIGN_CMOS SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_CMOS, $/;" e enum:e_spice_model_design_tech +SPICE_MODEL_DESIGN_RRAM SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_RRAM$/;" e enum:e_spice_model_design_tech +SPICE_MODEL_FF SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_FF, $/;" e enum:e_spice_model_type +SPICE_MODEL_GATE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_GATE $/;" e enum:e_spice_model_type +SPICE_MODEL_GATE_AND SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_GATE_AND, $/;" e enum:e_spice_model_gate_type +SPICE_MODEL_GATE_OR SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_GATE_OR$/;" e enum:e_spice_model_gate_type +SPICE_MODEL_HARDLOGIC SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_HARDLOGIC,$/;" e enum:e_spice_model_type +SPICE_MODEL_INVBUF SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_INVBUF, $/;" e enum:e_spice_model_type +SPICE_MODEL_IOPAD SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_IOPAD, $/;" e enum:e_spice_model_type +SPICE_MODEL_LUT SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_LUT, $/;" e enum:e_spice_model_type +SPICE_MODEL_MUX SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_MUX, $/;" e enum:e_spice_model_type +SPICE_MODEL_PASSGATE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASSGATE, $/;" e enum:e_spice_model_type +SPICE_MODEL_PASS_GATE_TRANSISTOR SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSISTOR$/;" e enum:e_spice_model_pass_gate_logic_type +SPICE_MODEL_PASS_GATE_TRANSMISSION SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSMISSION, $/;" e enum:e_spice_model_pass_gate_logic_type +SPICE_MODEL_PORT_BL SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BL,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_BLB SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BLB,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_CLOCK SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_CLOCK, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_INOUT SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INOUT, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_INPUT SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INPUT, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_OUTPUT SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_OUTPUT, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_SRAM SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_SRAM,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_WL SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WL,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_WLB SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WLB$/;" e enum:e_spice_model_port_type +SPICE_MODEL_SCFF SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_SCFF,$/;" e enum:e_spice_model_type +SPICE_MODEL_SRAM SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_SRAM, $/;" e enum:e_spice_model_type +SPICE_MODEL_STRUCTURE_CROSSBAR SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_CROSSBAR $/;" e enum:e_spice_model_structure +SPICE_MODEL_STRUCTURE_MULTILEVEL SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_MULTILEVEL, $/;" e enum:e_spice_model_structure +SPICE_MODEL_STRUCTURE_ONELEVEL SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_ONELEVEL, $/;" e enum:e_spice_model_structure +SPICE_MODEL_STRUCTURE_TREE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_TREE, $/;" e enum:e_spice_model_structure +SPICE_MODEL_WIRE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_WIRE, $/;" e enum:e_spice_model_type +SPICE_PB_MUX_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_PB_MUX_TB, $/;" e enum:e_spice_tb_type +SPICE_PB_PORT_CLOCK SRC/fpga_spice_include/spice_types.h /^ SPICE_PB_PORT_CLOCK$/;" e enum:e_spice_pb_port_type +SPICE_PB_PORT_INPUT SRC/fpga_spice_include/spice_types.h /^ SPICE_PB_PORT_INPUT,$/;" e enum:e_spice_pb_port_type +SPICE_PB_PORT_OUTPUT SRC/fpga_spice_include/spice_types.h /^ SPICE_PB_PORT_OUTPUT,$/;" e enum:e_spice_pb_port_type +SPICE_SB_MUX_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_SB_MUX_TB, $/;" e enum:e_spice_tb_type +SPICE_SB_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_SB_TB,$/;" e enum:e_spice_tb_type +SPICE_SRAM_MEMORY_BANK SRC/fpga_spice_include/spice_types.h /^ SPICE_SRAM_MEMORY_BANK$/;" e enum:e_sram_orgz +SPICE_SRAM_SCAN_CHAIN SRC/fpga_spice_include/spice_types.h /^ SPICE_SRAM_SCAN_CHAIN,$/;" e enum:e_sram_orgz +SPICE_SRAM_STANDALONE SRC/fpga_spice_include/spice_types.h /^ SPICE_SRAM_STANDALONE,$/;" e enum:e_sram_orgz +SPICE_TRANS_IO_NMOS SRC/fpga_spice_include/spice_types.h /^ SPICE_TRANS_IO_NMOS, $/;" e enum:e_spice_trans_type +SPICE_TRANS_IO_PMOS SRC/fpga_spice_include/spice_types.h /^ SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type +SPICE_TRANS_NMOS SRC/fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, $/;" e enum:e_spice_trans_type +SPICE_TRANS_PMOS SRC/fpga_spice_include/spice_types.h /^ SPICE_TRANS_PMOS, $/;" e enum:e_spice_trans_type +SPICE_TYPES_H SRC/fpga_spice_include/spice_types.h 2;" d +STTRAM SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +SUBSET SRC/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +SWSEG_UNBUF_CB SRC/include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type +SWSEG_UNBUF_SB SRC/include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type +Segments SRC/include/physical_types.h /^ t_segment_inf * Segments;$/;" m struct:s_arch +SetupEmptyType SRC/read_xml_arch_file.c /^static void SetupEmptyType(void) {$/;" f file: +SetupGridLocations SRC/read_xml_arch_file.c /^static void SetupGridLocations(ezxml_t Locations, t_type_descriptor * Type) {$/;" f file: +SetupPinEquivalenceAutoDetect SRC/read_xml_arch_file.c /^void SetupPinEquivalenceAutoDetect(ezxml_t Parent, t_type_descriptor* Type) {$/;" f file: +SetupPinLocationsAndPinClasses SRC/read_xml_arch_file.c /^static void SetupPinLocationsAndPinClasses(ezxml_t Locations,$/;" f file: +Side SRC/include/sides.h /^class Side {$/;" c +Side SRC/sides.cpp /^Side::Side() {$/;" f class:Side +Side SRC/sides.cpp /^Side::Side(enum e_side side) {$/;" f class:Side +Side SRC/sides.cpp /^Side::Side(size_t side) { $/;" f class:Side +Switches SRC/include/physical_types.h /^ struct s_switch_inf *Switches;$/;" m struct:s_arch typeref:struct:s_arch::s_switch_inf +SyncModelsPbTypes SRC/read_xml_arch_file.c /^static void SyncModelsPbTypes(INOUTP struct s_arch *arch,$/;" f file: +SyncModelsPbTypes_rec SRC/read_xml_arch_file.c /^static void SyncModelsPbTypes_rec(INOUTP struct s_arch *arch,$/;" f file: +TOKENS SRC/include/arch_types.h 19;" d +TOP SRC/include/sides.h /^ TOP = 0, $/;" e enum:e_side +TRUE SRC/include/util.h /^ FALSE, TRUE$/;" e enum:__anon4 +TYPICAL_CORNER SRC/fpga_spice_include/spice_types.h /^ TYPICAL_CORNER,$/;" e enum:e_process_corner +T_ipin_cblock SRC/include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_arch +T_ipin_cblock SRC/include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_timing_inf +T_opin_cblock SRC/include/arch_types_mrfpga.h /^ float T_opin_cblock;$/;" m struct:s_arch_mrfpga +T_opin_cblock SRC/include/physical_types.h /^ float T_opin_cblock;$/;" m struct:s_timing_inf +Tdel SRC/include/arch_types_mrfpga.h /^ float Tdel; $/;" m struct:s_memristor_inf +Tdel SRC/include/arch_types_mrfpga.h /^ float Tdel;$/;" m struct:s_buffer_inf +Tdel SRC/include/physical_types.h /^ float Tdel;$/;" m struct:s_switch_inf +UNDEFINED SRC/include/arch_types.h 22;" d +UNIFORM SRC/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +UNIVERSAL SRC/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +UNI_DIRECTIONAL SRC/include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality +UNKNOWN_CLASS SRC/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +UTIL_H SRC/include/util.h 2;" d +UpdateAndCheckModels SRC/read_xml_arch_file.c /^static void UpdateAndCheckModels(INOUTP struct s_arch *arch) {$/;" f file: +VPR_VERSION SRC/include/arch_types.h 16;" d +W SRC/include/physical_types.h /^ int W;$/;" m struct:s_clb_grid +WARNTAG SRC/include/util.h 27;" d +WILTON SRC/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +WIRE_MODEL_PIE SRC/fpga_spice_include/spice_types.h /^ WIRE_MODEL_PIE,$/;" e enum:e_wire_model_type +WIRE_MODEL_T SRC/fpga_spice_include/spice_types.h /^ WIRE_MODEL_T$/;" e enum:e_wire_model_type +WORST_CORNER SRC/fpga_spice_include/spice_types.h /^ WORST_CORNER$/;" e enum:e_process_corner +XmlReadArch SRC/read_xml_arch_file.c /^void XmlReadArch(INP const char *ArchFile, INP boolean timing_enabled,$/;" f +_EZXML_H SRC/include/ezxml.h 26;" d +abs_variation SRC/fpga_spice_include/spice_types.h /^ float abs_variation;$/;" m struct:s_spice_mc_variation_params +absolute_length SRC/include/physical_types.h /^ float absolute_length;$/;" m union:s_port_power::__anon3 +absolute_power_per_instance SRC/include/physical_types.h /^ t_power_usage absolute_power_per_instance; \/* User-provided absolute power per block *\/$/;" m struct:s_pb_type_power +accuracy SRC/fpga_spice_include/spice_types.h /^ float accuracy;$/;" m struct:s_spice_meas_params +accuracy_type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type accuracy_type;$/;" m struct:s_spice_meas_params typeref:enum:s_spice_meas_params::e_spice_accuracy_type +add_const_input SRC/fpga_spice_include/spice_types.h /^ boolean add_const_input;$/;" m struct:s_spice_model_mux +addr SRC/fpga_spice_include/spice_types.h /^ int addr; \/* Address to write the value *\/$/;" m struct:s_conf_bit +advanced_rram_design SRC/fpga_spice_include/spice_types.h /^ boolean advanced_rram_design;$/;" m struct:s_spice_model_mux +alloc_and_load_default_child_for_pb_type SRC/read_xml_arch_file.c /^static void alloc_and_load_default_child_for_pb_type( INOUTP t_pb_type *pb_type,$/;" f file: +alloc_ivector_and_copy_int_list SRC/util.c /^void alloc_ivector_and_copy_int_list(t_linked_int ** list_head_ptr,$/;" f +alloc_matrix SRC/util.c /^alloc_matrix(int nrmin, int nrmax, int ncmin, int ncmax, size_t elsize) {$/;" f +alloc_matrix3 SRC/util.c /^alloc_matrix3(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f +alloc_matrix4 SRC/util.c /^alloc_matrix4(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f +annotations SRC/include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_interconnect +annotations SRC/include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_pb_type +arch_mrfpga SRC/include/physical_types.h /^ t_arch_mrfpga arch_mrfpga;$/;" m struct:s_arch +area SRC/fpga_spice_include/spice_types.h /^ float area; \/\/Xifan TANG$/;" m struct:s_sram_inf +area SRC/include/physical_types.h /^ float area;$/;" m struct:s_type_descriptor +attr SRC/include/ezxml.h /^ char ***attr; \/* default attributes *\/$/;" m struct:ezxml_root +attr SRC/include/ezxml.h /^ char **attr; \/* tag attributes { name, value, name, value, ... NULL } *\/$/;" m struct:ezxml +auto_select_sim_num_clk_cycle SRC/fpga_spice_include/spice_types.h /^ int auto_select_sim_num_clk_cycle;$/;" m struct:s_spice_meas_params +autosize_buffer SRC/include/physical_types.h /^ boolean autosize_buffer; \/* autosize clock buffers *\/$/;" m struct:s_clock_network +base_cost SRC/include/cad_types.h /^ float base_cost; \/* base cost of pattern eg. If a group of logical blocks match a pattern of smaller primitives, that is better than the same group using bigger primitives *\/$/;" m struct:s_pack_patterns +base_cost SRC/include/cad_types.h /^ float base_cost; \/* cost independant of current status of packing *\/$/;" m struct:s_cluster_placement_primitive +bl SRC/fpga_spice_include/spice_types.h /^ t_conf_bit* bl;$/;" m struct:s_conf_bit_info +blif_model SRC/include/physical_types.h /^ char *blif_model;$/;" m struct:s_pb_type +block_id SRC/include/cad_types.h /^ int block_id;$/;" m struct:s_pack_pattern_block +boolean SRC/include/util.h /^typedef int boolean;$/;" t +boolean SRC/include/util.h /^} boolean;$/;" t typeref:enum:__anon4 +buf_size SRC/include/physical_types.h /^ float buf_size;$/;" m struct:s_switch_inf +buffer_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* buffer_info;$/;" m struct:s_spice_model_design_tech_info +buffer_size SRC/include/physical_types.h /^ float buffer_size; \/* if not autosized, the clock buffer size *\/$/;" m struct:s_clock_network +buffer_size SRC/include/physical_types.h /^ float buffer_size;$/;" m struct:s_pb_graph_pin_power +buffer_size SRC/include/physical_types.h /^ float buffer_size;$/;" m struct:s_port_power +buffer_type SRC/include/physical_types.h /^ e_power_buffer_type buffer_type;$/;" m struct:s_port_power +buffered SRC/include/physical_types.h /^ boolean buffered;$/;" m struct:s_switch_inf +c_str SRC/sides.cpp /^const char* Side::c_str() const { $/;" f class:Side +cap_val SRC/fpga_spice_include/spice_types.h /^ float cap_val; $/;" m struct:s_spice_model_wire_param +capacitance SRC/include/physical_types.h /^ float capacitance;$/;" m struct:s_pb_graph_edge +capacity SRC/include/physical_types.h /^ int capacity;$/;" m struct:s_type_descriptor +captab SRC/fpga_spice_include/spice_types.h /^ int captab;$/;" m struct:s_spice_params +cat_llists SRC/linkedlist.c /^t_llist* cat_llists(t_llist* head1,$/;" f +cb SRC/include/physical_types.h /^ boolean *cb;$/;" m struct:s_segment_inf +cb_len SRC/include/physical_types.h /^ int cb_len;$/;" m struct:s_segment_inf +cb_switches SRC/include/physical_types.h /^ t_switch_inf* cb_switches;$/;" m struct:s_arch +cb_type_descriptors SRC/read_xml_arch_file.c /^static struct s_type_descriptor *cb_type_descriptors;$/;" v typeref:struct:s_type_descriptor file: +cbx_index_high SRC/fpga_spice_include/spice_types.h /^ int** cbx_index_high;$/;" m struct:s_spice_model +cbx_index_low SRC/fpga_spice_include/spice_types.h /^ int** cbx_index_low;$/;" m struct:s_spice_model +cby_index_high SRC/fpga_spice_include/spice_types.h /^ int** cby_index_high;$/;" m struct:s_spice_model +cby_index_low SRC/fpga_spice_include/spice_types.h /^ int** cby_index_low;$/;" m struct:s_spice_model +chain_name SRC/include/physical_types.h /^ char *chain_name;$/;" m struct:s_port +chain_root_pin SRC/include/cad_types.h /^ t_pb_graph_pin *chain_root_pin; \/* pointer to logic block input pin that drives this chain from the preceding logic block *\/ $/;" m struct:s_pack_patterns +chan_length SRC/fpga_spice_include/spice_types.h /^ float chan_length;$/;" m struct:s_spice_transistor_type +chan_width_io SRC/include/physical_types.h /^ float chan_width_io;$/;" m struct:s_chan_width_dist +chan_x_dist SRC/include/physical_types.h /^ t_chan chan_x_dist;$/;" m struct:s_chan_width_dist +chan_y_dist SRC/include/physical_types.h /^ t_chan chan_y_dist;$/;" m struct:s_chan_width_dist +check_dptr_exist_in_llist SRC/linkedlist.c /^boolean check_dptr_exist_in_llist(t_llist* head, void* data_ptr) {$/;" f +check_spice_models SRC/read_xml_spice.c /^static void check_spice_models(int num_spice_model,$/;" f file: +check_tech_lib SRC/read_xml_spice.c /^static void check_tech_lib(t_spice_tech_lib tech_lib, $/;" f file: +child SRC/include/ezxml.h /^ ezxml_t child; \/* head of sub tag list, NULL if none *\/$/;" m struct:ezxml +child_pb_graph_nodes SRC/include/physical_types.h /^ struct s_pb_graph_node ***child_pb_graph_nodes; \/* [0..num_modes-1][0..num_pb_type_in_mode-1][0..num_pb-1] *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node +chunk_ptr_head SRC/include/util.h /^ struct s_linked_vptr *chunk_ptr_head; $/;" m struct:s_chunk typeref:struct:s_chunk::s_linked_vptr +class_inf SRC/include/physical_types.h /^ struct s_class *class_inf; \/* [0..num_class-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_class +class_type SRC/include/physical_types.h /^ enum e_pb_type_class class_type;$/;" m struct:s_pb_type typeref:enum:s_pb_type::e_pb_type_class +clb_grid SRC/include/physical_types.h /^ struct s_clb_grid clb_grid;$/;" m struct:s_arch typeref:struct:s_arch::s_clb_grid +clock SRC/include/physical_types.h /^ char * clock;$/;" m struct:s_pin_to_pin_annotation +clock_inf SRC/include/physical_types.h /^ t_clock_network *clock_inf; \/* Details about each clock *\/$/;" m struct:s_clock_arch +clock_pins SRC/include/physical_types.h /^ t_pb_graph_pin **clock_pins; \/* [0..num_clock_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node +clock_slew_fall_time SRC/fpga_spice_include/spice_types.h /^ float clock_slew_fall_time; $/;" m struct:s_spice_stimulate_params +clock_slew_fall_type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +clock_slew_rise_time SRC/fpga_spice_include/spice_types.h /^ float clock_slew_rise_time; $/;" m struct:s_spice_stimulate_params +clock_slew_rise_type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +clocks SRC/include/physical_types.h /^ t_clock_arch * clocks;$/;" m struct:s_arch +close SRC/ezxml.c 61;" d file: +cluster_placement_primitive SRC/include/physical_types.h /^ struct s_cluster_placement_primitive *cluster_placement_primitive; \/* pointer to indexing structure useful during packing stage *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_cluster_placement_primitive +cmos_variation SRC/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params cmos_variation;$/;" m struct:s_spice_mc_params +cnt SRC/fpga_spice_include/spice_types.h /^ int cnt; \/* Used in mux_testbench only*\/$/;" m struct:s_spice_mux_model +cnt SRC/fpga_spice_include/spice_types.h /^ int cnt;$/;" m struct:s_spice_model +col_rel SRC/include/physical_types.h /^ float col_rel;$/;" m struct:s_grid_loc_def +conf_bit_head SRC/fpga_spice_include/spice_types.h /^ t_llist* conf_bit_head; $/;" m struct:s_sram_orgz_info +connections SRC/include/cad_types.h /^ struct s_pack_pattern_connections *connections; \/* linked list of connections of logic blocks in pattern *\/$/;" m struct:s_pack_pattern_block typeref:struct:s_pack_pattern_block::s_pack_pattern_connections +const_input_val SRC/fpga_spice_include/spice_types.h /^ int const_input_val;$/;" m struct:s_spice_model_mux +cont SRC/util.c /^static int cont; \/* line continued? *\/$/;" v file: +create_llist SRC/linkedlist.c /^t_llist* create_llist(int len) {$/;" f +cur SRC/include/ezxml.h /^ ezxml_t cur; \/* current xml tree insertion point *\/$/;" m struct:ezxml_root +current_random SRC/util.c /^static unsigned int current_random = 0;$/;" v file: +data SRC/include/util.h /^ int data;$/;" m struct:s_linked_int +data_vptr SRC/include/util.h /^ void *data_vptr;$/;" m struct:s_linked_vptr +dc SRC/include/physical_types.h /^ float dc;$/;" m struct:s_chan +default_mode_num_conf_bits SRC/include/physical_types.h /^ int default_mode_num_conf_bits;$/;" m struct:s_pb_type +default_mode_num_iopads SRC/include/physical_types.h /^ int default_mode_num_iopads;$/;" m struct:s_pb_type +default_mode_num_mode_bits SRC/include/physical_types.h /^ int default_mode_num_mode_bits;$/;" m struct:s_pb_type +default_mode_num_reserved_conf_bits SRC/include/physical_types.h /^ int default_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type +default_val SRC/fpga_spice_include/spice_types.h /^ int default_val;$/;" m struct:s_spice_model_port +define_idle_mode SRC/include/physical_types.h /^ int define_idle_mode; $/;" m struct:s_mode +define_physical_mode SRC/include/physical_types.h /^ int define_physical_mode; $/;" m struct:s_mode +delay_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_delay_info* delay_info;$/;" m struct:s_spice_model +delay_max SRC/include/physical_types.h /^ float delay_max;$/;" m struct:s_pb_graph_edge +delay_min SRC/include/physical_types.h /^ float delay_min;$/;" m struct:s_pb_graph_edge +delete_in_vptr_list SRC/util.c /^delete_in_vptr_list(struct s_linked_vptr *head) {$/;" f +dens SRC/include/physical_types.h /^ float dens; \/* Switching density of net assigned to this clock *\/$/;" m struct:s_clock_network +density SRC/fpga_spice_include/spice_types.h /^ float density;$/;" m struct:s_spice_net_info +depth SRC/include/physical_types.h /^ int depth; \/* depth of pb_type *\/$/;" m struct:s_pb_type +design_tech SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_design_tech design_tech;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_design_tech +design_tech_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_design_tech_info design_tech_info;$/;" m struct:s_spice_model +dir SRC/include/logic_types.h /^ enum PORTS dir; \/* port direction *\/$/;" m struct:s_model_ports typeref:enum:s_model_ports::PORTS +directionality SRC/include/physical_types.h /^ enum e_directionality directionality;$/;" m struct:s_segment_inf typeref:enum:s_segment_inf::e_directionality +disabled_in_packing SRC/include/physical_types.h /^ boolean disabled_in_packing;$/;" m struct:s_mode +dptr SRC/fpga_spice_include/linkedlist.h /^ void* dptr;$/;" m struct:s_llist +driver_pin SRC/include/physical_types.h /^ int driver_pin;$/;" m struct:s_pb_graph_edge +driver_set SRC/include/physical_types.h /^ int driver_set;$/;" m struct:s_pb_graph_edge +dump_explicit_port_map SRC/fpga_spice_include/spice_types.h /^ boolean dump_explicit_port_map;$/;" m struct:s_spice_model +dump_structural_verilog SRC/fpga_spice_include/spice_types.h /^ boolean dump_structural_verilog;$/;" m struct:s_spice_model +dynamic SRC/include/physical_types.h /^ float dynamic;$/;" m struct:s_power_usage +e SRC/include/ezxml.h /^ char *e; \/* end of work area *\/$/;" m struct:ezxml_root +e_Fc_type SRC/include/physical_types.h /^enum e_Fc_type {$/;" g +e_directionality SRC/include/physical_types.h /^enum e_directionality {$/;" g +e_grid_loc_type SRC/include/physical_types.h /^enum e_grid_loc_type {$/;" g +e_interconnect SRC/include/physical_types.h /^enum e_interconnect {$/;" g +e_pb_graph_pin_type SRC/include/physical_types.h /^enum e_pb_graph_pin_type {$/;" g +e_pb_type_class SRC/include/physical_types.h /^enum e_pb_type_class {$/;" g +e_pin_location_distr SRC/include/physical_types.h /^enum e_pin_location_distr {$/;" g +e_pin_to_pin_annotation_format SRC/include/physical_types.h /^enum e_pin_to_pin_annotation_format {$/;" g +e_pin_to_pin_annotation_type SRC/include/physical_types.h /^enum e_pin_to_pin_annotation_type {$/;" g +e_pin_to_pin_capacitance_annotations SRC/include/physical_types.h /^enum e_pin_to_pin_capacitance_annotations {$/;" g +e_pin_to_pin_delay_annotations SRC/include/physical_types.h /^enum e_pin_to_pin_delay_annotations {$/;" g +e_pin_to_pin_mode_select_annotations SRC/include/physical_types.h /^enum e_pin_to_pin_mode_select_annotations {$/;" g +e_pin_to_pin_pack_pattern_annotations SRC/include/physical_types.h /^enum e_pin_to_pin_pack_pattern_annotations {$/;" g +e_pin_type SRC/include/physical_types.h /^enum e_pin_type {$/;" g +e_power_buffer_type SRC/include/physical_types.h /^} e_power_buffer_type;$/;" t typeref:enum:__anon2 +e_power_estimation_method SRC/include/physical_types.h /^typedef enum e_power_estimation_method_ e_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ +e_power_estimation_method_ SRC/include/physical_types.h /^enum e_power_estimation_method_ {$/;" g +e_power_wire_type SRC/include/physical_types.h /^} e_power_wire_type;$/;" t typeref:enum:__anon1 +e_process_corner SRC/fpga_spice_include/spice_types.h /^enum e_process_corner {$/;" g +e_side SRC/include/sides.h /^enum e_side {$/;" g +e_spice_accuracy_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_accuracy_type {$/;" g +e_spice_ff_trigger_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_ff_trigger_type {$/;" g +e_spice_model_buffer_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_buffer_type {$/;" g +e_spice_model_design_tech SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_design_tech {$/;" g +e_spice_model_gate_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_gate_type {$/;" g +e_spice_model_pass_gate_logic_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_pass_gate_logic_type {$/;" g +e_spice_model_port_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_port_type {$/;" g +e_spice_model_structure SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_structure {$/;" g +e_spice_model_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_type {$/;" g +e_spice_pb_port_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_pb_port_type {$/;" g +e_spice_pin2pin_interc_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_pin2pin_interc_type {$/;" g +e_spice_tb_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_tb_type {$/;" g +e_spice_tech_lib_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_tech_lib_type {$/;" g +e_spice_trans_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_trans_type {$/;" g +e_sram_orgz SRC/fpga_spice_include/spice_types.h /^enum e_sram_orgz {$/;" g +e_stat SRC/include/physical_types.h /^enum e_stat {$/;" g +e_switch_block_type SRC/include/physical_types.h /^enum e_switch_block_type {$/;" g +e_swseg_pattern_type SRC/include/physical_types.h /^enum e_swseg_pattern_type {$/;" g +e_tech_comp SRC/include/arch_types_mrfpga.h /^enum e_tech_comp { $/;" g +e_wire_model_type SRC/fpga_spice_include/spice_types.h /^enum e_wire_model_type {$/;" g +energy_per_toggle SRC/include/physical_types.h /^ float energy_per_toggle;$/;" m struct:s_port_power +ent SRC/include/ezxml.h /^ char **ent; \/* general entities (ampersand sequences) *\/$/;" m struct:ezxml_root +equivalent SRC/include/physical_types.h /^ boolean equivalent;$/;" m struct:s_port +err SRC/include/ezxml.h /^ char err[EZXML_ERRL]; \/* error string *\/$/;" m struct:ezxml_root +estimation_method SRC/include/physical_types.h /^ e_power_estimation_method estimation_method;$/;" m struct:s_pb_type_power +exist SRC/fpga_spice_include/spice_types.h /^ int exist;$/;" m struct:s_spice_model_buffer +ezxml SRC/include/ezxml.h /^struct ezxml {$/;" s +ezxml_add_child SRC/ezxml.c /^ezxml_t ezxml_add_child(ezxml_t xml, char *name, size_t off) {$/;" f +ezxml_add_child_d SRC/include/ezxml.h 149;" d +ezxml_ampencode SRC/ezxml.c /^ezxml_ampencode(const char *s, size_t len, char **dst, size_t * dlen,$/;" f file: +ezxml_attr SRC/ezxml.c /^ezxml_attr(ezxml_t xml, const char *attr) {$/;" f +ezxml_char_content SRC/ezxml.c /^static void ezxml_char_content(ezxml_root_t root, char *s,$/;" f file: +ezxml_child SRC/ezxml.c /^ezxml_t ezxml_child(ezxml_t xml, const char *name) {$/;" f +ezxml_close_tag SRC/ezxml.c /^static ezxml_t ezxml_close_tag(ezxml_root_t root, char *name, char *s) {$/;" f file: +ezxml_cut SRC/ezxml.c /^ezxml_t ezxml_cut(ezxml_t xml) {$/;" f +ezxml_decode SRC/ezxml.c /^ezxml_decode(char *s, char **ent, char t) {$/;" f file: +ezxml_ent_ok SRC/ezxml.c /^static int ezxml_ent_ok(char *name, char *s, char **ent) {$/;" f file: +ezxml_err SRC/ezxml.c /^static ezxml_t ezxml_err(ezxml_root_t root, char *s, const char *err, ...) {$/;" f file: +ezxml_error SRC/ezxml.c /^ezxml_error(ezxml_t xml) {$/;" f +ezxml_free SRC/ezxml.c /^void ezxml_free(ezxml_t xml) {$/;" f +ezxml_free_attr SRC/ezxml.c /^static void ezxml_free_attr(char **attr) {$/;" f file: +ezxml_get SRC/ezxml.c /^ezxml_t ezxml_get(ezxml_t xml, ...) {$/;" f +ezxml_idx SRC/ezxml.c /^ezxml_t ezxml_idx(ezxml_t xml, int idx) {$/;" f +ezxml_insert SRC/ezxml.c /^ezxml_t ezxml_insert(ezxml_t xml, ezxml_t dest, size_t off) {$/;" f +ezxml_internal_dtd SRC/ezxml.c /^static short ezxml_internal_dtd(ezxml_root_t root, char *s,$/;" f file: +ezxml_move SRC/include/ezxml.h 178;" d +ezxml_name SRC/include/ezxml.h 108;" d +ezxml_new SRC/ezxml.c /^ezxml_t ezxml_new(char *name) {$/;" f +ezxml_new_d SRC/include/ezxml.h 142;" d +ezxml_next SRC/include/ezxml.h 101;" d +ezxml_open_tag SRC/ezxml.c /^static void ezxml_open_tag(ezxml_root_t root, int line, char *name, char **attr) {$/;" f file: +ezxml_parse_fd SRC/ezxml.c /^ezxml_t ezxml_parse_fd(int fd) {$/;" f +ezxml_parse_file SRC/ezxml.c /^ezxml_t ezxml_parse_file(const char *file) {$/;" f +ezxml_parse_fp SRC/ezxml.c /^ezxml_t ezxml_parse_fp(FILE * fp) {$/;" f +ezxml_parse_str SRC/ezxml.c /^ezxml_t ezxml_parse_str(char *s, size_t len) {$/;" f +ezxml_pi SRC/ezxml.c /^ezxml_pi(ezxml_t xml, const char *target) {$/;" f +ezxml_proc_inst SRC/ezxml.c /^static void ezxml_proc_inst(ezxml_root_t root, char *s, size_t len) {$/;" f file: +ezxml_remove SRC/include/ezxml.h 181;" d +ezxml_root SRC/include/ezxml.h /^struct ezxml_root { \/* additional data for the root tag *\/$/;" s +ezxml_root_t SRC/include/ezxml.h /^typedef struct ezxml_root *ezxml_root_t;$/;" t typeref:struct:ezxml_root +ezxml_set_attr SRC/ezxml.c /^ezxml_t ezxml_set_attr(ezxml_t xml, char *name, char *value) {$/;" f +ezxml_set_attr_d SRC/include/ezxml.h 164;" d +ezxml_set_flag SRC/ezxml.c /^ezxml_t ezxml_set_flag(ezxml_t xml, short flag) {$/;" f +ezxml_set_txt SRC/ezxml.c /^ezxml_t ezxml_set_txt(ezxml_t xml, char *txt) {$/;" f +ezxml_set_txt_d SRC/include/ezxml.h 156;" d +ezxml_str2utf8 SRC/ezxml.c /^ezxml_str2utf8(char **s, size_t * len) {$/;" f file: +ezxml_t SRC/include/ezxml.h /^typedef struct ezxml *ezxml_t;$/;" t typeref:struct:ezxml +ezxml_toxml SRC/ezxml.c /^ezxml_toxml(ezxml_t xml) {$/;" f +ezxml_toxml_r SRC/ezxml.c /^ezxml_toxml_r(ezxml_t xml, char **s, size_t * len, size_t * max, size_t start,$/;" f file: +ezxml_txt SRC/include/ezxml.h 111;" d +ezxml_vget SRC/ezxml.c /^ezxml_t ezxml_vget(ezxml_t xml, va_list ap) {$/;" f +f_per_stage SRC/fpga_spice_include/spice_types.h /^ int f_per_stage;$/;" m struct:s_spice_model_buffer +fan_in SRC/include/physical_types.h /^ int fan_in;$/;" m struct:s_interconnect +fan_out SRC/include/physical_types.h /^ int fan_out;$/;" m struct:s_interconnect +fast SRC/fpga_spice_include/spice_types.h /^ int fast;$/;" m struct:s_spice_params +file_exists SRC/util.c /^boolean file_exists(const char * filename) {$/;" f +file_line_number SRC/util.c /^int file_line_number; \/* file in line number being parsed *\/$/;" v +findPortByName SRC/read_xml_arch_file.c /^static t_port * findPortByName(const char * name, t_pb_type * pb_type,$/;" f file: +find_length_llist SRC/linkedlist.c /^int find_length_llist(t_llist* head) {$/;" f +flags SRC/include/ezxml.h /^ short flags; \/* additional information *\/$/;" m struct:ezxml +format SRC/include/physical_types.h /^ enum e_pin_to_pin_annotation_format format;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_format +frac_cb SRC/include/physical_types.h /^ float frac_cb;$/;" m struct:s_segment_inf +frac_lut SRC/fpga_spice_include/spice_types.h /^ boolean frac_lut;$/;" m struct:s_spice_model_lut +frac_sb SRC/include/physical_types.h /^ float frac_sb;$/;" m struct:s_segment_inf +free_chunk_memory SRC/util.c /^void free_chunk_memory(t_chunk *chunk_info) {$/;" f +free_int_list SRC/util.c /^void free_int_list(t_linked_int ** int_list_head_ptr) {$/;" f +free_ivec_matrix SRC/util.c /^void free_ivec_matrix(struct s_ivec **ivec_matrix, int nrmin, int nrmax,$/;" f +free_ivec_matrix3 SRC/util.c /^void free_ivec_matrix3(struct s_ivec ***ivec_matrix3, int nrmin, int nrmax,$/;" f +free_ivec_vector SRC/util.c /^void free_ivec_vector(struct s_ivec *ivec_vector, int nrmin, int nrmax) {$/;" f +free_llist SRC/linkedlist.c /^void free_llist(t_llist* head) {$/;" f +free_matrix SRC/util.c /^void free_matrix(void *vptr, int nrmin, int nrmax, int ncmin, size_t elsize) {$/;" f +free_matrix3 SRC/util.c /^void free_matrix3(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f +free_matrix4 SRC/util.c /^void free_matrix4(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f +freq SRC/fpga_spice_include/spice_types.h /^ float freq; $/;" m struct:s_spice_net_info +frequency SRC/include/physical_types.h /^ int frequency;$/;" m struct:s_segment_inf +from_block SRC/include/cad_types.h /^ t_pack_pattern_block *from_block;$/;" m struct:s_pack_pattern_connections +from_pin SRC/include/cad_types.h /^ t_pb_graph_pin *from_pin;$/;" m struct:s_pack_pattern_connections +from_pin SRC/include/physical_types.h /^ char *from_pin;$/;" m struct:s_direct_inf +from_port SRC/fpga_spice_include/spice_types.h /^ t_spice_model_port* from_port;$/;" m struct:s_spice_model_tedge +from_port_pin_number SRC/fpga_spice_include/spice_types.h /^ int from_port_pin_number;$/;" m struct:s_spice_model_tedge +gate_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_gate* gate_info;$/;" m struct:s_spice_model_design_tech_info +get_opposite SRC/sides.cpp /^enum e_side Side::get_opposite() const {$/;" f class:Side +get_rotate_clockwise SRC/sides.cpp /^enum e_side Side::get_rotate_clockwise() const {$/;" f class:Side +get_rotate_counterclockwise SRC/sides.cpp /^enum e_side Side::get_rotate_counterclockwise() const {$/;" f class:Side +get_side SRC/sides.cpp /^enum e_side Side::get_side() const { $/;" f class:Side +grid_conf_bits_lsb SRC/fpga_spice_include/spice_types.h /^ int** grid_conf_bits_lsb;$/;" m struct:s_sram_orgz_info +grid_conf_bits_msb SRC/fpga_spice_include/spice_types.h /^ int** grid_conf_bits_msb;$/;" m struct:s_sram_orgz_info +grid_index_high SRC/fpga_spice_include/spice_types.h /^ int** grid_index_high;$/;" m struct:s_spice_model +grid_index_low SRC/fpga_spice_include/spice_types.h /^ int** grid_index_low;$/;" m struct:s_spice_model +grid_loc_def SRC/include/physical_types.h /^ struct s_grid_loc_def *grid_loc_def; \/* [0..num_def-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_grid_loc_def +grid_loc_type SRC/include/physical_types.h /^ enum e_grid_loc_type grid_loc_type;$/;" m struct:s_grid_loc_def typeref:enum:s_grid_loc_def::e_grid_loc_type +grid_logic_tile_area SRC/include/physical_types.h /^ float grid_logic_tile_area;$/;" m struct:s_arch +grid_nx SRC/fpga_spice_include/spice_types.h /^ int grid_nx; \/* grid size *\/ $/;" m struct:s_sram_orgz_info +grid_ny SRC/fpga_spice_include/spice_types.h /^ int grid_ny;$/;" m struct:s_sram_orgz_info +grid_reserved_conf_bits SRC/fpga_spice_include/spice_types.h /^ int** grid_reserved_conf_bits;$/;" m struct:s_sram_orgz_info +height SRC/include/physical_types.h /^ int height;$/;" m struct:s_type_descriptor +idle_mode_name SRC/include/physical_types.h /^ char* idle_mode_name;$/;" m struct:s_pb_type +in_port_name SRC/fpga_spice_include/spice_types.h /^ char* in_port_name;$/;" m struct:s_spice_model_delay_info +include_netlist SRC/fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlist;$/;" m struct:s_spice_model +include_netlists SRC/fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlists; $/;" m struct:s_spice +included SRC/fpga_spice_include/spice_types.h /^ int included;$/;" m struct:s_spice_model_netlist +incremental_cost SRC/include/cad_types.h /^ float incremental_cost; \/* cost dependant on current status of packing *\/$/;" m struct:s_cluster_placement_primitive +index SRC/fpga_spice_include/spice_types.h /^ int index;$/;" m struct:s_conf_bit_info +index SRC/include/cad_types.h /^ int index; \/* array index for pattern*\/$/;" m struct:s_pack_patterns +index SRC/include/logic_types.h /^ int index; \/* indexing for array look-up *\/$/;" m struct:s_model_ports +index SRC/include/logic_types.h /^ int index;$/;" m struct:s_model +index SRC/include/physical_types.h /^ int index; \/* index of type descriptor in array (allows for index referencing) *\/$/;" m struct:s_type_descriptor +index SRC/include/physical_types.h /^ int index;$/;" m struct:s_mode +index SRC/include/physical_types.h /^ int index;$/;" m struct:s_port +index_in_top_tb SRC/fpga_spice_include/spice_types.h /^ int index_in_top_tb;$/;" m struct:s_conf_bit_info +infer_annotations SRC/include/physical_types.h /^ boolean infer_annotations;$/;" m struct:s_interconnect +infer_pattern SRC/include/physical_types.h /^ boolean infer_pattern; \/*If TRUE, infer pattern based on patterns connected to it*\/$/;" m struct:s_pb_graph_edge +init_arch_mrfpga SRC/read_xml_mrfpga.c /^void init_arch_mrfpga(t_arch_mrfpga* arch_mrfpga) {$/;" f +init_buffer_inf SRC/read_xml_mrfpga.c /^void init_buffer_inf(t_buffer_inf* buffer_inf) {$/;" f +init_memristor_inf SRC/read_xml_mrfpga.c /^void init_memristor_inf(t_memristor_inf* memristor_inf) {$/;" f +init_val SRC/fpga_spice_include/spice_types.h /^ int init_val;$/;" m struct:s_spice_net_info +inport_link_pin SRC/include/cad_types.h /^ int inport_link_pin; \/* applicable pin of chain input port *\/$/;" m struct:s_model_chain_pattern +input_buffer SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* input_buffer;$/;" m struct:s_spice_model +input_edges SRC/include/physical_types.h /^ struct s_pb_graph_edge** input_edges; \/* [0..num_input_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge +input_level SRC/fpga_spice_include/spice_types.h /^ int* input_level; \/* [0...num_input] *\/$/;" m struct:s_spice_mux_arch +input_link_port SRC/include/cad_types.h /^ t_model_ports *input_link_port; \/* pointer to port of chain input *\/$/;" m struct:s_model_chain_pattern +input_offset SRC/fpga_spice_include/spice_types.h /^ int* input_offset; \/* [0...num_input] *\/ $/;" m struct:s_spice_mux_arch +input_pin_class_size SRC/include/physical_types.h /^ int *input_pin_class_size; \/* Stores the number of pins that belong to a particular input pin class *\/$/;" m struct:s_pb_graph_node +input_pins SRC/include/physical_types.h /^ char * input_pins;$/;" m struct:s_pin_to_pin_annotation +input_pins SRC/include/physical_types.h /^ struct s_pb_graph_pin *** input_pins; \/\/ [0..num_input_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin +input_pins SRC/include/physical_types.h /^ t_pb_graph_pin **input_pins; \/* [0..num_input_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node +input_pins SRC/include/physical_types.h /^ t_pb_graph_pin **input_pins;$/;" m struct:s_pb_graph_edge +input_ports_eq_auto_detect SRC/include/physical_types.h /^ boolean input_ports_eq_auto_detect;$/;" m struct:s_type_descriptor +input_slew_fall_time SRC/fpga_spice_include/spice_types.h /^ float input_slew_fall_time; $/;" m struct:s_spice_stimulate_params +input_slew_fall_type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +input_slew_rise_time SRC/fpga_spice_include/spice_types.h /^ float input_slew_rise_time; $/;" m struct:s_spice_stimulate_params +input_slew_rise_type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +input_string SRC/include/physical_types.h /^ char *input_string;$/;" m struct:s_interconnect +input_thres_pct_fall SRC/fpga_spice_include/spice_types.h /^ float input_thres_pct_fall;$/;" m struct:s_spice_meas_params +input_thres_pct_rise SRC/fpga_spice_include/spice_types.h /^ float input_thres_pct_rise;$/;" m struct:s_spice_meas_params +inputs SRC/include/logic_types.h /^ t_model_ports *inputs; \/* linked list of input\/clock ports *\/$/;" m struct:s_model +insert_in_int_list SRC/util.c /^insert_in_int_list(t_linked_int * head, int data,$/;" f +insert_in_vptr_list SRC/util.c /^insert_in_vptr_list(struct s_linked_vptr *head, void *vptr_to_add) {$/;" f +insert_llist_node SRC/linkedlist.c /^t_llist* insert_llist_node(t_llist* cur) {$/;" f +insert_llist_node_before_head SRC/linkedlist.c /^t_llist* insert_llist_node_before_head(t_llist* old_head) {$/;" f +insert_node_to_int_list SRC/util.c /^insert_node_to_int_list(struct s_linked_int *head, int int_to_add) {$/;" f +instances SRC/include/logic_types.h /^ void *instances;$/;" m struct:s_model +interconnect SRC/include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_interconnect_pins +interconnect SRC/include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_pb_graph_edge +interconnect SRC/include/physical_types.h /^ t_interconnect *interconnect;$/;" m struct:s_mode +interconnect_pins SRC/include/physical_types.h /^ t_interconnect_pins ** interconnect_pins; \/* [0..num_modes-1][0..num_interconnect_in_mode] *\/$/;" m struct:s_pb_graph_node +interconnect_power SRC/include/physical_types.h /^ t_interconnect_power * interconnect_power;$/;" m struct:s_interconnect +inv_prefix SRC/fpga_spice_include/spice_types.h /^ char* inv_prefix; $/;" m struct:s_spice_model_port +inv_spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* inv_spice_model;$/;" m struct:s_spice_model_port +inv_spice_model_name SRC/fpga_spice_include/spice_types.h /^ char* inv_spice_model_name;$/;" m struct:s_spice_model_port +io_vdd SRC/fpga_spice_include/spice_types.h /^ float io_vdd;$/;" m struct:s_spice_tech_lib +ipin_mux_trans_size SRC/include/physical_types.h /^ float ipin_mux_trans_size;$/;" m struct:s_arch +ipow SRC/util.c /^int ipow(int base, int exp) {$/;" f +is_Fc_frac SRC/include/physical_types.h /^ boolean *is_Fc_frac; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +is_Fc_full_flex SRC/include/physical_types.h /^ boolean *is_Fc_full_flex; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +is_accurate SRC/include/arch_types_mrfpga.h /^ boolean is_accurate;$/;" m struct:s_arch_mrfpga +is_block_optional SRC/include/cad_types.h /^ boolean *is_block_optional; \/* [0..num_blocks-1] is the block_id in this pattern mandatory or optional to form a molecule *\/$/;" m struct:s_pack_patterns +is_chain SRC/include/cad_types.h /^ boolean is_chain; \/* Does this pattern chain across logic blocks *\/$/;" m struct:s_pack_patterns +is_clock SRC/include/logic_types.h /^ boolean is_clock; \/* clock? *\/$/;" m struct:s_model_ports +is_clock SRC/include/physical_types.h /^ boolean is_clock;$/;" m struct:s_port +is_config_enable SRC/fpga_spice_include/spice_types.h /^ boolean is_config_enable;$/;" m struct:s_spice_model_port +is_default SRC/fpga_spice_include/spice_types.h /^ int is_default;$/;" m struct:s_spice_model +is_disabled SRC/include/physical_types.h /^ boolean is_disabled;$/;" m struct:s_pb_graph_edge +is_forced_connection SRC/include/physical_types.h /^ boolean is_forced_connection; \/* This output pin connects to one and only one input pin *\/$/;" m struct:s_pb_graph_pin +is_global SRC/fpga_spice_include/spice_types.h /^ boolean is_global;$/;" m struct:s_spice_model_port +is_global_pin SRC/include/physical_types.h /^ boolean *is_global_pin; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +is_isolation SRC/include/arch_types_mrfpga.h /^ boolean is_isolation;$/;" m struct:s_arch_mrfpga +is_junction SRC/include/arch_types_mrfpga.h /^ boolean is_junction;$/;" m struct:s_arch_mrfpga +is_mrFPGA SRC/include/arch_types_mrfpga.h /^ boolean is_mrFPGA;$/;" m struct:s_arch_mrfpga +is_non_clock_global SRC/include/logic_types.h /^ boolean is_non_clock_global; \/* not a clock but is a special, global, control signal (eg global asynchronous reset, etc) *\/$/;" m struct:s_model_ports +is_non_clock_global SRC/include/physical_types.h /^ boolean is_non_clock_global;$/;" m struct:s_port +is_opin_cblock_defined SRC/include/arch_types_mrfpga.h /^ int is_opin_cblock_defined;$/;" m struct:s_arch_mrfpga +is_prog SRC/fpga_spice_include/spice_types.h /^ boolean is_prog;$/;" m struct:s_spice_model_port +is_reset SRC/fpga_spice_include/spice_types.h /^ boolean is_reset;$/;" m struct:s_spice_model_port +is_set SRC/fpga_spice_include/spice_types.h /^ boolean is_set;$/;" m struct:s_spice_model_port +is_show_pass_trans SRC/include/arch_types_mrfpga.h /^ boolean is_show_pass_trans;$/;" m struct:s_arch_mrfpga +is_show_sram SRC/include/arch_types_mrfpga.h /^ boolean is_show_sram;$/;" m struct:s_arch_mrfpga +is_stack SRC/include/arch_types_mrfpga.h /^ boolean is_stack;$/;" m struct:s_arch_mrfpga +is_wire_buffer SRC/include/arch_types_mrfpga.h /^ boolean is_wire_buffer;$/;" m struct:s_arch_mrfpga +leakage SRC/include/physical_types.h /^ float leakage;$/;" m struct:s_power_usage +leakage_default_mode SRC/include/physical_types.h /^ int leakage_default_mode; \/* Default mode for leakage analysis, if block has no set mode *\/$/;" m struct:s_pb_type_power +len SRC/include/ezxml.h /^ size_t len; \/* length of allocated memory for mmap, -1 for malloc *\/$/;" m struct:ezxml_root +length SRC/include/physical_types.h /^ int length;$/;" m struct:s_segment_inf +level SRC/fpga_spice_include/spice_types.h /^ int level;$/;" m struct:s_spice_model_wire_param +lib_name SRC/fpga_spice_include/spice_types.h /^ char* lib_name; $/;" m struct:s_spice_model_port +limit_value SRC/util.c /^int limit_value(int cur, int max, const char *name) {$/;" f +line SRC/include/ezxml.h /^ int line;$/;" m struct:ezxml +line SRC/include/physical_types.h /^ int line;$/;" m struct:s_direct_inf +line_num SRC/include/physical_types.h /^ int line_num; \/* Interconnect is processed later, need to know what line number it messed up on to give proper error message *\/$/;" m struct:s_interconnect +line_num SRC/include/physical_types.h /^ int line_num; \/* used to report what line number this annotation is found in architecture file *\/$/;" m struct:s_pin_to_pin_annotation +list SRC/include/util.h /^ int *list;$/;" m struct:s_ivec +list_of_connectable_input_pin_ptrs SRC/include/physical_types.h /^ struct s_pb_graph_pin ***list_of_connectable_input_pin_ptrs; \/* [0..depth-1][0..num_connectable_primtive_input_pins-1] what input pins this output can connect to without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin +local_interc_factor SRC/include/physical_types.h /^ float local_interc_factor;$/;" m struct:s_power_arch +location_map SRC/fpga_spice_include/spice_types.h /^ char* location_map;$/;" m struct:s_spice_model_buffer +logical_effort_factor SRC/include/physical_types.h /^ float logical_effort_factor;$/;" m struct:s_power_arch +longline SRC/include/physical_types.h /^ boolean longline;$/;" m struct:s_segment_inf +loop_breaker_delay_after_max SRC/include/physical_types.h /^ char *loop_breaker_delay_after_max;$/;" m struct:s_interconnect +loop_breaker_delay_after_max SRC/include/physical_types.h /^ char* loop_breaker_delay_after_max;$/;" m struct:s_pb_graph_edge +loop_breaker_delay_after_min SRC/include/physical_types.h /^ char *loop_breaker_delay_after_min;$/;" m struct:s_interconnect +loop_breaker_delay_after_min SRC/include/physical_types.h /^ char* loop_breaker_delay_after_min;$/;" m struct:s_pb_graph_edge +loop_breaker_delay_before_max SRC/include/physical_types.h /^ char *loop_breaker_delay_before_max;$/;" m struct:s_interconnect +loop_breaker_delay_before_max SRC/include/physical_types.h /^ char* loop_breaker_delay_before_max;$/;" m struct:s_pb_graph_edge +loop_breaker_delay_before_min SRC/include/physical_types.h /^ char *loop_breaker_delay_before_min;$/;" m struct:s_interconnect +loop_breaker_delay_before_min SRC/include/physical_types.h /^ char* loop_breaker_delay_before_min;$/;" m struct:s_pb_graph_edge +loop_breaker_string SRC/include/physical_types.h /^ char *loop_breaker_string;$/;" m struct:s_interconnect +lut_frac_level SRC/fpga_spice_include/spice_types.h /^ int lut_frac_level;$/;" m struct:s_spice_model_port +lut_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_lut* lut_info;$/;" m struct:s_spice_model_design_tech_info +lut_input_buffer SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_input_buffer;$/;" m struct:s_spice_model +lut_input_inverter SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_input_inverter;$/;" m struct:s_spice_model +lut_intermediate_buffer SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_intermediate_buffer;$/;" m struct:s_spice_model +lut_output_mask SRC/fpga_spice_include/spice_types.h /^ int* lut_output_mask;$/;" m struct:s_spice_model_port +m SRC/include/ezxml.h /^ char *m; \/* original xml string *\/$/;" m struct:ezxml_root +main SRC/ezxml.c /^main(int argc,$/;" f +main SRC/main.c /^int main(int argc, char **argv) {$/;" f +main_best_buffer_list SRC/include/arch_types_mrfpga.h /^ t_linked_int* main_best_buffer_list;$/;" m struct:s_arch_mrfpga +max_internal_delay SRC/include/physical_types.h /^ float max_internal_delay;$/;" m struct:s_pb_type +max_pins_per_side SRC/include/arch_types_mrfpga.h /^ int max_pins_per_side;$/;" m struct:s_arch_mrfpga +mc_params SRC/fpga_spice_include/spice_types.h /^ t_spice_mc_params mc_params;$/;" m struct:s_spice_params +mc_sim SRC/fpga_spice_include/spice_types.h /^ boolean mc_sim;$/;" m struct:s_spice_mc_params +meas_params SRC/fpga_spice_include/spice_types.h /^ t_spice_meas_params meas_params;$/;" m struct:s_spice_params +mem_avail SRC/include/util.h /^ int mem_avail; \/* number of bytes left in the current chunk *\/$/;" m struct:s_chunk +mem_bank_info SRC/fpga_spice_include/spice_types.h /^ t_mem_bank_info* mem_bank_info; \/* Only be allocated when orgz type is memory bank *\/$/;" m struct:s_sram_orgz_info +mem_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_mem_bank_info +mem_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_scff_info +mem_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_standalone_sram_info +memristor_inf SRC/include/arch_types_mrfpga.h /^ t_memristor_inf memristor_inf;$/;" m struct:s_arch_mrfpga +messagelogger SRC/include/util.h /^typedef unsigned char (*messagelogger)( TIO_MessageMode_t messageMode,$/;" t +min_size SRC/include/logic_types.h /^ int min_size; \/* minimum number of pins *\/$/;" m struct:s_model_ports +min_width SRC/fpga_spice_include/spice_types.h /^ float min_width;$/;" m struct:s_spice_transistor_type +mode_bits SRC/include/physical_types.h /^ char* mode_bits; \/* Mode bits to select *\/$/;" m struct:s_pb_type +mode_power SRC/include/physical_types.h /^ t_mode_power * mode_power;$/;" m struct:s_mode +mode_select SRC/fpga_spice_include/spice_types.h /^ boolean mode_select;$/;" m struct:s_spice_model_port +model SRC/include/cad_types.h /^ t_model *model; \/* block associated with chain *\/$/;" m struct:s_model_chain_pattern +model SRC/include/physical_types.h /^ t_model *model;$/;" m struct:s_pb_type +model_library SRC/include/physical_types.h /^ t_model *model_library;$/;" m struct:s_arch +model_name SRC/fpga_spice_include/spice_types.h /^ char* model_name;$/;" m struct:s_spice_transistor_type +model_netlist SRC/fpga_spice_include/spice_types.h /^ char* model_netlist; \/* SPICE netlist provided by user *\/$/;" m struct:s_spice_model +model_port SRC/include/physical_types.h /^ t_model_ports *model_port;$/;" m struct:s_port +model_ref SRC/fpga_spice_include/spice_types.h /^ char* model_ref;$/;" m struct:s_spice_tech_lib +models SRC/include/physical_types.h /^ t_model *models;$/;" m struct:s_arch +modes SRC/include/physical_types.h /^ t_mode *modes; \/* [0..num_modes-1] *\/$/;" m struct:s_pb_type +mux_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_mux* mux_info;$/;" m struct:s_spice_model_design_tech_info +mux_num_level SRC/fpga_spice_include/spice_types.h /^ int mux_num_level;$/;" m struct:s_spice_model_mux +mux_trans_size SRC/include/physical_types.h /^ float mux_trans_size;$/;" m struct:s_switch_inf +mux_transistor_size SRC/include/physical_types.h /^ float mux_transistor_size;$/;" m struct:s_power_arch +my_atoi SRC/util.c /^int my_atoi(const char *str) {$/;" f +my_calloc SRC/util.c /^my_calloc(size_t nelem, size_t size) {$/;" f +my_chunk_malloc SRC/util.c /^my_chunk_malloc(size_t size, t_chunk *chunk_info) {$/;" f +my_fgets SRC/util.c /^my_fgets(char *buf, int max_size, FILE * fp) {$/;" f +my_fopen SRC/util.c /^my_fopen(const char *fname, const char *flag, int prompt) {$/;" f +my_frand SRC/util.c /^float my_frand(void) {$/;" f +my_free SRC/read_xml_spice_util.c /^void my_free(void* ptr) {$/;" f +my_irand SRC/util.c /^int my_irand(int imax) {$/;" f +my_malloc SRC/util.c /^my_malloc(size_t size) {$/;" f +my_realloc SRC/util.c /^my_realloc(void *ptr, size_t size) {$/;" f +my_srandom SRC/util.c /^void my_srandom(int seed) {$/;" f +my_strdup SRC/util.c /^my_strdup(const char *str) {$/;" f +my_strncpy SRC/util.c /^my_strncpy(char *dest, const char *src, size_t size) {$/;" f +my_strtok SRC/util.c /^my_strtok(char *ptr, const char *tokens, FILE * fp, char *buf) {$/;" f +name SRC/fpga_spice_include/spice_types.h /^ char* name;$/;" m struct:s_spice_model +name SRC/include/cad_types.h /^ char *name; \/* name of this chain of logic *\/$/;" m struct:s_model_chain_pattern +name SRC/include/cad_types.h /^ char *name; \/* name of this logic model pattern *\/$/;" m struct:s_pack_patterns +name SRC/include/ezxml.h /^ char *name; \/* tag name *\/$/;" m struct:ezxml +name SRC/include/logic_types.h /^ char *name; \/* name of this logic model *\/$/;" m struct:s_model +name SRC/include/logic_types.h /^ char *name; \/* name of this port *\/$/;" m struct:s_model_ports +name SRC/include/physical_types.h /^ char *name;$/;" m struct:s_direct_inf +name SRC/include/physical_types.h /^ char *name;$/;" m struct:s_interconnect +name SRC/include/physical_types.h /^ char *name;$/;" m struct:s_switch_inf +name SRC/include/physical_types.h /^ char *name;$/;" m struct:s_type_descriptor +name SRC/include/physical_types.h /^ char* name;$/;" m struct:s_mode +name SRC/include/physical_types.h /^ char* name;$/;" m struct:s_pb_type +name SRC/include/physical_types.h /^ char* name;$/;" m struct:s_port +name_mux SRC/include/physical_types.h /^ char* name_mux;$/;" m struct:s_pb_graph_pin +nb_mux SRC/include/physical_types.h /^ int nb_mux;$/;" m struct:s_pb_graph_edge +nb_pin SRC/include/physical_types.h /^ int nb_pin;$/;" m struct:s_pb_graph_edge +nelem SRC/include/util.h /^ int nelem;$/;" m struct:s_ivec +next SRC/fpga_spice_include/linkedlist.h /^ t_llist* next;$/;" m struct:s_llist +next SRC/include/cad_types.h /^ struct s_model_chain_pattern *next; \/* next chain (linked list) *\/$/;" m struct:s_model_chain_pattern typeref:struct:s_model_chain_pattern::s_model_chain_pattern +next SRC/include/cad_types.h /^ struct s_pack_pattern_connections *next;$/;" m struct:s_pack_pattern_connections typeref:struct:s_pack_pattern_connections::s_pack_pattern_connections +next SRC/include/ezxml.h /^ ezxml_t next; \/* next tag with same name in this section at this depth *\/$/;" m struct:ezxml +next SRC/include/logic_types.h /^ struct s_model *next; \/* next model (linked list) *\/$/;" m struct:s_model typeref:struct:s_model::s_model +next SRC/include/logic_types.h /^ struct s_model_ports *next; \/* next port *\/$/;" m struct:s_model_ports typeref:struct:s_model_ports::s_model_ports +next SRC/include/util.h /^ struct s_linked_int *next;$/;" m struct:s_linked_int typeref:struct:s_linked_int::s_linked_int +next SRC/include/util.h /^ struct s_linked_vptr *next;$/;" m struct:s_linked_vptr typeref:struct:s_linked_vptr::s_linked_vptr +next_mem_loc_ptr SRC/include/util.h /^ char *next_mem_loc_ptr;\/* pointer to the first available (free) *$/;" m struct:s_chunk +next_primitive SRC/include/cad_types.h /^ struct s_cluster_placement_primitive *next_primitive;$/;" m struct:s_cluster_placement_primitive typeref:struct:s_cluster_placement_primitive::s_cluster_placement_primitive +nint SRC/include/util.h 24;" d +nmos_size SRC/fpga_spice_include/spice_types.h /^ float nmos_size;$/;" m struct:s_spice_model_pass_gate_logic +nominal_vdd SRC/fpga_spice_include/spice_types.h /^ float nominal_vdd;$/;" m struct:s_spice_tech_lib +num_annotations SRC/include/physical_types.h /^ int num_annotations;$/;" m struct:s_interconnect +num_annotations SRC/include/physical_types.h /^ int num_annotations;$/;" m struct:s_pb_type +num_bl SRC/fpga_spice_include/spice_types.h /^ int num_bl; \/* Number of Bit Lines in total *\/$/;" m struct:s_mem_bank_info +num_blocks SRC/include/cad_types.h /^ int num_blocks; \/* number of blocks in pattern *\/$/;" m struct:s_pack_patterns +num_cb_switch SRC/include/physical_types.h /^ int num_cb_switch;$/;" m struct:s_arch +num_class SRC/include/physical_types.h /^ int num_class;$/;" m struct:s_type_descriptor +num_clock_pins SRC/include/physical_types.h /^ int *num_clock_pins; \/* [0..num_clock_ports - 1] *\/$/;" m struct:s_pb_graph_node +num_clock_pins SRC/include/physical_types.h /^ int num_clock_pins;$/;" m struct:s_pb_type +num_clock_ports SRC/include/physical_types.h /^ int num_clock_ports;$/;" m struct:s_pb_graph_node +num_clocks SRC/fpga_spice_include/spice_types.h /^ int num_clocks;$/;" m struct:s_spice_stimulate_params +num_connectable_primtive_input_pins SRC/include/physical_types.h /^ int *num_connectable_primtive_input_pins; \/* [0..depth-1] number of input pins that this output pin can reach without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin +num_data_input SRC/fpga_spice_include/spice_types.h /^ int num_data_input; \/* Inputs for multiplexing datapath signals*\/ $/;" m struct:s_spice_mux_arch +num_delay_info SRC/fpga_spice_include/spice_types.h /^ int num_delay_info;$/;" m struct:s_spice_model +num_directs SRC/include/physical_types.h /^ int num_directs;$/;" m struct:s_arch +num_drivers SRC/include/physical_types.h /^ int num_drivers;$/;" m struct:s_type_descriptor +num_global_clocks SRC/include/physical_types.h /^ int num_global_clocks;$/;" m struct:s_clock_arch +num_grid_loc_def SRC/include/physical_types.h /^ int num_grid_loc_def;$/;" m struct:s_type_descriptor +num_include_netlist SRC/fpga_spice_include/spice_types.h /^ int num_include_netlist;$/;" m struct:s_spice +num_input SRC/fpga_spice_include/spice_types.h /^ int num_input; \/* All Inputs including those connect to constant generator *\/$/;" m struct:s_spice_mux_arch +num_input_basis SRC/fpga_spice_include/spice_types.h /^ int num_input_basis;$/;" m struct:s_spice_mux_arch +num_input_edges SRC/include/physical_types.h /^ int num_input_edges;$/;" m struct:s_pb_graph_pin +num_input_last_level SRC/fpga_spice_include/spice_types.h /^ int num_input_last_level;$/;" m struct:s_spice_mux_arch +num_input_per_level SRC/fpga_spice_include/spice_types.h /^ int* num_input_per_level; \/* [0...num_level] *\/$/;" m struct:s_spice_mux_arch +num_input_pin_class SRC/include/physical_types.h /^ int num_input_pin_class; \/* number of pin classes that this input pb_graph_node has *\/$/;" m struct:s_pb_graph_node +num_input_pins SRC/include/physical_types.h /^ int *num_input_pins; \/* [0..num_input_ports - 1] *\/$/;" m struct:s_pb_graph_node +num_input_pins SRC/include/physical_types.h /^ int num_input_pins; \/* inputs not including clock pins *\/$/;" m struct:s_pb_type +num_input_pins SRC/include/physical_types.h /^ int num_input_pins;$/;" m struct:s_pb_graph_edge +num_input_ports SRC/include/physical_types.h /^ int num_input_ports;$/;" m struct:s_interconnect_power +num_input_ports SRC/include/physical_types.h /^ int num_input_ports;$/;" m struct:s_pb_graph_node +num_interconnect SRC/include/physical_types.h /^ int num_interconnect;$/;" m struct:s_mode +num_level SRC/fpga_spice_include/spice_types.h /^ int num_level;$/;" m struct:s_spice_mux_arch +num_mc_points SRC/fpga_spice_include/spice_types.h /^ int num_mc_points;$/;" m struct:s_spice_mc_params +num_mem_bit SRC/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_mem_bank_info +num_mem_bit SRC/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_scff_info +num_mem_bit SRC/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_standalone_sram_info +num_modes SRC/include/physical_types.h /^ int num_modes;$/;" m struct:s_pb_type +num_mux SRC/include/physical_types.h /^ int num_mux;$/;" m struct:s_interconnect +num_normal_switch SRC/include/arch_types_mrfpga.h /^ short num_normal_switch;$/;" m struct:s_arch_mrfpga +num_output_edges SRC/include/physical_types.h /^ int num_output_edges;$/;" m struct:s_pb_graph_pin +num_output_pin_class SRC/include/physical_types.h /^ int num_output_pin_class; \/* number of output pin classes that this pb_graph_node has *\/$/;" m struct:s_pb_graph_node +num_output_pins SRC/include/physical_types.h /^ int *num_output_pins; \/* [0..num_output_ports - 1] *\/$/;" m struct:s_pb_graph_node +num_output_pins SRC/include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_graph_edge +num_output_pins SRC/include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_type +num_output_ports SRC/include/physical_types.h /^ int num_output_ports;$/;" m struct:s_interconnect_power +num_output_ports SRC/include/physical_types.h /^ int num_output_ports;$/;" m struct:s_pb_graph_node +num_pack_patterns SRC/include/physical_types.h /^ int num_pack_patterns;$/;" m struct:s_pb_graph_edge +num_pb SRC/include/physical_types.h /^ int num_pb;$/;" m struct:s_pb_type +num_pb_type_children SRC/include/physical_types.h /^ int num_pb_type_children;$/;" m struct:s_mode +num_pin_loc_assignments SRC/include/physical_types.h /^ int **num_pin_loc_assignments; \/* [0..height-1][0..3] *\/$/;" m struct:s_type_descriptor +num_pin_timing SRC/include/physical_types.h /^ int num_pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin +num_pins SRC/include/physical_types.h /^ int num_pins;$/;" m struct:s_class +num_pins SRC/include/physical_types.h /^ int num_pins;$/;" m struct:s_port +num_pins SRC/include/physical_types.h /^ int num_pins;$/;" m struct:s_type_descriptor +num_pins_per_port SRC/include/physical_types.h /^ int num_pins_per_port;$/;" m struct:s_interconnect_power +num_port SRC/fpga_spice_include/spice_types.h /^ int num_port;$/;" m struct:s_spice_model +num_ports SRC/include/physical_types.h /^ int num_ports;$/;" m struct:s_pb_type +num_receivers SRC/include/physical_types.h /^ int num_receivers;$/;" m struct:s_type_descriptor +num_scff SRC/fpga_spice_include/spice_types.h /^ int num_scff; \/* Number of Scan-chain flip-flops *\/$/;" m struct:s_scff_info +num_segments SRC/include/physical_types.h /^ int num_segments;$/;" m struct:s_arch +num_sigma SRC/fpga_spice_include/spice_types.h /^ int num_sigma;$/;" m struct:s_spice_mc_variation_params +num_sim_clock_cycles SRC/fpga_spice_include/spice_types.h /^ int num_sim_clock_cycles;$/;" m struct:s_spicetb_info +num_spice_model SRC/fpga_spice_include/spice_types.h /^ int num_spice_model;$/;" m struct:s_spice +num_sram SRC/fpga_spice_include/spice_types.h /^ int num_sram; \/* Number of SRAMs in total *\/$/;" m struct:s_standalone_sram_info +num_switches SRC/include/physical_types.h /^ int num_switches;$/;" m struct:s_arch +num_swseg_pattern SRC/include/physical_types.h /^ int num_swseg_pattern;$/;" m struct:s_arch +num_tedges SRC/fpga_spice_include/spice_types.h /^ int* num_tedges; \/* 1-D Array, show number of tedges of each pin *\/$/;" m struct:s_spice_model_port +num_transistor_type SRC/fpga_spice_include/spice_types.h /^ int num_transistor_type;$/;" m struct:s_spice_tech_lib +num_value_prop_pairs SRC/include/physical_types.h /^ int num_value_prop_pairs;$/;" m struct:s_pin_to_pin_annotation +num_wl SRC/fpga_spice_include/spice_types.h /^ int num_wl; \/* Number of Word Lines in total *\/$/;" m struct:s_mem_bank_info +off SRC/include/ezxml.h /^ size_t off; \/* tag offset from start of parent tag character content *\/$/;" m struct:ezxml +op_clock_freq SRC/fpga_spice_include/spice_types.h /^ float op_clock_freq; \/* Operation clock frequency*\/$/;" m struct:s_spice_stimulate_params +open SRC/ezxml.c 58;" d file: +opin_switch SRC/include/physical_types.h /^ short opin_switch;$/;" m struct:s_segment_inf +opin_to_cb SRC/include/physical_types.h /^ boolean opin_to_cb;$/;" m struct:s_type_descriptor +ordered SRC/include/ezxml.h /^ ezxml_t ordered; \/* next tag, same section and depth, in original order *\/$/;" m struct:ezxml +out_file_prefix SRC/util.c /^char *out_file_prefix = NULL;$/;" v +out_port_name SRC/fpga_spice_include/spice_types.h /^ char* out_port_name;$/;" m struct:s_spice_model_delay_info +outport_link_pin SRC/include/cad_types.h /^ int outport_link_pin; \/* applicable pin of chain output port *\/$/;" m struct:s_model_chain_pattern +output_buffer SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* output_buffer;$/;" m struct:s_spice_model +output_edges SRC/include/physical_types.h /^ struct s_pb_graph_edge** output_edges; \/* [0..num_output_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge +output_link_port SRC/include/cad_types.h /^ t_model_ports *output_link_port; \/* pointer to port of chain output *\/$/;" m struct:s_model_chain_pattern +output_pin_class_size SRC/include/physical_types.h /^ int *output_pin_class_size; \/* Stores the number of pins that belong to a particular output pin class *\/$/;" m struct:s_pb_graph_node +output_pins SRC/include/physical_types.h /^ char * output_pins;$/;" m struct:s_pin_to_pin_annotation +output_pins SRC/include/physical_types.h /^ struct s_pb_graph_pin *** output_pins; \/\/ [0..num_output_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin +output_pins SRC/include/physical_types.h /^ t_pb_graph_pin **output_pins; \/* [0..num_output_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node +output_pins SRC/include/physical_types.h /^ t_pb_graph_pin **output_pins;$/;" m struct:s_pb_graph_edge +output_ports_eq_auto_detect SRC/include/physical_types.h /^ boolean output_ports_eq_auto_detect;$/;" m struct:s_type_descriptor +output_string SRC/include/physical_types.h /^ char *output_string;$/;" m struct:s_interconnect +output_thres_pct_fall SRC/fpga_spice_include/spice_types.h /^ float output_thres_pct_fall;$/;" m struct:s_spice_meas_params +output_thres_pct_rise SRC/fpga_spice_include/spice_types.h /^ float output_thres_pct_rise;$/;" m struct:s_spice_meas_params +outputs SRC/include/logic_types.h /^ t_model_ports *outputs; \/* linked list of output ports *\/$/;" m struct:s_model +pack_pattern_indices SRC/include/physical_types.h /^ int *pack_pattern_indices; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge +pack_pattern_names SRC/include/physical_types.h /^ char **pack_pattern_names; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge +parent SRC/include/ezxml.h /^ ezxml_t parent; \/* parent tag, NULL if current tag is root tag *\/$/;" m struct:ezxml +parent_mode SRC/include/physical_types.h /^ t_mode * parent_mode;$/;" m struct:s_interconnect +parent_mode SRC/include/physical_types.h /^ t_mode *parent_mode;$/;" m struct:s_pb_type +parent_mode_index SRC/include/physical_types.h /^ int parent_mode_index;$/;" m struct:s_interconnect +parent_node SRC/include/physical_types.h /^ struct s_pb_graph_node *parent_node;$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_node +parent_pb_graph_node SRC/include/physical_types.h /^ struct s_pb_graph_node *parent_pb_graph_node;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node +parent_pb_type SRC/include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type +parent_pb_type SRC/include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_port typeref:struct:s_port::s_pb_type +parent_pin_class SRC/include/physical_types.h /^ int *parent_pin_class; \/* [0..depth-1] the grouping of pins that this particular pin belongs to *\/$/;" m struct:s_pb_graph_pin +parent_spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* parent_spice_model;$/;" m struct:s_conf_bit_info +parent_spice_model_index SRC/fpga_spice_include/spice_types.h /^ int parent_spice_model_index;$/;" m struct:s_conf_bit_info +pass_gate_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_info;$/;" m struct:s_spice_model_design_tech_info +pass_gate_logic SRC/fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_logic;$/;" m struct:s_spice_model +path SRC/fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_model_netlist +path SRC/fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_tech_lib +pattern_index SRC/include/cad_types.h /^ int pattern_index; \/* index of pattern that this block is a part of *\/$/;" m struct:s_pack_pattern_block +pattern_length SRC/include/physical_types.h /^ int pattern_length;$/;" m struct:s_swseg_pattern_inf +patterns SRC/include/physical_types.h /^ boolean* patterns;$/;" m struct:s_swseg_pattern_inf +pb_graph_head SRC/include/physical_types.h /^ t_pb_graph_node *pb_graph_head;$/;" m struct:s_type_descriptor +pb_graph_node SRC/include/cad_types.h /^ t_pb_graph_node *pb_graph_node;$/;" m struct:s_cluster_placement_primitive +pb_node_power SRC/include/physical_types.h /^ t_pb_graph_node_power * pb_node_power;$/;" m struct:s_pb_graph_node +pb_type SRC/include/cad_types.h /^ const t_pb_type *pb_type; \/* pb_type that this block is an instance of *\/$/;" m struct:s_pack_pattern_block +pb_type SRC/include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_type +pb_type SRC/include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_pb_type +pb_type_children SRC/include/physical_types.h /^ struct s_pb_type *pb_type_children; \/* [0..num_child_pb_types] *\/$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type +pb_type_power SRC/include/physical_types.h /^ t_pb_type_power * pb_type_power;$/;" m struct:s_pb_type +pb_types SRC/include/logic_types.h /^ struct s_linked_vptr *pb_types; \/* Physical block types that implement this model *\/$/;" m struct:s_model typeref:struct:s_model::s_linked_vptr +peak SRC/include/physical_types.h /^ float peak;$/;" m struct:s_chan +period SRC/include/physical_types.h /^ float period; \/* Period of clock *\/$/;" m struct:s_clock_network +phy_mode_pin_rotate_offset_acc SRC/include/physical_types.h /^ int phy_mode_pin_rotate_offset_acc; \/* The pin number will rotate by an offset unit when mapping to physical modes *\/$/;" m struct:s_port +phy_pb_type SRC/include/physical_types.h /^ struct s_pb_type* phy_pb_type;$/;" m struct:s_pb_type typeref:struct:s_pb_type::s_pb_type +phy_pb_type_port SRC/include/physical_types.h /^ t_port* phy_pb_type_port;$/;" m struct:s_port +phy_pb_type_port_lsb SRC/include/physical_types.h /^ int phy_pb_type_port_lsb;$/;" m struct:s_port +phy_pb_type_port_msb SRC/include/physical_types.h /^ int phy_pb_type_port_msb;$/;" m struct:s_port +physical_mode_name SRC/include/physical_types.h /^ char* physical_mode_name;$/;" m struct:s_pb_type +physical_mode_num_conf_bits SRC/include/physical_types.h /^ int physical_mode_num_conf_bits;$/;" m struct:s_pb_type +physical_mode_num_iopads SRC/include/physical_types.h /^ int physical_mode_num_iopads;$/;" m struct:s_pb_type +physical_mode_num_reserved_conf_bits SRC/include/physical_types.h /^ int physical_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type +physical_mode_pin SRC/include/physical_types.h /^ char* physical_mode_pin;$/;" m struct:s_port +physical_mode_pin_rotate_offset SRC/include/physical_types.h /^ int physical_mode_pin_rotate_offset; \/* The pin number will rotate by an offset unit when mapping to physical modes *\/$/;" m struct:s_port +physical_pb_graph_node SRC/include/physical_types.h /^ t_pb_graph_node* physical_pb_graph_node; \/* physical pb_graph_node *\/$/;" m struct:s_pb_graph_node +physical_pb_graph_pin SRC/include/physical_types.h /^ t_pb_graph_pin* physical_pb_graph_pin;$/;" m struct:s_pb_graph_pin +physical_pb_type_index_factor SRC/include/physical_types.h /^ float physical_pb_type_index_factor;$/;" m struct:s_pb_type +physical_pb_type_index_offset SRC/include/physical_types.h /^ int physical_pb_type_index_offset;$/;" m struct:s_pb_type +physical_pb_type_name SRC/include/physical_types.h /^ char* physical_pb_type_name;$/;" m struct:s_pb_type +pi SRC/include/ezxml.h /^ char ***pi; \/* processing instructions *\/$/;" m struct:ezxml_root +pin_class SRC/include/physical_types.h /^ int *pin_class; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +pin_class SRC/include/physical_types.h /^ int pin_class;$/;" m struct:s_pb_graph_pin +pin_count_in_cluster SRC/include/physical_types.h /^ int pin_count_in_cluster;$/;" m struct:s_pb_graph_pin +pin_height SRC/include/physical_types.h /^ int *pin_height; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +pin_index_per_side SRC/include/physical_types.h /^ int* pin_index_per_side;$/;" m struct:s_type_descriptor +pin_loc_assignments SRC/include/physical_types.h /^ char ****pin_loc_assignments; \/* [0..height-1][0..3][0..num_tokens-1][0..string_name] *\/$/;" m struct:s_type_descriptor +pin_location_distribution SRC/include/physical_types.h /^ enum e_pin_location_distr pin_location_distribution;$/;" m struct:s_type_descriptor typeref:enum:s_type_descriptor::e_pin_location_distr +pin_number SRC/include/physical_types.h /^ int pin_number;$/;" m struct:s_pb_graph_pin +pin_power SRC/include/physical_types.h /^ t_pb_graph_pin_power * pin_power;$/;" m struct:s_pb_graph_pin +pin_ptc_to_side SRC/include/physical_types.h /^ int* pin_ptc_to_side;$/;" m struct:s_type_descriptor +pin_timing SRC/include/physical_types.h /^ struct s_pb_graph_pin** pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin +pin_timing_del_max SRC/include/physical_types.h /^ float *pin_timing_del_max; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin +pin_toggle_initialized SRC/include/physical_types.h /^ boolean pin_toggle_initialized;$/;" m struct:s_port_power +pinlist SRC/include/physical_types.h /^ int *pinlist; \/* [0..num_pins - 1] *\/$/;" m struct:s_class +pinloc SRC/include/physical_types.h /^ int ***pinloc; \/* [0..height-1][0..3][0..num_pins-1] *\/$/;" m struct:s_type_descriptor +placement_index SRC/include/physical_types.h /^ int placement_index;$/;" m struct:s_pb_graph_node +placement_index_in_top_node SRC/include/physical_types.h /^ int placement_index_in_top_node; \/* index at the top-level pb_graph node *\/$/;" m struct:s_pb_graph_node +pmos_size SRC/fpga_spice_include/spice_types.h /^ float pmos_size;$/;" m struct:s_spice_model_pass_gate_logic +pn_ratio SRC/fpga_spice_include/spice_types.h /^ float pn_ratio;$/;" m struct:s_spice_tech_lib +port SRC/include/physical_types.h /^ t_port *port;$/;" m struct:s_pb_graph_pin +port_class SRC/include/physical_types.h /^ char * port_class;$/;" m struct:s_port +port_index_by_type SRC/include/physical_types.h /^ int port_index_by_type;$/;" m struct:s_port +port_info_initialized SRC/include/physical_types.h /^ boolean port_info_initialized;$/;" m struct:s_interconnect_power +port_power SRC/include/physical_types.h /^ t_port_power * port_power;$/;" m struct:s_port +ports SRC/fpga_spice_include/spice_types.h /^ t_spice_model_port* ports;$/;" m struct:s_spice_model +ports SRC/include/physical_types.h /^ t_port *ports; \/* [0..num_ports] *\/$/;" m struct:s_pb_type +post SRC/fpga_spice_include/spice_types.h /^ int post;$/;" m struct:s_spice_params +power SRC/include/physical_types.h /^ t_power_arch * power;$/;" m struct:s_arch +power_buffer_size SRC/include/physical_types.h /^ float power_buffer_size;$/;" m struct:s_switch_inf +power_buffer_type SRC/include/physical_types.h /^ e_power_buffer_type power_buffer_type;$/;" m struct:s_switch_inf +power_gated SRC/fpga_spice_include/spice_types.h /^ boolean power_gated;$/;" m struct:s_spice_model_design_tech_info +power_method_inherited SRC/read_xml_arch_file.c /^e_power_estimation_method power_method_inherited($/;" f +power_usage SRC/include/physical_types.h /^ t_power_usage power_usage; \/* Power usage of this mode *\/$/;" m struct:s_mode_power +power_usage SRC/include/physical_types.h /^ t_power_usage power_usage; \/* Total power usage of this pb type *\/$/;" m struct:s_pb_type_power +power_usage SRC/include/physical_types.h /^ t_power_usage power_usage;$/;" m struct:s_interconnect_power +power_usage_bufs_wires SRC/include/physical_types.h /^ t_power_usage power_usage_bufs_wires; \/* Power dissipated in local buffers and wire switching (Subset of total power) *\/$/;" m struct:s_pb_type_power +prefix SRC/fpga_spice_include/spice_types.h /^ char* prefix; $/;" m struct:s_spice_model_port +prefix SRC/fpga_spice_include/spice_types.h /^ char* prefix; \/* Prefix when it show up in the spice netlist *\/$/;" m struct:s_spice_model +print_help SRC/main.c /^void print_help() {$/;" f +print_int_matrix3 SRC/util.c /^void print_int_matrix3(int ***vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f +priority SRC/include/physical_types.h /^ int priority;$/;" m struct:s_grid_loc_def +prob SRC/include/physical_types.h /^ float prob; \/* Static probability of net assigned to this clock *\/$/;" m struct:s_clock_network +probability SRC/fpga_spice_include/spice_types.h /^ float probability;$/;" m struct:s_spice_net_info +prog_clock_freq SRC/fpga_spice_include/spice_types.h /^ float prog_clock_freq; \/* Programming clock frequency, used during programming phase only *\/$/;" m struct:s_spice_stimulate_params +prop SRC/include/physical_types.h /^ int * prop; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation +pwh SRC/fpga_spice_include/spice_types.h /^ float pwh;$/;" m struct:s_spice_net_info +pwl SRC/fpga_spice_include/spice_types.h /^ float pwl;$/;" m struct:s_spice_net_info +read SRC/ezxml.c 59;" d file: +read_xml_spice SRC/include/physical_types.h /^ boolean read_xml_spice;$/;" m struct:s_arch +relative_length SRC/include/physical_types.h /^ float relative_length;$/;" m union:s_port_power::__anon3 +remove_llist_node SRC/linkedlist.c /^void remove_llist_node(t_llist* cur) { $/;" f +repeat SRC/include/physical_types.h /^ int repeat;$/;" m struct:s_grid_loc_def +res_val SRC/fpga_spice_include/spice_types.h /^ float res_val;$/;" m struct:s_spice_model_wire_param +reserved_bl SRC/fpga_spice_include/spice_types.h /^ int reserved_bl; \/* Number of reserved BLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info +reserved_wl SRC/fpga_spice_include/spice_types.h /^ int reserved_wl; \/* Number of reserved WLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info +reverse_llist SRC/linkedlist.c /^t_llist* reverse_llist(t_llist* head) {$/;" f +reverse_scaled SRC/include/physical_types.h /^ boolean reverse_scaled; \/* Scale by (1-prob) *\/$/;" m struct:s_port_power +roff SRC/fpga_spice_include/spice_types.h /^ float roff;$/;" m struct:s_spice_model_rram +ron SRC/fpga_spice_include/spice_types.h /^ float ron;$/;" m struct:s_spice_model_rram +root_block SRC/include/cad_types.h /^ t_pack_pattern_block *root_block; \/* root block used by this pattern *\/$/;" m struct:s_pack_patterns +rotate_clockwise SRC/sides.cpp /^void Side::rotate_clockwise() {$/;" f class:Side +rotate_counterclockwise SRC/sides.cpp /^void Side::rotate_counterclockwise() {$/;" f class:Side +rr_node_index_physical_pb SRC/include/physical_types.h /^ int rr_node_index_physical_pb; \/* rr_node in the physical pb rr_graph*\/$/;" m struct:s_pb_graph_pin +rram_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_rram* rram_info;$/;" m struct:s_spice_model_design_tech_info +rram_pass_tran_value SRC/include/arch_types_mrfpga.h /^ float rram_pass_tran_value;$/;" m struct:s_arch_mrfpga +rram_variation SRC/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params rram_variation;$/;" m struct:s_spice_mc_params +s SRC/include/ezxml.h /^ char *s; \/* start of work area *\/$/;" m struct:ezxml_root +s_arch SRC/include/physical_types.h /^struct s_arch {$/;" s +s_arch_mrfpga SRC/include/arch_types_mrfpga.h /^struct s_arch_mrfpga {$/;" s +s_buffer_inf SRC/include/arch_types_mrfpga.h /^struct s_buffer_inf { $/;" s +s_chan SRC/include/physical_types.h /^typedef struct s_chan {$/;" s +s_chan_width_dist SRC/include/physical_types.h /^typedef struct s_chan_width_dist {$/;" s +s_chunk SRC/include/util.h /^typedef struct s_chunk {$/;" s +s_class SRC/include/physical_types.h /^struct s_class {$/;" s +s_clb_grid SRC/include/physical_types.h /^struct s_clb_grid {$/;" s +s_clock_arch SRC/include/physical_types.h /^struct s_clock_arch {$/;" s +s_clock_network SRC/include/physical_types.h /^struct s_clock_network {$/;" s +s_cluster_placement_primitive SRC/include/cad_types.h /^typedef struct s_cluster_placement_primitive {$/;" s +s_conf_bit SRC/fpga_spice_include/spice_types.h /^struct s_conf_bit {$/;" s +s_conf_bit_info SRC/fpga_spice_include/spice_types.h /^struct s_conf_bit_info {$/;" s +s_direct_inf SRC/include/physical_types.h /^typedef struct s_direct_inf {$/;" s +s_grid_loc_def SRC/include/physical_types.h /^typedef struct s_grid_loc_def {$/;" s +s_interconnect SRC/include/physical_types.h /^struct s_interconnect {$/;" s +s_interconnect_pins SRC/include/physical_types.h /^struct s_interconnect_pins {$/;" s +s_interconnect_power SRC/include/physical_types.h /^struct s_interconnect_power {$/;" s +s_ivec SRC/include/util.h /^typedef struct s_ivec {$/;" s +s_linked_int SRC/include/util.h /^typedef struct s_linked_int {$/;" s +s_linked_vptr SRC/include/util.h /^typedef struct s_linked_vptr {$/;" s +s_llist SRC/fpga_spice_include/linkedlist.h /^struct s_llist$/;" s +s_mem_bank_info SRC/fpga_spice_include/spice_types.h /^struct s_mem_bank_info {$/;" s +s_memristor_inf SRC/include/arch_types_mrfpga.h /^struct s_memristor_inf { $/;" s +s_mode SRC/include/physical_types.h /^struct s_mode {$/;" s +s_mode_power SRC/include/physical_types.h /^struct s_mode_power {$/;" s +s_model SRC/include/logic_types.h /^typedef struct s_model {$/;" s +s_model_chain_pattern SRC/include/cad_types.h /^typedef struct s_model_chain_pattern {$/;" s +s_model_ports SRC/include/logic_types.h /^typedef struct s_model_ports {$/;" s +s_pack_pattern_block SRC/include/cad_types.h /^typedef struct s_pack_pattern_block {$/;" s +s_pack_pattern_connections SRC/include/cad_types.h /^typedef struct s_pack_pattern_connections {$/;" s +s_pack_patterns SRC/include/cad_types.h /^typedef struct s_pack_patterns {$/;" s +s_pb_graph_edge SRC/include/physical_types.h /^struct s_pb_graph_edge {$/;" s +s_pb_graph_node SRC/include/physical_types.h /^struct s_pb_graph_node {$/;" s +s_pb_graph_node_power SRC/include/physical_types.h /^struct s_pb_graph_node_power {$/;" s +s_pb_graph_pin SRC/include/physical_types.h /^struct s_pb_graph_pin {$/;" s +s_pb_graph_pin_power SRC/include/physical_types.h /^struct s_pb_graph_pin_power {$/;" s +s_pb_type SRC/include/physical_types.h /^struct s_pb_type {$/;" s +s_pb_type_power SRC/include/physical_types.h /^struct s_pb_type_power {$/;" s +s_pin_to_pin_annotation SRC/include/physical_types.h /^struct s_pin_to_pin_annotation {$/;" s +s_port SRC/include/physical_types.h /^struct s_port {$/;" s +s_port_power SRC/include/physical_types.h /^struct s_port_power {$/;" s +s_power_arch SRC/include/physical_types.h /^struct s_power_arch {$/;" s +s_power_usage SRC/include/physical_types.h /^struct s_power_usage {$/;" s +s_reserved_syntax_char SRC/fpga_spice_include/spice_types.h /^struct s_reserved_syntax_char {$/;" s +s_scff_info SRC/fpga_spice_include/spice_types.h /^struct s_scff_info {$/;" s +s_segment_inf SRC/include/physical_types.h /^typedef struct s_segment_inf {$/;" s +s_spice SRC/fpga_spice_include/spice_types.h /^struct s_spice {$/;" s +s_spice_mc_params SRC/fpga_spice_include/spice_types.h /^struct s_spice_mc_params {$/;" s +s_spice_mc_variation_params SRC/fpga_spice_include/spice_types.h /^struct s_spice_mc_variation_params {$/;" s +s_spice_meas_params SRC/fpga_spice_include/spice_types.h /^struct s_spice_meas_params {$/;" s +s_spice_model SRC/fpga_spice_include/spice_types.h /^struct s_spice_model {$/;" s +s_spice_model_buffer SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_buffer {$/;" s +s_spice_model_delay_info SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_delay_info {$/;" s +s_spice_model_design_tech_info SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_design_tech_info {$/;" s +s_spice_model_gate SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_gate {$/;" s +s_spice_model_lut SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_lut {$/;" s +s_spice_model_mux SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_mux {$/;" s +s_spice_model_netlist SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_netlist {$/;" s +s_spice_model_pass_gate_logic SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_pass_gate_logic {$/;" s +s_spice_model_port SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_port {$/;" s +s_spice_model_rram SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_rram {$/;" s +s_spice_model_tedge SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_tedge {$/;" s +s_spice_model_wire_param SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_wire_param {$/;" s +s_spice_mux_arch SRC/fpga_spice_include/spice_types.h /^struct s_spice_mux_arch {$/;" s +s_spice_mux_model SRC/fpga_spice_include/spice_types.h /^struct s_spice_mux_model {$/;" s +s_spice_net_info SRC/fpga_spice_include/spice_types.h /^struct s_spice_net_info {$/;" s +s_spice_params SRC/fpga_spice_include/spice_types.h /^struct s_spice_params {$/;" s +s_spice_stimulate_params SRC/fpga_spice_include/spice_types.h /^struct s_spice_stimulate_params {$/;" s +s_spice_tech_lib SRC/fpga_spice_include/spice_types.h /^struct s_spice_tech_lib {$/;" s +s_spice_transistor_type SRC/fpga_spice_include/spice_types.h /^struct s_spice_transistor_type {$/;" s +s_spicetb_info SRC/fpga_spice_include/spice_types.h /^struct s_spicetb_info {$/;" s +s_sram_inf SRC/fpga_spice_include/spice_types.h /^struct s_sram_inf {$/;" s +s_sram_inf_orgz SRC/fpga_spice_include/spice_types.h /^struct s_sram_inf_orgz {$/;" s +s_sram_orgz_info SRC/fpga_spice_include/spice_types.h /^struct s_sram_orgz_info {$/;" s +s_standalone_sram_info SRC/fpga_spice_include/spice_types.h /^struct s_standalone_sram_info {$/;" s +s_switch_inf SRC/include/physical_types.h /^typedef struct s_switch_inf {$/;" s +s_swseg_pattern_inf SRC/include/physical_types.h /^struct s_swseg_pattern_inf {$/;" s +s_timing_inf SRC/include/physical_types.h /^typedef struct s_timing_inf {$/;" s +s_type_descriptor SRC/include/physical_types.h /^struct s_type_descriptor \/* TODO rename this. maybe physical type descriptor or complex logic block or physical logic block*\/$/;" s +sb SRC/include/physical_types.h /^ boolean *sb;$/;" m struct:s_segment_inf +sb_index_high SRC/fpga_spice_include/spice_types.h /^ int** sb_index_high;$/;" m struct:s_spice_model +sb_index_low SRC/fpga_spice_include/spice_types.h /^ int** sb_index_low;$/;" m struct:s_spice_model +sb_len SRC/include/physical_types.h /^ int sb_len;$/;" m struct:s_segment_inf +scaled_by_pin SRC/include/physical_types.h /^ t_pb_graph_pin * scaled_by_pin;$/;" m struct:s_pb_graph_pin_power +scaled_by_port SRC/include/physical_types.h /^ t_port * scaled_by_port;$/;" m struct:s_port_power +scaled_by_port_pin_idx SRC/include/physical_types.h /^ int scaled_by_port_pin_idx;$/;" m struct:s_port_power +scff_info SRC/fpga_spice_include/spice_types.h /^ t_scff_info* scff_info; \/* Only be allocated when orgz type is scan-chain *\/$/;" m struct:s_sram_orgz_info +scratch_pad SRC/include/physical_types.h /^ int scratch_pad; \/* temporary data structure useful to store traversal info *\/$/;" m struct:s_pb_graph_pin +search_in_int_list SRC/util.c /^t_linked_int* search_in_int_list(t_linked_int* int_list_head, $/;" f +search_llist_tail SRC/linkedlist.c /^t_llist* search_llist_tail(t_llist* head) {$/;" f +seg_direction_type SRC/include/physical_types.h /^ enum e_directionality seg_direction_type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_directionality +seg_length SRC/include/physical_types.h /^ int seg_length;$/;" m struct:s_swseg_pattern_inf +seg_switch SRC/include/physical_types.h /^ short seg_switch;$/;" m struct:s_segment_inf +set_opposite SRC/sides.cpp /^void Side::set_opposite() { $/;" f class:Side +set_side SRC/sides.cpp /^void Side::set_side(enum e_side side) { $/;" f class:Side +set_side SRC/sides.cpp /^void Side::set_side(size_t side) { $/;" f class:Side +sibling SRC/include/ezxml.h /^ ezxml_t sibling; \/* next tag with different name in same section and depth *\/$/;" m struct:ezxml +side_ SRC/include/sides.h /^ enum e_side side_; $/;" m class:Side typeref:enum:Side::e_side +sim_clock_freq_slack SRC/fpga_spice_include/spice_types.h /^ float sim_clock_freq_slack;$/;" m struct:s_spice_stimulate_params +sim_num_clock_cycle SRC/fpga_spice_include/spice_types.h /^ int sim_num_clock_cycle; \/* Number of clock cycle in simulation *\/$/;" m struct:s_spice_meas_params +sim_temp SRC/fpga_spice_include/spice_types.h /^ int sim_temp; \/* Simulation Temperature*\/$/;" m struct:s_spice_params +size SRC/fpga_spice_include/spice_types.h /^ float size;$/;" m struct:s_spice_model_buffer +size SRC/fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_model_port +size SRC/fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_mux_model +size SRC/include/logic_types.h /^ int size; \/* maximum number of pins *\/$/;" m struct:s_model_ports +slew_fall SRC/fpga_spice_include/spice_types.h /^ float slew_fall;$/;" m struct:s_spice_net_info +slew_lower_thres_pct_fall SRC/fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_fall;$/;" m struct:s_spice_meas_params +slew_lower_thres_pct_rise SRC/fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_rise;$/;" m struct:s_spice_meas_params +slew_rise SRC/fpga_spice_include/spice_types.h /^ float slew_rise;$/;" m struct:s_spice_net_info +slew_upper_thres_pct_fall SRC/fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_fall;$/;" m struct:s_spice_meas_params +slew_upper_thres_pct_rise SRC/fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_rise;$/;" m struct:s_spice_meas_params +snprintf SRC/ezxml.c 57;" d file: +spice SRC/include/physical_types.h /^ t_spice* spice;$/;" m struct:s_arch +spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz +spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_buffer +spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_pass_gate_logic +spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_port +spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_mux_model +spice_model SRC/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_direct_inf +spice_model SRC/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_interconnect +spice_model SRC/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_pb_type +spice_model SRC/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_segment_inf +spice_model SRC/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_switch_inf +spice_model_delay_type SRC/fpga_spice_include/spice_types.h /^enum spice_model_delay_type {$/;" g +spice_model_name SRC/fpga_spice_include/spice_types.h /^ char* spice_model_name; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz +spice_model_name SRC/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_buffer +spice_model_name SRC/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_pass_gate_logic +spice_model_name SRC/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_port +spice_model_name SRC/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_direct_inf +spice_model_name SRC/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_interconnect +spice_model_name SRC/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_pb_type +spice_model_name SRC/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_segment_inf +spice_model_name SRC/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_switch_inf +spice_model_port SRC/include/physical_types.h /^ t_spice_model_port* spice_model_port;$/;" m struct:s_port +spice_model_sram_offset SRC/include/physical_types.h /^ int spice_model_sram_offset;$/;" m struct:s_interconnect +spice_model_sram_offset SRC/include/physical_types.h /^ int spice_model_sram_offset;$/;" m struct:s_pb_type +spice_models SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_models;$/;" m struct:s_spice +spice_mux_arch SRC/fpga_spice_include/spice_types.h /^ t_spice_mux_arch* spice_mux_arch;$/;" m struct:s_spice_mux_model +spice_params SRC/fpga_spice_include/spice_types.h /^ t_spice_params spice_params;$/;" m struct:s_spice +spice_reserved SRC/fpga_spice_include/spice_types.h /^ boolean spice_reserved;$/;" m struct:s_reserved_syntax_char +spice_sram_inf_orgz SRC/fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* spice_sram_inf_orgz;$/;" m struct:s_sram_inf +spot_int_in_array SRC/util.c /^int spot_int_in_array(int array_len, int* array,$/;" f +sram_bit SRC/fpga_spice_include/spice_types.h /^ t_conf_bit* sram_bit;$/;" m struct:s_conf_bit_info +sram_inf SRC/include/physical_types.h /^ t_sram_inf sram_inf;$/;" m struct:s_arch +standalone SRC/include/ezxml.h /^ short standalone; \/* non-zero if *\/$/;" m struct:ezxml_root +standalone_sram_info SRC/fpga_spice_include/spice_types.h /^ t_standalone_sram_info* standalone_sram_info; \/* Only be allocated when orgz type is standalone *\/$/;" m struct:s_sram_orgz_info +start_col SRC/include/physical_types.h /^ int start_col;$/;" m struct:s_grid_loc_def +start_seg_switch SRC/include/arch_types_mrfpga.h /^ short start_seg_switch;$/;" m struct:s_arch_mrfpga +stimulate_params SRC/fpga_spice_include/spice_types.h /^ t_spice_stimulate_params stimulate_params;$/;" m struct:s_spice_params +structure SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_model_mux typeref:enum:s_spice_model_mux::e_spice_model_structure +structure SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_mux_arch typeref:enum:s_spice_mux_arch::e_spice_model_structure +structure SRC/include/physical_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_switch_inf typeref:enum:s_switch_inf::e_spice_model_structure +switch_num_level SRC/include/physical_types.h /^ int switch_num_level;$/;" m struct:s_switch_inf +swseg_patterns SRC/include/physical_types.h /^ t_swseg_pattern_inf* swseg_patterns;$/;" m struct:s_arch +syntax_char SRC/fpga_spice_include/spice_types.h /^ char syntax_char;$/;" m struct:s_reserved_syntax_char +t_arch SRC/include/physical_types.h /^typedef struct s_arch t_arch;$/;" t typeref:struct:s_arch +t_arch_mrfpga SRC/include/arch_types_mrfpga.h /^typedef struct s_arch_mrfpga t_arch_mrfpga;$/;" t typeref:struct:s_arch_mrfpga +t_buffer_inf SRC/include/arch_types_mrfpga.h /^typedef struct s_buffer_inf t_buffer_inf;$/;" t typeref:struct:s_buffer_inf +t_chan SRC/include/physical_types.h /^} t_chan;$/;" t typeref:struct:s_chan +t_chan_width_dist SRC/include/physical_types.h /^} t_chan_width_dist;$/;" t typeref:struct:s_chan_width_dist +t_chunk SRC/include/util.h /^} t_chunk;$/;" t typeref:struct:s_chunk +t_class SRC/include/physical_types.h /^typedef struct s_class t_class;$/;" t typeref:struct:s_class +t_clock_arch SRC/include/physical_types.h /^typedef struct s_clock_arch t_clock_arch;$/;" t typeref:struct:s_clock_arch +t_clock_network SRC/include/physical_types.h /^typedef struct s_clock_network t_clock_network;$/;" t typeref:struct:s_clock_network +t_cluster_placement_primitive SRC/include/cad_types.h /^} t_cluster_placement_primitive;$/;" t typeref:struct:s_cluster_placement_primitive +t_conf_bit SRC/fpga_spice_include/spice_types.h /^typedef struct s_conf_bit t_conf_bit;$/;" t typeref:struct:s_conf_bit +t_conf_bit_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_conf_bit_info t_conf_bit_info;$/;" t typeref:struct:s_conf_bit_info +t_direct_inf SRC/include/physical_types.h /^} t_direct_inf;$/;" t typeref:struct:s_direct_inf +t_grid_loc_def SRC/include/physical_types.h /^} t_grid_loc_def;$/;" t typeref:struct:s_grid_loc_def +t_interconnect SRC/include/physical_types.h /^typedef struct s_interconnect t_interconnect;$/;" t typeref:struct:s_interconnect +t_interconnect_pins SRC/include/physical_types.h /^typedef struct s_interconnect_pins t_interconnect_pins;$/;" t typeref:struct:s_interconnect_pins +t_interconnect_power SRC/include/physical_types.h /^typedef struct s_interconnect_power t_interconnect_power;$/;" t typeref:struct:s_interconnect_power +t_ivec SRC/include/util.h /^} t_ivec;$/;" t typeref:struct:s_ivec +t_linked_int SRC/include/util.h /^} t_linked_int;$/;" t typeref:struct:s_linked_int +t_linked_vptr SRC/include/util.h /^} t_linked_vptr;$/;" t typeref:struct:s_linked_vptr +t_llist SRC/fpga_spice_include/linkedlist.h /^typedef struct s_llist t_llist;$/;" t typeref:struct:s_llist +t_mem_bank_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_mem_bank_info t_mem_bank_info;$/;" t typeref:struct:s_mem_bank_info +t_memristor_inf SRC/include/arch_types_mrfpga.h /^typedef struct s_memristor_inf t_memristor_inf;$/;" t typeref:struct:s_memristor_inf +t_mode SRC/include/physical_types.h /^typedef struct s_mode t_mode;$/;" t typeref:struct:s_mode +t_mode_power SRC/include/physical_types.h /^typedef struct s_mode_power t_mode_power;$/;" t typeref:struct:s_mode_power +t_model SRC/include/logic_types.h /^} t_model;$/;" t typeref:struct:s_model +t_model_chain_pattern SRC/include/cad_types.h /^} t_model_chain_pattern;$/;" t typeref:struct:s_model_chain_pattern +t_model_ports SRC/include/logic_types.h /^} t_model_ports;$/;" t typeref:struct:s_model_ports +t_pack_pattern_block SRC/include/cad_types.h /^} t_pack_pattern_block;$/;" t typeref:struct:s_pack_pattern_block +t_pack_pattern_connections SRC/include/cad_types.h /^} t_pack_pattern_connections;$/;" t typeref:struct:s_pack_pattern_connections +t_pack_patterns SRC/include/cad_types.h /^} t_pack_patterns;$/;" t typeref:struct:s_pack_patterns +t_pb_graph_edge SRC/include/physical_types.h /^typedef struct s_pb_graph_edge t_pb_graph_edge;$/;" t typeref:struct:s_pb_graph_edge +t_pb_graph_node SRC/include/physical_types.h /^typedef struct s_pb_graph_node t_pb_graph_node;$/;" t typeref:struct:s_pb_graph_node +t_pb_graph_node_power SRC/include/physical_types.h /^typedef struct s_pb_graph_node_power t_pb_graph_node_power;$/;" t typeref:struct:s_pb_graph_node_power +t_pb_graph_pin SRC/include/physical_types.h /^typedef struct s_pb_graph_pin t_pb_graph_pin;$/;" t typeref:struct:s_pb_graph_pin +t_pb_graph_pin_power SRC/include/physical_types.h /^typedef struct s_pb_graph_pin_power t_pb_graph_pin_power;$/;" t typeref:struct:s_pb_graph_pin_power +t_pb_type SRC/include/physical_types.h /^typedef struct s_pb_type t_pb_type;$/;" t typeref:struct:s_pb_type +t_pb_type_power SRC/include/physical_types.h /^typedef struct s_pb_type_power t_pb_type_power;$/;" t typeref:struct:s_pb_type_power +t_pin_to_pin_annotation SRC/include/physical_types.h /^typedef struct s_pin_to_pin_annotation t_pin_to_pin_annotation;$/;" t typeref:struct:s_pin_to_pin_annotation +t_port SRC/include/physical_types.h /^typedef struct s_port t_port;$/;" t typeref:struct:s_port +t_port_power SRC/include/physical_types.h /^typedef struct s_port_power t_port_power;$/;" t typeref:struct:s_port_power +t_power_arch SRC/include/physical_types.h /^typedef struct s_power_arch t_power_arch;$/;" t typeref:struct:s_power_arch +t_power_estimation_method SRC/include/physical_types.h /^typedef enum e_power_estimation_method_ t_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ +t_power_usage SRC/include/physical_types.h /^typedef struct s_power_usage t_power_usage;$/;" t typeref:struct:s_power_usage +t_reserved_syntax_char SRC/fpga_spice_include/spice_types.h /^typedef struct s_reserved_syntax_char t_reserved_syntax_char;$/;" t typeref:struct:s_reserved_syntax_char +t_scff_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_scff_info t_scff_info;$/;" t typeref:struct:s_scff_info +t_segment_inf SRC/include/physical_types.h /^} t_segment_inf;$/;" t typeref:struct:s_segment_inf +t_spice SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice t_spice;$/;" t typeref:struct:s_spice +t_spice_mc_params SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_params t_spice_mc_params;$/;" t typeref:struct:s_spice_mc_params +t_spice_mc_variation_params SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_variation_params t_spice_mc_variation_params;$/;" t typeref:struct:s_spice_mc_variation_params +t_spice_meas_params SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_meas_params t_spice_meas_params;$/;" t typeref:struct:s_spice_meas_params +t_spice_model SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model t_spice_model;$/;" t typeref:struct:s_spice_model +t_spice_model_buffer SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_buffer t_spice_model_buffer;$/;" t typeref:struct:s_spice_model_buffer +t_spice_model_delay_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_delay_info t_spice_model_delay_info;$/;" t typeref:struct:s_spice_model_delay_info +t_spice_model_design_tech_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_design_tech_info t_spice_model_design_tech_info;$/;" t typeref:struct:s_spice_model_design_tech_info +t_spice_model_gate SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_gate t_spice_model_gate;$/;" t typeref:struct:s_spice_model_gate +t_spice_model_lut SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_lut t_spice_model_lut;$/;" t typeref:struct:s_spice_model_lut +t_spice_model_mux SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_mux t_spice_model_mux;$/;" t typeref:struct:s_spice_model_mux +t_spice_model_netlist SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_netlist t_spice_model_netlist;$/;" t typeref:struct:s_spice_model_netlist +t_spice_model_pass_gate_logic SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_pass_gate_logic t_spice_model_pass_gate_logic;$/;" t typeref:struct:s_spice_model_pass_gate_logic +t_spice_model_port SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_port t_spice_model_port;$/;" t typeref:struct:s_spice_model_port +t_spice_model_rram SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_rram t_spice_model_rram;$/;" t typeref:struct:s_spice_model_rram +t_spice_model_tedge SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_tedge t_spice_model_tedge;$/;" t typeref:struct:s_spice_model_tedge +t_spice_model_wire_param SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_wire_param t_spice_model_wire_param;$/;" t typeref:struct:s_spice_model_wire_param +t_spice_mux_arch SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_arch t_spice_mux_arch;$/;" t typeref:struct:s_spice_mux_arch +t_spice_mux_model SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_model t_spice_mux_model;$/;" t typeref:struct:s_spice_mux_model +t_spice_net_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_net_info t_spice_net_info;$/;" t typeref:struct:s_spice_net_info +t_spice_params SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_params t_spice_params;$/;" t typeref:struct:s_spice_params +t_spice_stimulate_params SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_stimulate_params t_spice_stimulate_params;$/;" t typeref:struct:s_spice_stimulate_params +t_spice_tech_lib SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_tech_lib t_spice_tech_lib;$/;" t typeref:struct:s_spice_tech_lib +t_spice_transistor_type SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_transistor_type t_spice_transistor_type;$/;" t typeref:struct:s_spice_transistor_type +t_spicetb_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_spicetb_info t_spicetb_info;$/;" t typeref:struct:s_spicetb_info +t_sram_inf SRC/fpga_spice_include/spice_types.h /^typedef struct s_sram_inf t_sram_inf;$/;" t typeref:struct:s_sram_inf +t_sram_inf_orgz SRC/fpga_spice_include/spice_types.h /^typedef struct s_sram_inf_orgz t_sram_inf_orgz;$/;" t typeref:struct:s_sram_inf_orgz +t_sram_orgz_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_sram_orgz_info t_sram_orgz_info;$/;" t typeref:struct:s_sram_orgz_info +t_standalone_sram_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_standalone_sram_info t_standalone_sram_info;$/;" t typeref:struct:s_standalone_sram_info +t_switch_block_type SRC/include/physical_types.h /^typedef enum e_switch_block_type t_switch_block_type;$/;" t typeref:enum:e_switch_block_type +t_switch_inf SRC/include/physical_types.h /^} t_switch_inf;$/;" t typeref:struct:s_switch_inf +t_swseg_pattern_inf SRC/include/physical_types.h /^typedef struct s_swseg_pattern_inf t_swseg_pattern_inf;$/;" t typeref:struct:s_swseg_pattern_inf +t_timing_inf SRC/include/physical_types.h /^} t_timing_inf;$/;" t typeref:struct:s_timing_inf +t_type_descriptor SRC/include/physical_types.h /^typedef struct s_type_descriptor t_type_descriptor;$/;" t typeref:struct:s_type_descriptor +t_type_ptr SRC/include/physical_types.h /^typedef const struct s_type_descriptor *t_type_ptr;$/;" t typeref:struct:s_type_descriptor +tap_buf_level SRC/fpga_spice_include/spice_types.h /^ int tap_buf_level;$/;" m struct:s_spice_model_buffer +tapered_buf SRC/fpga_spice_include/spice_types.h /^ int tapered_buf; \/*Valid only when this is a buffer*\/$/;" m struct:s_spice_model_buffer +tb_cnt SRC/fpga_spice_include/spice_types.h /^ int tb_cnt;$/;" m struct:s_spice_model +tb_name SRC/fpga_spice_include/spice_types.h /^ char* tb_name;$/;" m struct:s_spicetb_info +tech_comp SRC/include/arch_types_mrfpga.h /^ enum e_tech_comp tech_comp;$/;" m struct:s_arch_mrfpga typeref:enum:s_arch_mrfpga::e_tech_comp +tech_lib SRC/fpga_spice_include/spice_types.h /^ t_spice_tech_lib tech_lib;$/;" m struct:s_spice +tedge SRC/fpga_spice_include/spice_types.h /^ t_spice_model_tedge*** tedge; \/* 3-D array, considering the each pin in this port, [pin_number][num_edges[iedge]] is an edge pointor *\/$/;" m struct:s_spice_model_port +temp_net_num SRC/include/physical_types.h /^ int temp_net_num;$/;" m struct:s_pb_graph_pin +temp_placement_index SRC/include/physical_types.h /^ int temp_placement_index;$/;" m struct:s_pb_type +temp_scratch_pad SRC/include/physical_types.h /^ void *temp_scratch_pad; \/* temporary data, useful for keeping track of things when traversing data structure *\/$/;" m struct:s_pb_graph_node +tfall SRC/fpga_spice_include/spice_types.h /^ float tfall; \/* Fall condition: delay *\/$/;" m struct:s_spice_model_tedge +tileable SRC/include/physical_types.h /^ bool tileable; \/* Xifan TANG: tileable rr_graph support *\/$/;" m struct:s_arch +timing_analysis_enabled SRC/include/physical_types.h /^ boolean timing_analysis_enabled;$/;" m struct:s_timing_inf +to_block SRC/include/cad_types.h /^ t_pack_pattern_block *to_block;$/;" m struct:s_pack_pattern_connections +to_pin SRC/include/cad_types.h /^ t_pb_graph_pin *to_pin;$/;" m struct:s_pack_pattern_connections +to_pin SRC/include/physical_types.h /^ char *to_pin;$/;" m struct:s_direct_inf +to_port SRC/fpga_spice_include/spice_types.h /^ t_spice_model_port* to_port;$/;" m struct:s_spice_model_tedge +to_port_pin_number SRC/fpga_spice_include/spice_types.h /^ int to_port_pin_number;$/;" m struct:s_spice_model_tedge +to_size_t SRC/sides.cpp /^size_t Side::to_size_t() const {$/;" f class:Side +to_string SRC/sides.cpp /^std::string Side::to_string() const { $/;" f class:Side +total_pb_pins SRC/include/physical_types.h /^ int total_pb_pins; \/* only valid for top-level *\/$/;" m struct:s_pb_graph_node +transistor_cnt SRC/include/physical_types.h /^ float transistor_cnt;$/;" m struct:s_interconnect_power +transistor_cnt_buffers SRC/include/physical_types.h /^ float transistor_cnt_buffers;$/;" m struct:s_pb_graph_node_power +transistor_cnt_interc SRC/include/physical_types.h /^ float transistor_cnt_interc; \/* Total transistor size of the interconnect in this pb *\/$/;" m struct:s_pb_graph_node_power +transistor_cnt_pb_children SRC/include/physical_types.h /^ float transistor_cnt_pb_children; \/* Total transistor size of this pb *\/$/;" m struct:s_pb_graph_node_power +transistor_type SRC/fpga_spice_include/spice_types.h /^ char* transistor_type;$/;" m struct:s_spice_tech_lib +transistor_types SRC/fpga_spice_include/spice_types.h /^ t_spice_transistor_type* transistor_types;$/;" m struct:s_spice_tech_lib +transistors_per_SRAM_bit SRC/include/physical_types.h /^ float transistors_per_SRAM_bit;$/;" m struct:s_power_arch +tri_state_map SRC/fpga_spice_include/spice_types.h /^ char* tri_state_map;$/;" m struct:s_spice_model_port +trise SRC/fpga_spice_include/spice_types.h /^ float trise; \/* Rise condition: delay *\/$/;" m struct:s_spice_model_tedge +tsu_tco SRC/include/physical_types.h /^ float tsu_tco; \/* For sequential logic elements, this is the setup time (if input) or clock-to-q time (if output) *\/$/;" m struct:s_pb_graph_pin +txt SRC/include/ezxml.h /^ char *txt; \/* tag character content, empty string if none *\/$/;" m struct:ezxml +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_buffer_type type;$/;" m struct:s_spice_model_buffer typeref:enum:s_spice_model_buffer::e_spice_model_buffer_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_gate_type type;$/;" m struct:s_spice_model_gate typeref:enum:s_spice_model_gate::e_spice_model_gate_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_pass_gate_logic_type type;$/;" m struct:s_spice_model_pass_gate_logic typeref:enum:s_spice_model_pass_gate_logic::e_spice_model_pass_gate_logic_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_port_type type;$/;" m struct:s_spice_model_port typeref:enum:s_spice_model_port::e_spice_model_port_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_type type;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_tech_lib_type type;$/;" m struct:s_spice_tech_lib typeref:enum:s_spice_tech_lib::e_spice_tech_lib_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_trans_type type;$/;" m struct:s_spice_transistor_type typeref:enum:s_spice_transistor_type::e_spice_trans_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_inf_orgz typeref:enum:s_sram_inf_orgz::e_sram_orgz +type SRC/fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_orgz_info typeref:enum:s_sram_orgz_info::e_sram_orgz +type SRC/fpga_spice_include/spice_types.h /^ enum e_wire_model_type type;$/;" m struct:s_spice_model_wire_param typeref:enum:s_spice_model_wire_param::e_wire_model_type +type SRC/fpga_spice_include/spice_types.h /^ enum spice_model_delay_type type;$/;" m struct:s_spice_model_delay_info typeref:enum:s_spice_model_delay_info::spice_model_delay_type +type SRC/include/physical_types.h /^ enum PORTS type;$/;" m struct:s_port typeref:enum:s_port::PORTS +type SRC/include/physical_types.h /^ enum e_interconnect type;$/;" m struct:s_interconnect typeref:enum:s_interconnect::e_interconnect +type SRC/include/physical_types.h /^ enum e_pb_graph_pin_type type; \/* Is a sequential logic element (TRUE), inpad\/outpad (TRUE), or neither (FALSE) *\/$/;" m struct:s_pb_graph_pin typeref:enum:s_pb_graph_pin::e_pb_graph_pin_type +type SRC/include/physical_types.h /^ enum e_pin_to_pin_annotation_type type;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_type +type SRC/include/physical_types.h /^ enum e_pin_type type;$/;" m struct:s_class typeref:enum:s_class::e_pin_type +type SRC/include/physical_types.h /^ enum e_stat type;$/;" m struct:s_chan typeref:enum:s_chan::e_stat +type SRC/include/physical_types.h /^ char* type;$/;" m struct:s_switch_inf +type SRC/include/physical_types.h /^ enum e_swseg_pattern_type type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_swseg_pattern_type +u SRC/include/ezxml.h /^ char *u; \/* UTF-8 conversion of string if original was UTF-16 *\/$/;" m struct:ezxml_root +unbuf_switch SRC/include/physical_types.h /^ short unbuf_switch;$/;" m struct:s_swseg_pattern_inf +used SRC/include/logic_types.h /^ int used;$/;" m struct:s_model +val SRC/fpga_spice_include/spice_types.h /^ int val; \/* binary value to be writtent: either 0 or 1 *\/$/;" m struct:s_conf_bit +valid SRC/include/cad_types.h /^ boolean valid;$/;" m struct:s_cluster_placement_primitive +validate SRC/sides.cpp /^bool Side::validate() const {$/;" f class:Side +value SRC/fpga_spice_include/spice_types.h /^ char* value; $/;" m struct:s_spice_model_delay_info +value SRC/include/physical_types.h /^ char ** value; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation +variation_on SRC/fpga_spice_include/spice_types.h /^ boolean variation_on;$/;" m struct:s_spice_mc_variation_params +verilog_netlist SRC/fpga_spice_include/spice_types.h /^ char* verilog_netlist; \/* Verilog netlist provided by user *\/$/;" m struct:s_spice_model +verilog_reserved SRC/fpga_spice_include/spice_types.h /^ boolean verilog_reserved;$/;" m struct:s_reserved_syntax_char +verilog_sram_inf_orgz SRC/fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* verilog_sram_inf_orgz;$/;" m struct:s_sram_inf +vpr_crit_path_delay SRC/fpga_spice_include/spice_types.h /^ float vpr_crit_path_delay; \/* Reference operation clock frequency *\/$/;" m struct:s_spice_stimulate_params +vpr_printf SRC/util.c /^messagelogger vpr_printf = PrintHandlerMessage;$/;" v +width SRC/include/physical_types.h /^ float width;$/;" m struct:s_chan +wire SRC/include/physical_types.h /^ } wire;$/;" m struct:s_port_power typeref:union:s_port_power::__anon3 +wire_buffer_inf SRC/include/arch_types_mrfpga.h /^ t_buffer_inf wire_buffer_inf;$/;" m struct:s_arch_mrfpga +wire_param SRC/fpga_spice_include/spice_types.h /^ t_spice_model_wire_param* wire_param;$/;" m struct:s_spice_model +wire_switch SRC/include/physical_types.h /^ short wire_switch;$/;" m struct:s_segment_inf +wire_type SRC/include/physical_types.h /^ e_power_wire_type wire_type;$/;" m struct:s_port_power +wire_variation SRC/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params wire_variation;$/;" m struct:s_spice_mc_params +wl SRC/fpga_spice_include/spice_types.h /^ t_conf_bit* wl;$/;" m struct:s_conf_bit_info +wprog_reset_nmos SRC/fpga_spice_include/spice_types.h /^ float wprog_reset_nmos;$/;" m struct:s_spice_model_rram +wprog_reset_pmos SRC/fpga_spice_include/spice_types.h /^ float wprog_reset_pmos;$/;" m struct:s_spice_model_rram +wprog_set_nmos SRC/fpga_spice_include/spice_types.h /^ float wprog_set_nmos;$/;" m struct:s_spice_model_rram +wprog_set_pmos SRC/fpga_spice_include/spice_types.h /^ float wprog_set_pmos;$/;" m struct:s_spice_model_rram +write SRC/ezxml.c 60;" d file: +x_offset SRC/include/physical_types.h /^ int x_offset;$/;" m struct:s_direct_inf +xml SRC/include/ezxml.h /^ struct ezxml xml; \/* is a super-struct built on top of ezxml struct *\/$/;" m struct:ezxml_root typeref:struct:ezxml_root::ezxml +xpeak SRC/include/physical_types.h /^ float xpeak;$/;" m struct:s_chan +y_offset SRC/include/physical_types.h /^ int y_offset;$/;" m struct:s_direct_inf +z_offset SRC/include/physical_types.h /^ int z_offset;$/;" m struct:s_direct_inf diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 7e1a0cd77..2e1b85236 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -378,7 +378,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf /* I/O PAD */ dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, 0, phy_block_type->capacity * phy_block_type->pb_type->physical_mode_num_iopads - 1, - VERILOG_PORT_INOUT, is_explicit_mapping); + VERILOG_PORT_INOUT, false); /* Print configuration ports */ /* Reserved configuration ports */ @@ -622,9 +622,9 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, } if (IO_TYPE == grid[ix][iy].type) { - dump_verilog_io_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE); + dump_verilog_io_grid_pins(fp, ix, iy, TRUE, border_side, FALSE, FALSE, is_explicit_mapping); } else { - dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE); + dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE, is_explicit_mapping); } /* IO PAD */ @@ -792,10 +792,20 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz fprintf(fp, "//----- %s side channel ports-----\n", side_manager.c_str()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { - fprintf(fp, "%s,\n", + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), chan_coordinator.get_x(), chan_coordinator.get_y(), itrack, rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + } + fprintf(fp, "%s", + gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), + chan_coordinator.get_x(), chan_coordinator.get_y(), itrack, + rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + if (true == is_explicit_mapping) { + fprintf(fp, ")",itrack); + } + fprintf(fp, ",\n",itrack); } fprintf(fp, "//----- %s side inputs: CLB output pins -----\n", convert_side_index_to_string(side)); /* Dump OPINs of adjacent CLBs */ @@ -917,9 +927,16 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ fprintf(fp, "//----- %s side inputs: channel track middle outputs -----\n", convert_side_index_to_string(rr_gsb.get_cb_chan_side(cb_type))); for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - fprintf(fp, "%s, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", rr_gsb.gen_cb_verilog_routing_track_name(cb_type, itrack)); - fprintf(fp, "\n"); + } + fprintf(fp, "%s", + rr_gsb.gen_cb_verilog_routing_track_name(cb_type, itrack)); + if (true == is_explicit_mapping) { + fprintf(fp, ")",itrack); + } + fprintf(fp, ",\n"); } std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index a779ee550..6fa1ad6da 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -369,8 +369,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, pb_type_port->num_pins - 1, port_prefix, pb_type_port->name); } else { - if ((NULL != cur_pb_type->spice_model) - && (TRUE == dump_explicit_port_map)) { + if (TRUE == dump_explicit_port_map) { fprintf(fp, ".%s(", pb_type_port->spice_model_port->lib_name); } @@ -383,8 +382,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin)); } fprintf(fp, "}"); - if ((NULL != cur_pb_type->spice_model) - && (TRUE == dump_explicit_port_map)) { + if (TRUE == dump_explicit_port_map) { fprintf(fp, ")"); } } @@ -537,7 +535,8 @@ void dump_verilog_pb_type_ports(FILE* fp, t_pb_type* cur_pb_type, boolean dump_port_type, boolean dump_last_comma, - boolean require_explicit_port_map) { + boolean require_explicit_port_map, + bool is_full_name) { int iport, ipin; int num_pb_type_input_port = 0; t_port** pb_type_input_ports = NULL; @@ -588,18 +587,21 @@ void dump_verilog_pb_type_ports(FILE* fp, } if (TRUE == dump_port_type) { fprintf(fp, "inout wire "); - } else if ((NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + } else if (TRUE == require_explicit_port_map) { + if (false == is_full_name && NULL != cur_pb_type->spice_model) { fprintf(fp, ".%s(", pb_type_inout_ports[iport]->spice_model_port->lib_name); + } else { + /* fprintf(fp, ".%s(", + gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_inout_ports[iport], ipin)); */ + fprintf(fp, ".%s__%s_%d_(", + cur_pb_type->name, pb_type_inout_ports[iport]->name, ipin); + } } - fprintf(fp, "%s", + fprintf(fp, "%s", gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_inout_ports[iport], ipin)); - if ((FALSE == dump_port_type) - && (NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + if ((FALSE == dump_port_type) + && TRUE == require_explicit_port_map) { fprintf(fp, ") "); } /* Update the counter */ @@ -631,18 +633,21 @@ void dump_verilog_pb_type_ports(FILE* fp, } if (TRUE == dump_port_type) { fprintf(fp, "input wire "); - } else if ((NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + } else if (TRUE == require_explicit_port_map) { + if (false == is_full_name && NULL != cur_pb_type->spice_model) { fprintf(fp, ".%s(", pb_type_input_ports[iport]->spice_model_port->lib_name); + } else { + /* fprintf(fp, ".%s(", + gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_input_ports[iport], ipin)); */ + fprintf(fp, ".%s__%s_%d_(", + cur_pb_type->name, pb_type_input_ports[iport]->name, ipin); + } } fprintf(fp, "%s", gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_input_ports[iport], ipin)); if ((FALSE == dump_port_type) - && (NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + && TRUE == require_explicit_port_map) { fprintf(fp, ") "); } /* Update the counter */ @@ -673,18 +678,21 @@ void dump_verilog_pb_type_ports(FILE* fp, } if (TRUE == dump_port_type) { fprintf(fp, "output wire "); - } else if ((NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + } else if (TRUE == require_explicit_port_map) { + if (false == is_full_name && NULL != cur_pb_type->spice_model) { fprintf(fp, ".%s(", pb_type_output_ports[iport]->spice_model_port->lib_name); + } else { + /* fprintf(fp, ".%s(", + gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_output_ports[iport], ipin));*/ + fprintf(fp, ".%s__%s_%d_(", + cur_pb_type->name, pb_type_output_ports[iport]->name, ipin); + } } fprintf(fp, "%s", gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_output_ports[iport], ipin)); if ((FALSE == dump_port_type) - && (NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + && TRUE == require_explicit_port_map) { fprintf(fp, ") "); } /* Update the counter */ @@ -718,18 +726,19 @@ void dump_verilog_pb_type_ports(FILE* fp, } if (TRUE == dump_port_type) { fprintf(fp, "input wire "); - } else if ((NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + } else if (TRUE == require_explicit_port_map) { + if (false == is_full_name && NULL != cur_pb_type->spice_model) { fprintf(fp, ".%s(", pb_type_clk_ports[iport]->spice_model_port->lib_name); + } else { + fprintf(fp, ".%s__%s_%d_(", + cur_pb_type->name, pb_type_clk_ports[iport]->name, ipin); + } } fprintf(fp, "%s", gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_clk_ports[iport], ipin)); if ((FALSE == dump_port_type) - && (NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + && TRUE == require_explicit_port_map) { fprintf(fp, ") "); } /* Update the counter */ @@ -1501,7 +1510,7 @@ void dump_verilog_pb_graph_primitive_node(FILE* fp, fprintf(fp, "module %s (", subckt_name); /* subckt_port_name = format_verilog_node_prefix(subckt_name); */ /* Inputs, outputs, inouts, clocks */ - dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, TRUE, FALSE, FALSE); + dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, TRUE, FALSE, FALSE, false); /* SRAM ports */ fprintf(fp, ");\n"); /* Include the spice_model*/ @@ -1509,7 +1518,7 @@ void dump_verilog_pb_graph_primitive_node(FILE* fp, verilog_model->cnt++; /* Stats the number of verilog_model used*/ /* Make input, output, inout, clocks connected*/ /* IMPORTANT: (sequence of these ports should be changed!) */ - dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, FALSE, FALSE, TRUE); + dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, FALSE, FALSE, TRUE, true); fprintf(fp, ");"); /* Print end of subckt*/ fprintf(fp, "endmodule\n"); @@ -1735,12 +1744,12 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ",\n"); } /* Simplify the port prefix, make SPICE netlist readable */ - dump_verilog_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type, TRUE, FALSE, FALSE); + dump_verilog_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type, TRUE, FALSE, FALSE, false); /* Print Input Pad and Output Pad */ dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, stamped_iopad_cnt, iopad_verilog_model->cnt - 1, - VERILOG_PORT_INOUT, is_explicit_mapping); + VERILOG_PORT_INOUT, false); /* Print Configuration ports */ /* sram_verilog_model->cnt should be updated because all the child pbs have been dumped * stamped_sram_cnt remains the old sram_verilog_model->cnt before all the child pbs are dumped @@ -1823,7 +1832,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, } else { if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model, - FALSE, TRUE, FALSE)) { + FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } } @@ -1840,7 +1849,13 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, /* Print inputs, outputs, inouts, clocks * NO SRAMs !!! They have already been fixed in the bottom level */ - dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, FALSE); + bool is_explicit_full_name = true; + if (NULL != cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model){ + if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){ + is_explicit_full_name = false; + } + } + dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), is_explicit_full_name); /* Print I/O pads */ dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, @@ -1871,7 +1886,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, stamped_sram_cnt, stamped_sram_cnt + child_pb_num_conf_bits - 1, - VERILOG_PORT_CONKT, false); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2008,7 +2023,8 @@ void dump_verilog_grid_pins(FILE* fp, int y, boolean top_level, boolean dump_port_type, - boolean dump_last_comma) { + boolean dump_last_comma, + bool is_explicit_mapping) { int iheight, side, ipin, class_id; int side_pin_index; t_type_ptr type_descriptor = grid[x][y].type; @@ -2063,7 +2079,14 @@ void dump_verilog_grid_pins(FILE* fp, } } /* This pin appear at this side! */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s_height_%d__pin_%d_(", + convert_side_index_to_string(side), iheight, ipin); + } fprintf(fp, " %s", gen_verilog_grid_one_pin_name(x, y, iheight, side, ipin, top_level)); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* Update counter */ num_dumped_port++; side_pin_index++; @@ -2093,8 +2116,10 @@ void dump_verilog_grid_pins(FILE* fp, void dump_verilog_io_grid_pins(FILE* fp, int x, int y, boolean top_level, + int border_side, boolean dump_port_type, - boolean dump_last_comma) { + boolean dump_last_comma, + bool is_explicit_mapping) { int iheight, side, ipin; int side_pin_index; t_type_ptr type_descriptor = grid[x][y].type; @@ -2156,7 +2181,14 @@ void dump_verilog_io_grid_pins(FILE* fp, } } /* This pin appear at this side! */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s_height_%d__pin_%d_(", + convert_side_index_to_string(border_side), iheight, ipin); + } fprintf(fp, " %s", gen_verilog_grid_one_pin_name(x, y, iheight, side, ipin, top_level)); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* Update counter */ num_dumped_port++; side_pin_index++; @@ -2581,9 +2613,9 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, /* Pins */ /* Special Care for I/O grid */ if (IO_TYPE == grid[ix][iy].type) { - dump_verilog_io_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE); + dump_verilog_io_grid_pins(fp, ix, iy, FALSE, 0, TRUE, FALSE,is_explicit_mapping); } else { - dump_verilog_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE); + dump_verilog_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE, is_explicit_mapping); } /* IO PAD */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h index 25ffcd85d..e7df65069 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h @@ -32,7 +32,8 @@ void dump_verilog_pb_type_ports(FILE* fp, t_pb_type* cur_pb_type, boolean dump_port_type, boolean dump_last_comma, - boolean require_explicit_port_map); + boolean require_explicit_port_map, + bool is_full_name); void dump_verilog_dangling_des_pb_graph_pin_interc(FILE* fp, t_pb_graph_pin* des_pb_graph_pin, @@ -111,13 +112,16 @@ void dump_verilog_grid_pins(FILE* fp, int x, int y, boolean top_level, boolean dump_port_type, - boolean dump_last_comma); + boolean dump_last_comma, + bool is_explicit_mapping); void dump_verilog_io_grid_pins(FILE* fp, int x, int y, boolean top_level, + int border_side, boolean dump_port_type, - boolean dump_last_comma); + boolean dump_last_comma, + bool is_explicit_mapping); char* get_grid_block_subckt_name(int x, int y, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index 3354a8938..24c46587b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -134,8 +134,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); /* print ports --> input ports */ - dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE); - + dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE, false); /* IOPADs requires a specical port to output */ if (SPICE_MODEL_IOPAD == verilog_model->type) { fprintf(fp, ",\n"); @@ -236,22 +235,21 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, /* assert */ num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); /* print ports --> input ports */ - dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, verilog_model->dump_explicit_port_map); - + dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping)); /* IOPADs requires a specical port to output */ if (SPICE_MODEL_IOPAD == verilog_model->type) { fprintf(fp, ",\n"); assert(1 == num_pad_port); assert(NULL != pad_ports[0]); /* Add explicit port mapping if required */ - if (TRUE == verilog_model->dump_explicit_port_map) { + if (true == is_explicit_mapping) { fprintf(fp, ".%s(", pad_ports[0]->lib_name); } /* Print inout port */ fprintf(fp, "%s%s[%d]", gio_inout_prefix, verilog_model->prefix, verilog_model->cnt); - if (TRUE == verilog_model->dump_explicit_port_map) { + if (true == is_explicit_mapping) { fprintf(fp, ")"); } fprintf(fp, ", "); @@ -265,7 +263,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, case SPICE_SRAM_SCAN_CHAIN: /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -275,7 +273,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 0, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { fprintf(fp, ")"); } @@ -286,7 +284,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ", "); /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -296,14 +294,14 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 1, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { fprintf(fp, ")"); } break; case SPICE_SRAM_MEMORY_BANK: /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -313,7 +311,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 0, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { fprintf(fp, ")"); } /* Check if we have an inverterd prefix */ @@ -323,7 +321,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ", "); /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -333,7 +331,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 1, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { fprintf(fp, ")"); } break; @@ -531,7 +529,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ",\n"); } /* Print inputs, outputs, inouts, clocks, NO SRAMs*/ - dump_verilog_pb_type_ports(fp, port_prefix, 0, cur_pb_type, TRUE, TRUE, FALSE); + dump_verilog_pb_type_ports(fp, port_prefix, 0, cur_pb_type, TRUE, TRUE, FALSE, false); /* Print SRAM ports */ cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index eced18e87..2203641fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2101,7 +2101,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or rr_gsb.get_sb_conf_bits_lsb(), rr_gsb.get_sb_conf_bits_msb(), VERILOG_PORT_INPUT, - is_explicit_mapping); + false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index b91ffc3e6..e0f09aebd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3088,7 +3088,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, input_port[0]->prefix); /* Connect MUX inverted configuration port to inverted LUT inputs */ if (true == is_explicit_mapping) { - fprintf(fp, "), sram_inv("); + fprintf(fp, "), .sram_inv("); } else { fprintf(fp, ", "); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index f0edb1578..61e8981ae 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -396,9 +396,9 @@ void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, } if (IO_TYPE == grid[ix][iy].type) { - dump_verilog_io_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE); + dump_verilog_io_grid_pins(fp, ix, iy, TRUE, 0, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping)); } else { - dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE); + dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE, is_explicit_mapping); } /* IO PAD */ @@ -1474,8 +1474,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->input_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_", convert_side_index_to_string(border_side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } side_pin_index++; dump_pin_cnt++; } @@ -1497,8 +1504,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->output_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_", convert_side_index_to_string(border_side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } side_pin_index++; dump_pin_cnt++; } @@ -1520,8 +1534,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->clock_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_", convert_side_index_to_string(border_side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } side_pin_index++; dump_pin_cnt++; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 90a010607..d2da736c1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -806,16 +806,14 @@ int rec_dump_verilog_spice_model_lib_global_ports(FILE* fp, cur_spice_model_port->lib_name); } else { /* Add explicit port mapping if required */ - if ((TRUE == require_explicit_port_map) - && (TRUE == cur_spice_model->dump_explicit_port_map)) { + if (TRUE == require_explicit_port_map) { fprintf(fp, ".%s(", cur_spice_model_port->lib_name); } fprintf(fp, "%s[0:%d]", cur_spice_model_port->lib_name, cur_spice_model_port->size - 1); - if ((TRUE == require_explicit_port_map) - && (TRUE == cur_spice_model->dump_explicit_port_map)) { + if (TRUE == require_explicit_port_map) { fprintf(fp, ")"); } } @@ -902,8 +900,7 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, cur_spice_model_port->prefix); } else { /* Add explicit port mapping if required */ - if ((TRUE == require_explicit_port_map) - && (TRUE == cur_spice_model->dump_explicit_port_map)) { + if (TRUE == require_explicit_port_map ) { fprintf(fp, ".%s(", /* cur_spice_model_port->lib_name); /* Old version*/ cur_spice_model_port->prefix); @@ -911,8 +908,7 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, fprintf(fp, "%s[0:%d]", cur_spice_model_port->prefix, cur_spice_model_port->size - 1); - if ((TRUE == require_explicit_port_map) - && (TRUE == cur_spice_model->dump_explicit_port_map)) { + if (TRUE == require_explicit_port_map) { fprintf(fp, ")"); } } @@ -2736,9 +2732,15 @@ void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, /*Malloc and generate the full name of port */ port_full_name = (char*)my_malloc(sizeof(char)*(strlen(general_port_prefix) + strlen(cur_verilog_model->prefix) + 1)); sprintf(port_full_name, "%s%s", general_port_prefix, cur_verilog_model->prefix); - fprintf(fp, ",\n"); + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + port_full_name); + } dump_verilog_generic_port(fp, dump_port_type, port_full_name, msb, lsb); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* Free */ /* Local variables such as port1_name and port2 name are automatically freed */ @@ -3099,6 +3101,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, int num_bl_per_sram = 0; int num_wl_per_sram = 0; + int iport = 0; /* Check the file handler*/ if (NULL == fp) { @@ -3201,75 +3204,99 @@ void dump_verilog_mem_sram_submodule(FILE* fp, if (SPICE_MODEL_MUX == cur_verilog_model->type) { /* Input of Scan-chain DFF, should be connected to the output of its precedent */ if (true == is_explicit_mapping) { + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[0].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, -1, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } - fprintf(fp, ", \n"); // + fprintf(fp, ", \n"); /* Output of Scan-chain DFF, should be connected to the output of its successor */ + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } if (true == is_explicit_mapping) { fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[1].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, 0, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } - fprintf(fp, ", \n"); // + fprintf(fp, ", \n"); + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } if (true == is_explicit_mapping) { fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[2].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, 1, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } break; } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ if (true == is_explicit_mapping) { + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[0].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, -1, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } - fprintf(fp, ", \n"); // + fprintf(fp, ", \n"); /* Output of Scan-chain DFF, should be connected to the output of its successor */ if (true == is_explicit_mapping) { + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[1].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, 0, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } - fprintf(fp, ", \n"); // + fprintf(fp, ", \n"); if (true == is_explicit_mapping) { + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[2].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, 1, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } break; diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh old mode 100644 new mode 100755 index 8007363cf..b31d5efa2 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -35,6 +35,8 @@ cd - # Run VPR ./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping +#/research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif --full_stats --nodisp --activity_file /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.act --fpga_verilog --fpga_verilog_dir /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/vpr7_x2p/vpr/test_modes_Verilog --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/benchmarks/Verilog/Test_Modes/test_modes.v --fpga_verilog_print_user_defined_template --route_chan_width 200 --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping + cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path cd - From 589f58b55ec6919c3c5da978ce9c375094692cad Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Tue, 9 Jul 2019 09:18:06 -0600 Subject: [PATCH 17/24] Regression test succeeded --- .../arch/template/k6_N10_sram_chain_HC_template.xml | 4 ++-- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c | 4 ++-- vpr7_x2p/vpr/VerilogNetlists/io.v | 10 +++++----- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml index 06e75d911..8dca26477 100644 --- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml @@ -336,8 +336,8 @@ - - + + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 6fa1ad6da..25c162c48 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1851,9 +1851,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, */ bool is_explicit_full_name = true; if (NULL != cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model){ - if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){ + /*if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){ is_explicit_full_name = false; - } + }TEST*/ } dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), is_explicit_full_name); /* Print I/O pads */ diff --git a/vpr7_x2p/vpr/VerilogNetlists/io.v b/vpr7_x2p/vpr/VerilogNetlists/io.v index ab451b2b7..9fccdd23d 100644 --- a/vpr7_x2p/vpr/VerilogNetlists/io.v +++ b/vpr7_x2p/vpr/VerilogNetlists/io.v @@ -3,14 +3,14 @@ //------ Author: Xifan TANG -----// module iopad( //input zin, // Set output to be Z -input dout, // Data output -output din, // Data input +input outpad, // Data output +output inpad, // Data input inout pad, // bi-directional pad -input direction // enable signal to control direction of iopad +input en // enable signal to control direction of iopad //input direction_inv // enable signal to control direction of iopad ); //----- when direction enabled, the signal is propagated from pad to din - assign din = direction ? pad : 1'bz; + assign inpad = en ? pad : 1'bz; //----- when direction is disabled, the signal is propagated from dout to pad - assign pad = direction ? 1'bz : dout; + assign pad = en ? 1'bz : outpad; endmodule From 65f696c1d76508840952077b3056f736d5442668 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2019 17:41:20 -0600 Subject: [PATCH 18/24] fix critical bugs in rectangle floorplan --- .../device/rr_graph/tileable_rr_graph_builder.cpp | 13 +++++++++---- .../vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c | 8 +++++++- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp | 4 ++-- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h | 4 ++-- 4 files changed, 20 insertions(+), 9 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp index fe521ffa0..3d919ecc0 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp @@ -687,10 +687,15 @@ void alloc_rr_graph_fast_lookup(const DeviceCoordinator& device_size, if ((SOURCE == type) || (OPIN == type) ) { continue; } - rr_graph->rr_node_indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * device_size.get_x()); - for (size_t i = 0; i < device_size.get_x(); ++i) { - rr_graph->rr_node_indices[type][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * device_size.get_y()); - for (size_t j = 0; j < device_size.get_y(); ++j) { + DeviceCoordinator actual_device_size(device_size); + /* Special for CHANX: we use (y,x) in allocation */ + if (CHANX == type) { + actual_device_size.rotate(); + } + rr_graph->rr_node_indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * actual_device_size.get_x()); + for (size_t i = 0; i < actual_device_size.get_x(); ++i) { + rr_graph->rr_node_indices[type][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * actual_device_size.get_y()); + for (size_t j = 0; j < actual_device_size.get_y(); ++j) { rr_graph->rr_node_indices[type][i][j].nelem = 0; rr_graph->rr_node_indices[type][i][j].list = NULL; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index dc76ff55d..315f4f5ff 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -1354,6 +1354,12 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, "Backannotated %d switch blocks.\n", (nx + 1) * (ny + 1) ); + /* End time count */ + t_end = clock(); + + run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, "Backannotation of Switch Block took %g seconds\n\n", run_time_sec); + if (TRUE == output_sb_xml) { create_dir_path(sb_xml_dir); @@ -1406,7 +1412,7 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, t_end = clock(); run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniqifying took %g seconds\n", run_time_sec); + vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniqifying took %g seconds\n\n", run_time_sec); return LL_device_rr_gsb; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index f0d59fd9b..42fc21c17 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -2598,7 +2598,7 @@ void DeviceRRGSB::reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator) } /* Resize rr_switch_block array is needed*/ -void DeviceRRGSB::resize_upon_need(DeviceCoordinator& coordinator) { +void DeviceRRGSB::resize_upon_need(const DeviceCoordinator& coordinator) { if (coordinator.get_x() + 1 > rr_gsb_.size()) { rr_gsb_.resize(coordinator.get_x() + 1); @@ -2622,7 +2622,7 @@ void DeviceRRGSB::resize_upon_need(DeviceCoordinator& coordinator) { } /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ -void DeviceRRGSB::add_rr_gsb(DeviceCoordinator& coordinator, +void DeviceRRGSB::add_rr_gsb(const DeviceCoordinator& coordinator, const RRGSB& rr_gsb) { /* Resize upon needs*/ resize_upon_need(coordinator); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h index d95c08d75..e87ee78c6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h @@ -353,8 +353,8 @@ class DeviceRRGSB { void set_cb_conf_bits_msb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ void reserve(DeviceCoordinator& coordinator); /* Pre-allocate the rr_switch_block array that the device requires */ void reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ - void resize_upon_need(DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */ - void add_rr_gsb(DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ + void resize_upon_need(const DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */ + void add_rr_gsb(const DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ void build_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ void clear(); /* clean the content */ private: /* Internal cleaners */ From edfe3144c3417b848fbd19157d474616814bbfc0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2019 20:28:01 -0600 Subject: [PATCH 19/24] update profiling, found where runtime is lost --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index 315f4f5ff..d625a5375 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -1324,6 +1324,10 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, clock_t t_end; float run_time_sec; + clock_t t_start_profiling; + clock_t t_end_profiling; + float run_time_sec_profiling = 0.; + /* Start time count */ t_start = clock(); @@ -1342,8 +1346,15 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, num_segments, LL_rr_indexed_data); + + /* For profiling */ + t_start_profiling = clock(); /* sort drive_rr_nodes */ sort_rr_gsb_drive_rr_nodes(rr_gsb); + /* End time count */ + t_end_profiling = clock(); + run_time_sec_profiling += (float)(t_end_profiling - t_start_profiling) / CLOCKS_PER_SEC; + /* Add to device_rr_gsb */ DeviceCoordinator sb_coordinator = rr_gsb.get_sb_coordinator(); LL_device_rr_gsb.add_rr_gsb(sb_coordinator, rr_gsb); @@ -1360,6 +1371,8 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; vpr_printf(TIO_MESSAGE_INFO, "Backannotation of Switch Block took %g seconds\n\n", run_time_sec); + vpr_printf(TIO_MESSAGE_INFO, "Edge sorting for Switch Block took %g seconds\n\n", run_time_sec_profiling); + if (TRUE == output_sb_xml) { create_dir_path(sb_xml_dir); From 57ae5dbbec48eecc277525b296eb8a5d6c1533fe Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2019 20:47:52 -0600 Subject: [PATCH 20/24] bug fixing for rectangle FPGA sizes --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 064cb2623..8ea7f0f6b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -986,7 +986,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or /* Get X-channel CB coordinator */ const DeviceCoordinator cbx_coordinator = rr_gsb.get_cb_coordinator(CHANX); /* X - channels [1...nx][0..ny]*/ - if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_x())) + if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_y())) &&(true == rr_gsb.is_cb_exist(CHANX))) { dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX); } @@ -994,7 +994,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or /* Get X-channel CB coordinator */ const DeviceCoordinator cby_coordinator = rr_gsb.get_cb_coordinator(CHANY); /* Y - channels [1...ny][0..nx]*/ - if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_x())) + if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_y())) &&(true == rr_gsb.is_cb_exist(CHANY))) { dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY); } From b7f9831bd2fe10274740ec7ccaa536a8f26b0f53 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2019 13:08:03 -0600 Subject: [PATCH 21/24] add statistics for unique GSBs --- .../fpga_x2p/base/fpga_x2p_unique_routing.c | 11 ++- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp | 75 +++++++++++++++++++ vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h | 8 ++ 3 files changed, 91 insertions(+), 3 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index d625a5375..7217afd25 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -1395,17 +1395,22 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, /* Report number of unique CB Modules */ vpr_printf(TIO_MESSAGE_INFO, - "Detect %d independent connection blocks from %d X-channel connection blocks.\n", + "Detect %d unique connection blocks from %d X-channel connection blocks.\n", LL_device_rr_gsb.get_num_cb_unique_module(CHANX), (nx + 0) * (ny + 1) ); vpr_printf(TIO_MESSAGE_INFO, - "Detect %d independent connection blocks from %d Y-channel connection blocks.\n", + "Detect %d unique connection blocks from %d Y-channel connection blocks.\n", LL_device_rr_gsb.get_num_cb_unique_module(CHANY), (nx + 1) * (ny + 0) ); /* Report number of unique SB modules */ vpr_printf(TIO_MESSAGE_INFO, - "Detect %d independent switch blocks from %d switch blocks.\n", + "Detect %d unique switch blocks from %d switch blocks.\n", + LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) ); + + /* Report number of unique GSB modules */ + vpr_printf(TIO_MESSAGE_INFO, + "Detect %d unique GSBs from %d GSBs.\n", LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) ); /* Report number of unique mirrors */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index 42fc21c17..4330ca5cc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -2379,6 +2379,11 @@ size_t DeviceRRGSB::get_num_sb_unique_module() const { return sb_unique_module_.size(); } +/* get the number of unique mirrors of switch blocks */ +size_t DeviceRRGSB::get_num_gsb_unique_module() const { + return gsb_unique_module_.size(); +} + /* Get the submodule id of a SB */ size_t DeviceRRGSB::get_sb_unique_submodule_id(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const { @@ -2565,6 +2570,8 @@ void DeviceRRGSB::set_sb_conf_bits_msb(DeviceCoordinator& coordinator, size_t co void DeviceRRGSB::reserve(DeviceCoordinator& coordinator) { rr_gsb_.resize(coordinator.get_x()); + gsb_unique_module_id_.resize(coordinator.get_x()); + sb_unique_submodule_id_.resize(coordinator.get_x()); sb_unique_module_id_.resize(coordinator.get_x()); @@ -2574,6 +2581,8 @@ void DeviceRRGSB::reserve(DeviceCoordinator& coordinator) { for (size_t x = 0; x < coordinator.get_x(); ++x) { rr_gsb_[x].resize(coordinator.get_y()); + gsb_unique_module_id_[x].resize(coordinator.get_y()); + sb_unique_submodule_id_[x].resize(coordinator.get_y()); sb_unique_module_id_[x].resize(coordinator.get_y()); @@ -2769,6 +2778,45 @@ void DeviceRRGSB::add_sb_unique_side_segment_submodule(DeviceCoordinator& coordi return; } +/* Find repeatable GSB block in the array */ +void DeviceRRGSB::build_gsb_unique_module() { + /* Make sure a clean start */ + clear_gsb_unique_module(); + + for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) { + for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) { + bool is_unique_module = true; + DeviceCoordinator gsb_coordinator(ix, iy); + + /* Traverse the unique_mirror list and check it is an mirror of another */ + for (size_t id = 0; id < get_num_gsb_unique_module(); ++id) { + /* We have alreay built sb and cb unique module list + * We just need to check if the unique module id of SBs, CBX and CBY are the same or not + */ + const DeviceCoordinator& gsb_unique_module_coordinator = gsb_unique_module_[id]; + if ((sb_unique_module_id_[ix][iy] == sb_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()]) + && (cbx_unique_module_id_[ix][iy] == cbx_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()]) + && (cby_unique_module_id_[ix][iy] == cby_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()])) { + /* This is a mirror, raise the flag and we finish */ + is_unique_module = false; + /* Record the id of unique mirror */ + gsb_unique_module_id_[ix][iy] = id; + break; + } + } + /* Add to list if this is a unique mirror*/ + if (true == is_unique_module) { + add_gsb_unique_module(gsb_coordinator); + /* Record the id of unique mirror */ + gsb_unique_module_id_[ix][iy] = get_num_gsb_unique_module() - 1; + } + } + } + return; +} + + + void DeviceRRGSB::build_unique_module() { build_segment_ids(); @@ -2777,6 +2825,8 @@ void DeviceRRGSB::build_unique_module() { build_cb_unique_module(CHANX); build_cb_unique_module(CHANY); + build_gsb_unique_module(); + return; } @@ -2797,6 +2847,11 @@ void DeviceRRGSB::add_sb_unique_side_submodule(DeviceCoordinator& coordinator, return; } +void DeviceRRGSB::add_gsb_unique_module(const DeviceCoordinator& coordinator) { + gsb_unique_module_.push_back(coordinator); + return; +} + void DeviceRRGSB::add_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator) { assert (validate_cb_type(cb_type)); switch(cb_type) { @@ -2868,6 +2923,9 @@ void DeviceRRGSB::build_segment_ids() { void DeviceRRGSB::clear() { clear_gsb(); + clear_gsb_unique_module(); + clear_gsb_unique_module_id(); + /* clean unique module lists */ clear_cb_unique_module(CHANX); clear_cb_unique_module_id(CHANX); @@ -2893,6 +2951,15 @@ void DeviceRRGSB::clear_gsb() { return; } +void DeviceRRGSB::clear_gsb_unique_module_id() { + /* clean rr_switch_block array */ + for (size_t x = 0; x < rr_gsb_.size(); ++x) { + gsb_unique_module_id_[x].clear(); + } + return; +} + + void DeviceRRGSB::clear_sb_unique_module_id() { /* clean rr_switch_block array */ for (size_t x = 0; x < rr_gsb_.size(); ++x) { @@ -2950,6 +3017,14 @@ void DeviceRRGSB::clear_sb_unique_submodule() { return; } +/* clean the content related to unique_mirrors */ +void DeviceRRGSB::clear_gsb_unique_module() { + /* clean unique mirror */ + gsb_unique_module_.clear(); + + return; +} + /* clean the content related to unique_mirrors */ void DeviceRRGSB::clear_sb_unique_module() { /* clean unique mirror */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h index e87ee78c6..c6cb9978c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h @@ -330,6 +330,7 @@ class DeviceRRGSB { DeviceCoordinator get_gsb_range() const; /* get the max coordinator of the switch block array */ const RRGSB get_gsb(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */ const RRGSB get_gsb(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */ + size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */ size_t get_num_sb_unique_submodule(enum e_side side, size_t seg_index) const; /* get the number of unique mirrors of switch blocks */ size_t get_num_sb_unique_module() const; /* get the number of unique mirrors of switch blocks */ size_t get_num_cb_unique_module(t_rr_type cb_type) const; /* get the number of unique mirrors of CBs */ @@ -365,6 +366,8 @@ class DeviceRRGSB { void clear_sb_unique_module_id(); /* clean the content */ void clear_sb_unique_submodule(); /* clean the content */ void clear_sb_unique_submodule_id(); /* clean the content */ + void clear_gsb_unique_module(); /* clean the content */ + void clear_gsb_unique_module_id(); /* clean the content */ void clear_segment_ids(); private: /* Validators */ bool validate_coordinator(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device */ @@ -376,6 +379,7 @@ class DeviceRRGSB { bool validate_cb_type(t_rr_type cb_type) const; private: /* Internal builders */ void build_segment_ids(); /* build a map of segment_ids */ + void add_gsb_unique_module(const DeviceCoordinator& coordinator); void add_sb_unique_side_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side); void add_sb_unique_side_segment_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side, size_t seg_id); void add_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator); @@ -383,9 +387,13 @@ class DeviceRRGSB { void build_sb_unique_submodule(); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */ void build_sb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ void build_cb_unique_module(t_rr_type cb_type); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */ + void build_gsb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ private: /* Internal Data */ std::vector< std::vector > rr_gsb_; + std::vector< std::vector > gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ + std::vector gsb_unique_module_; + std::vector< std::vector > sb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ std::vector sb_unique_module_; From 0a978db8669e10c8d417b0bc141128a277e53f21 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Wed, 10 Jul 2019 14:16:34 -0600 Subject: [PATCH 22/24] Fix regression test --- .../verilog/verilog_compact_netlist.c | 21 +++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 2e1b85236..6f93f2142 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -928,13 +928,12 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ convert_side_index_to_string(rr_gsb.get_cb_chan_side(cb_type))); for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { if (true == is_explicit_mapping) { - fprintf(fp, ".%s (", - rr_gsb.gen_cb_verilog_routing_track_name(cb_type, itrack)); + fprintf(fp, ".%s(", unique_mirror.gen_cb_verilog_routing_track_name(cb_type, itrack)); } fprintf(fp, "%s", rr_gsb.gen_cb_verilog_routing_track_name(cb_type, itrack)); if (true == is_explicit_mapping) { - fprintf(fp, ")",itrack); + fprintf(fp, ")"); } fprintf(fp, ",\n"); } @@ -949,12 +948,26 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { t_rr_node* cur_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); /* Print each INPUT Pins of a grid */ + if (true == is_explicit_mapping) { + if (RIGHT == side_manager.get_side()) { + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x() + 1, unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + } else if (TOP == side_manager.get_side()) { + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + } else if (LEFT == side_manager.get_side()) { + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + } else if (BOTTOM == side_manager.get_side()) { + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y(), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + } + } dump_verilog_grid_side_pin_with_given_index(fp, OPIN, cur_ipin_node->ptc_num, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), cur_ipin_node->xlow, cur_ipin_node->ylow, - FALSE, is_explicit_mapping); /* Do not specify direction of port */ + FALSE, false); /* Do not specify direction of port */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", \n"); } } From 206fc84a0eaf7e265194968cf4b08debf83a29e2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2019 15:12:51 -0600 Subject: [PATCH 23/24] minor fix in fpga_flow --- fpga_flow/scripts/fpga_flow.pl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 8ee3801a9..49eda2e33 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1790,7 +1790,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); # Remove previous route results if (-e $vpr_route) { - system(rm $vpr_route); + system("rm $vpr_route"); } # Keep increase min_chan_width until route success &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file); From 31749fe62bb68f23826a038d7b2e87f8803d7340 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2019 21:12:00 -0600 Subject: [PATCH 24/24] fix bugs in fpga_flow.pl --- fpga_flow/scripts/fpga_flow.pl | 4 ++-- vpr7_x2p/vpr/SRC/base/vpr_api.c | 36 ++++++++++++++++----------------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 49eda2e33..7d21875e9 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1318,7 +1318,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) my ($chan_width_opt) = (""); if (($fix_chan_width > 0)||($fix_chan_width == 0)) { - $chan_width_opt = "-route_chan_width $fix_chan_width"; + $chan_width_opt = "--route_chan_width $fix_chan_width"; } if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) { $chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width"; @@ -1569,7 +1569,7 @@ sub run_mpack2_vpr($ $ $ $ $ $ $) if (0 != $min_chan_width%2) { $min_chan_width += 1; } - $chan_width_opt = "-route_chan_width $min_chan_width"; + $chan_width_opt = "--route_chan_width $min_chan_width"; } chdir $vpr_dir; diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index c85dc934f..023b2df92 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -365,16 +365,16 @@ void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) { alloc_and_load_grid(num_instances_type); freeGrid(); - /* Xifan TANG: We need consider the length of carry-chain CLBs into account! */ - num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros); - /* find length of longest carry-chain logic blocks */ - max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros); - /* Free all the allocated structs */ - free_placement_macros_structs(); - for (imacro = 0; imacro < num_pl_macros; imacro ++) { - free(pl_macros[imacro].members); - } - free(pl_macros); + /* Xifan TANG: We need consider the length of carry-chain CLBs into account! */ + num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros); + /* find length of longest carry-chain logic blocks */ + max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros); + /* Free all the allocated structs */ + free_placement_macros_structs(); + for (imacro = 0; imacro < num_pl_macros; imacro ++) { + free(pl_macros[imacro].members); + } + free(pl_macros); /* Test if netlist fits in grid */ fit = TRUE; @@ -384,14 +384,14 @@ void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) { break; } } - /* If the length of macros is longer than ny - 2, fitting should fail. - * Note: carry-chain logic blocks are placed only vertically in FPGA. - */ - if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) { - fit = FALSE; - vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d)!\n", - max_len_chain_blocks, ny); - } + /* If the length of macros is longer than ny - 2, fitting should fail. + * Note: carry-chain logic blocks are placed only vertically in FPGA. + */ + if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) { + fit = FALSE; + vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d)!\n", + max_len_chain_blocks, ny); + } /* get next value */ if (!fit) {