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Changed for the naming

This commit is contained in:
Baudouin Chauviere 2018-12-08 16:19:38 -07:00
parent 4440066565
commit 79930982cf
4 changed files with 18 additions and 54912 deletions
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34
fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf
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@ -1,27 +1,27 @@
# Standard Configuration Example
[dir_path]
script_base = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/scripts/
benchmark_dir = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/benchmarks/FPGA_SPICE_bench/
yosys_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../yosys/yosys
odin2_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
cirkit_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/not_used_atm/cirkit
abc_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../yosys/yosys-abc
abc_mccl_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../abc_with_bb_support/abc
abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../abc_with_bb_support/abc
mpack1_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/not_used_atm/mpack1
m2net_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/not_used_atm/m2net
mpack2_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/not_used_atm/mpack2
vpr_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../vpr7_x2p/vpr/vpr
rpt_dir = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/results
ace_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/../ace2/ace
script_base = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/scripts/
benchmark_dir = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/benchmarks/FPGA_SPICE_bench/
yosys_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../yosys/yosys
odin2_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
cirkit_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/cirkit
abc_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../yosys/yosys-abc
abc_mccl_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../abc_with_bb_support/abc
abc_with_bb_support_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../abc_with_bb_support/abc
mpack1_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/mpack1
m2net_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/m2net
mpack2_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/mpack2
vpr_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../vpr7_x2p/vpr/vpr
rpt_dir = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/results
ace_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../ace2/ace
[flow_conf]
flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
vpr_arch = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK
vpr_arch = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
m2net_conf = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
power_tech_xml = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
power_tech_xml = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:

2
vpr7_x2p/vpr/picorv.sh
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@ -3,7 +3,7 @@
# Pack, place, and route a heterogeneous FPGA
# Packing uses the AAPack algorithm
./vpr picorv/arch.xml picorv/picorv_ace.blif --full_stats --nodisp --activity_file picorv/picorv_ace.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_picorv --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_picorv --fpga_verilog_print_top_testbench
./vpr picorv/arch.xml picorv/picorv.blif --full_stats --nodisp --activity_file picorv/picorv.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_picorv --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_picorv --fpga_verilog_print_top_testbench

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vpr7_x2p/vpr/picorv/picorv_ace.act
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35993
vpr7_x2p/vpr/picorv/picorv_ace.blif
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